Showing papers on "Phase noise published in 2007"

Effects of Phase Noise on OFDM Systems With and Without PLL: Characterization and Compensation

Abstract: In this paper, we propose an algorithm for suppressing intercarrier interference due to phase noise in coded orthogonal frequency division multiplexing (OFDM) systems. The algorithm approximates the phase-noise waveform by using a Fourier series approximation for the current phase-noise realization. Thereby, it cancels the effects of the phase noise beyond the standard common phase error correction used in contemporary OFDM standards. The algorithm requires that the correlation properties of the intercarrier interference are known. We calculate these properties in terms of the phase-noise spectral correlation matrix for both Wiener and Ornstein-Uhlenbeck phase-noise models, respectively. This modeling corresponds to a free-running oscillator, as well as a phase-locked loop realization of the local oscillator in orthogonal frequency division multiplexing transceivers. For both transceiver configurations, we investigate the performance of the proposed algorithm. It is demonstrated that the new algorithm achieves as much as one order of magnitude better performance in terms of packet/bit error rate when compared to a receiver with only the common phase error suppression.

The Quadrature LC Oscillator: A Complete Portrait Based on Injection Locking

Abstract: We show that the quadrature LC oscillator is best treated as two strongly coupled, nominally identical oscillators that are locked to the same frequency. Differential equations that extend Adler's description of locking to strong injection reveal the full dynamics of this circuit. With a simplifying insight, the analysis reveals all the modes of the oscillator, their stability, the effects of mismatch on quadrature phase accuracy, and through a novel use of the analysis, phase noise.

Low-noise fiber-laser frequency combs (Invited)

Abstract: We discuss experimental and theoretical aspects of a low-noise fiber-laser frequency comb, including the experimental configuration and the major contributions to the frequency noise and linewidth of the individual comb modes. Intracavity noise sources acting on the mode-locked laser determine the free-running comb linewidth and include environmental changes, pump noise, and amplified spontaneous emission (ASE). Extracavity noise sources acting outside of the laser typically determine the signal-to-noise ratio on the comb lines and include environmental effects, shot noise, and noise generated during supercontinuum generation. Feedback strongly suppresses these intracavity noise contributions, yielding a system that operates with comb linewidths and timing jitter below the quantum limit set by the intracavity ASE. Finally, we discuss correlations in the residual noise across a phase-locked comb.

Noise properties of superconducting coplanar waveguide microwave resonators

Abstract: The authors have measured noise in thin-film superconducting coplanar waveguide resonators. This noise appears entirely as phase noise, equivalent to a jitter of the resonance frequency. In contrast, amplitude fluctuations are not observed at the sensitivity of their measurement. The ratio between the noise power in the phase and amplitude directions is large, in excess of 30 dB. These results have important implications for resonant readouts of various devices such as detectors, amplifiers, and qubits. They suggest that the phase noise is due to two-level systems in dielectric materials.

20-Gb/s OFDM Transmission over 4,160-km SSMF Enabled by RF-Pilot Tone Phase Noise Compensation

Abstract: We introduce a novel method to compensate for local oscillator offset and phase-noise in coherent-OFDM systems and report continuously detectable transmission at 20-Gb/s data rate (25.8 Gb/s before coding) over 4,160-km SSMF without dispersion compensation.

An Optical Domain Combined Dual-Loop Optoelectronic Oscillator

Abstract: A dual loop optoelectronic oscillator (OEO) is able to effectively suppress the sidemodes in each single loop. In this paper, a dual-loop OEO scheme is reported. By utilizing a polarization-beam splitter and a polarization-beam combiner, the two loops are directly joined in the optical domain without adding any active electrical device. The laser's phase-to-intensity noise is discussed. We present free-running experimental results, which show a phase noise of -109 dBc/Hz at 10kHz away from the carrier (12 GHz) and a Q value of 1010 with a sidemode suppression ratio of 60 dB, which is improved by 30-50dB in the experimental comparison. Meanwhile, the experimental comparison indicates that no significant noise is introduced by this configuration

Continuous-time cross-phase modulation and quantum computation

Abstract: The weak nonlinear Kerr interaction between single photons and intense laser fields has been recently proposed as a basis for distributed optics-based solutions to few-qubit applications in quantum communication and computation. Here, we analyse the above Kerr interaction by employing a continuous-time multi-mode model for the input/output fields to/from the nonlinear medium. In contrast to previous single-mode treatments of this problem, our analysis takes into account the full temporal content of the free-field input beams as well as the non-instantaneous response of the medium. The main implication of this model, in which the cross-Kerr phase shift on one input is proportional to the photon flux of the other input, is the existence of phase noise terms at the output. We show that these phase noise terms will preclude satisfactory performance of the parity gate proposed by Munro et al (2005 New J. Phys. 7 137).

Coherent Optical Phase Transfer over a 32-km Fiber with 1 s Instability at 10 − 17

Abstract: The phase coherence of an ultrastable optical frequency reference is fully maintained over actively stabilized fiber networks of lengths exceeding 30 km. For a 7-km link installed in an urban environment, the transfer instability is $6\ifmmode\times\else\texttimes\fi{}{10}^{\ensuremath{-}18}$ at 1 s. The excess phase noise of 0.15 rad, integrated from 8 mHz to 25 MHz, yields a total timing jitter of 0.085 fs. A 32-km link achieves similar performance. Using frequency combs at each end of the coherent-transfer fiber link, a heterodyne beat between two independent ultrastable lasers, separated by 3.5 km and 163 THz, achieves a 1-Hz linewidth.

Compensation of Phase Noise in OFDM Wireless Systems

Abstract: Phase noise causes significant degradation in the performance of orthogonal frequency division multiplexing (OFDM)-based wireless communication systems. The presence of phase noise can reduce the effective signal-to-noise ratio (SNR) at the receiver, and consequently, limit the bit error rate (BER) and data rate. In this paper, the effect of phase noise on OFDM wireless systems is studied, and a compensation scheme is proposed to mitigate the common phase error and intercarrier interference (ICI) caused by phase noise. In the proposed scheme, the communication between the transmitter and receiver blocks consists of two stages. In the first stage, block-type pilot symbols are transmitted and the channel coefficients are jointly estimated with the phase noise in the time domain. In the second stage, comb-type OFDM symbols are transmitted such that the receiver can jointly estimate the data symbols and the phase noise. It is shown both by theory and computer simulations that the proposed scheme can effectively mitigate the ICI caused by phase noise and improve the BER of OFDM systems. Another benefit of the proposed scheme is that the sensitivity of OFDM receivers to phase noise can be significantly lowered, which helps simplify the oscillator and circuitry design in terms of implementation cost and power consumption.

Attosecond-resolution timing jitter characterization of free-running mode-locked lasers

Abstract: Timing jitter characterization of optical pulse trains from free-running mode-locked lasers with attosecond resolution is demonstrated using balanced optical cross correlation in the timing detector and the timing delay configurations. In the timing detector configuration, the balanced cross correlation between two mode-locked lasers synchronized by a low-bandwidth phase-locked loop is used to measure the timing jitter spectral density outside the locking bandwidth. In addition, the timing delay configuration using a 325 m long timing-stabilized fiber link enables the characterization of timing jitter faster than the delay time. The limitation set by shot noise in this configuration is 2.2×10−8 fs2/Hz corresponding to 470 as in 10 MHz bandwidth.

A Wide-Bandwidth 2.4 GHz ISM Band Fractional- $N$ PLL With Adaptive Phase Noise Cancellation

Abstract: A fast-settling adaptive calibration technique is presented that makes phase noise cancelling DeltaSigma fractional-N PLLs practical for the low reference frequencies commonly used in wireless communication systems. The technique is demonstrated as an enabling component of a 2.4 GHz ISM band CMOS PLL IC with a 730 kHz bandwidth, a 12 MHz reference, and an on-chip loop filter. In addition to the adaptive calibration technique, the IC incorporates a dynamic charge pump biasing technique to reduce power dissipation. The worst-case phase noise of the IC is -101 dBc/Hz and -124 dBc/Hz at 100 kHz and 3 MHz offsets, respectively, and the adaptive phase noise cancellation technique has a worst-case settling time of 35 mus . The IC is implemented in 0.18 CMOS technology. It measures 2.2 x 22 mm2 and its core circuitry consumes 20.9 mA from a 1.8 V supply.

An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL

Abstract: This paper reports an agile VCO frequency calibration technique and its application on a 10-GHz CMOS integer-N phase-locked loop. The proposed calibration method accomplishes efficient search for an optimum VCO discrete tuning curve among a group of frequency sub-bands. The agility is attributed to a proposed frequency comparison technique which is based on measuring the period difference between two signals. Other mixed-signal circuits are also developed to facilitate this approach. The PLL incorporating the proposed calibration technique is implemented in a 0.18-mum CMOS process. The measured PLL phase noise at 10 GHz is -102 dBc/Hz at 1-MHz offset frequency and the reference spurs are lower than -48 dBc. The PLL consumes 44 mW in the low-current mode. The calibration time is less than 4mus

Transformer-Based Dual-Mode Voltage-Controlled Oscillators

Abstract: In this brief, we propose to use a transformer-based resonator to build a dual-mode oscillator, e.g., a system capable of oscillating at two different frequencies without recurring to switched inductors, switched capacitors, or varactors. The behavior of the resonator configured as a one-port and a two-port network is studied analytically, and the dependence of the quality factor on the design parameters is thoroughly explored. These results, combined with the use of traditional frequency tuning techniques, are applied to the design of a wide-band voltage-controlled oscillator (VCO) that covers the frequency range 3.6-7.8 GHz. The performance of the designed VCO, implemented in a digital 0.13-mum CMOS technology, has been studied by transistor-level and 2.5D electromagnetic simulation (Agilent Momentum). A typical phase noise performance at 1-MHz offset of -104 dBc/Hz has been predicted, while the power consumption ranges from 1 to 8 mW, depending on the VCO configuration

All-Digital PLL With Ultra Fast Settling

Abstract: A fully digital frequency synthesizer for RF wireless applications has recently been proposed At its foundation lies a digitally controlled oscillator with sufficiently fine frequency resolution to avoid analog tuning The conventional phase/frequency detector, charge pump and RC loop filter are replaced by a time-to-digital converter and a simple digital loop filter When implemented in highly scaled digital CMOS processes, the proposed architecture is more advantageous over conventional charge-pump-based phase-locked loops (PLLs) since it exploits signal processing capabilities of digital circuits and avoids relying on the fine voltage resolution of analog circuits In this brief, we present novel techniques used in the all-digital PLL to achieve an ultra-fast frequency acquisition of <50 mus while maintaining excellent phase noise and spurious performance during transmission and reception This approach has been validated and incorporated in commercial single-chip Bluetooth and Global System for Mobile Communications radios realized in deep-submicrometer CMOS

Signal Design and Detection in Presence of Nonlinear Phase Noise

Abstract: In optical fiber transmission systems using inline amplifiers, the interaction of a signal and amplifier noise through the Kerr effect leads to nonlinear phase noise that can impair the detection of phase-modulated signals. We present analytical expressions for the maximum-likelihood (ML) decision boundaries and symbol-error rate (SER) for phase-shift keying and differential phase-shift keying systems with coherent and differentially coherent detection, respectively. The ML decision boundaries are in the form thetas(r) = c2r2 + c1r + c0, where thetas and r are the phase and the amplitude of the received signal, respectively. Using the expressions for the SER, we show that the impact of phase error from carrier synchronization is small, particularly for transoceanic links. For modulation formats such as 16-quadrature amplitude modulation, we propose various transmitter and receiver phase rotation strategies such that the ML detection is well approximated by using straight-line decision boundaries. The problem of signal constellation design for optimal SER performance is also studied for a system with four signal points.

Noise squeezing in a nanomechanical duffing resonator

Abstract: We study mechanical amplification and noise squeezing in a nonlinear nanomechanical resonator driven by an intense pump near its dynamical bifurcation point, namely, the onset of Duffing bistability. Phase sensitive amplification is achieved by a homodyne detection scheme, where the displacement detector's output, which has a correlated spectrum around the pump frequency, is down-converted by mixing with a local oscillator operating at the pump frequency with an adjustable phase. The down-converted signal at the mixer's output could be either amplified or deamplified, yielding noise squeezing, depending on the local oscillator phase.

A High-Performance CMOS Voltage-Controlled Oscillator for Ultra-Low-Voltage Operations

Abstract: In this paper, a novel circuit topology of voltage-controlled oscillators (VCOs) suitable for ultra-low-voltage operations is presented. By utilizing the capacitive feedback and the forward-body-bias (FBB) technique, the proposed VCO can operate at reduced supply voltage and power consumption while maintaining remarkable circuit performance in terms of phase noise, tuning range, and output swing. Using a standard 0.18-mum CMOS process, a 5.6-GHz VCO is designed and fabricated for demonstration. Consuming a dc power of 3 mW from a 0.6-V supply voltage, the VCO exhibits a frequency tuning range of 8.1% and a phase noise of -118 dBc/Hz at 1-MHz offset frequency. With an FBB for the cross-coupled transistors, the fabricated circuit can operate at a supply voltage as low as 0.4 V. The measured tuning range and phase noise are 6.4% and -114 dBc/Hz, respectively

RF and Microwave Transistor Oscillator Design

Abstract: About the Author. Preface. Acknowledgements. 1 Nonlinear circuit design methods. 1.1 Spectral-domain analysis. 1.2 Time-domain analysis. 1.3 Newton-Raphson algorithm. 1.4 Quasilinear method. 1.5 Van der Pol method. 1.6 Computer-aided analysis and design. References. 2 Oscillator operation and design principles. 2.1 Steady-state operation mode. 2.2 Start-up conditions. 2.3 Oscillator configurations and historical aspects. 2.4 Self-bias condition. 2.5 Oscillator analysis using matrix techniques. 2.6 Dual transistor oscillators. 2.7 Transmission-line oscillator. 2.8 Push-push oscillator. 2.9 Triple-push oscillator. 2.10 Oscillator with delay line. References. 3 Stability of self-oscillations. 3.1 Negative-resistance oscillator circuits. 3.2 General single-frequency stability condition. 3.3 Single-resonant circuit oscillators. 3.4 Double-resonant circuit oscillator. 3.5 Stability of multi-resonant circuits. 3.6 Phase plane method. 3.7 Nyquist stability criterion. 3.8 Start-up and stability. References. 4 Optimum design and circuit technique. 4.1 Empirical optimum design approach. 4.2 Analytic optimum design approach. 4.3 Parallel feedback oscillators. 4.4 Series feedback bipolar oscillators. 4.5 Series feedback MESFET oscillators. 4.6 High-efficiency design technique. 4.7 Practical oscillator schematics. References. 5 Noise in oscillators. 5.1 Noise figure. 5.2 Flicker noise. 5.3 Active device noise modelling. 5.4 Oscillator noise spectrum: linear model. 5.5 Oscillator noise spectrum: nonlinear model. 5.6 Loaded quality factor. 5.7 Amplitude-to-phase conversion. 5.8 Oscillator pulling figure. References. 6 Varactor and oscillator frequency tuning. 6.1 Varactor modelling. 6.2 Varactor nonlinearity. 6.3 Frequency modulation. 6.4 Anti-series varactor pair. 6.5 Tuning linearity. 6.6 Reactance compensation technique. 6.7 Practical VCO schematics. References. 7 CMOS voltage-controlled oscillators. 7.1 MOS varactor. 7.2 Phase noise. 7.3 Flicker noise. 7.4 Tank inductor. 7.5 Circuit design concepts and technique. 7.6 Implementation technology issues. 7.7 Practical schematics of CMOS VCOs. References. 8 Wideband voltage-controlled oscillators. 8.1 Main requirements. 8.2 Single-resonant circuits with lumped elements. 8.3 Double-resonant circuit with lumped elements. 8.4 Transmission line circuit realization. 8.5 VCO circuit design aspects. 8.6 Wideband nonlinear design. 8.7 Dual mode varactor tuning. 8.8 Practical RF and microwave wideband VCOs. References. 9 Noise reduction techniques. 9.1 Resonant circuit design technique. 9.2 Low-frequency loading and feedback optimization. 9.3 Filtering technique. 9.4 Noise-shifting technique. 9.5 Impedance noise matching. 9.6 Nonlinear feedback loop noise suppression. References. Index.

Design of Wide-Tuning-Range Millimeter-Wave CMOS VCO With a Standing-Wave Architecture

Abstract: The design of a wide-tuning-range millimeter-wave CMOS VCO is presented in this paper. In contrast to the conventional wideband topologies, a nonuniform standing-wave oscillator utilizing tapered gain elements, switched transmission lines and distributed varactors is employed to provide an extended output range with the coarse and fine frequency tuning. Due to the use of the transmission line architecture and the position-dependent amplitude of the standing waves, the loading effects of the varactors and the MOS switches can be alleviated, enabling the VCO to operate at higher frequencies. Using a 0.18-mum CMOS process, a 40-GHz VCO is designed and implemented. Consuming a DC power of 27 mW from a 1.5-V supply voltage, the fabricated circuit exhibits a frequency tuning range of 7.5 GHz with an output power level ranging from -13.6 to -4 dBm. The measured phase noise at 1-MHz offset is lower than -96 dBc/Hz within the entire frequency range. This work demonstrates the widest tuning range in percentage among the CMOS VCOs at millimeter-wave frequencies.

An Ultralow Phase Noise Coupled Optoelectronic Oscillator

Abstract: Ultralow jitter optical pulse sources are much needed in optical communications, optical sampling, and metrology applications. We report a coupled optoelectronic oscillator employing nonpolarization-maintaining components and an erbium-doped fiber amplifier that generates 9.4-GHz microwave signals with -150-dBc/Hz phase noise at 10- to 100-kHz offset, and 2-fs jitter (integrated in 100-Hz to 100-kHz range) optical pulses. To our knowledge, this is the lowest phase noise and time jitter reported in the same frequency range for such mode-locked laser-based systems

A 50-GHz Phase-Locked Loop in 0.13- $\mu$ m CMOS

Abstract: A 50-GHz charge pump phase-locked loop (PLL) utilizing an LC-oscillator-based injection-locked frequency divider (ILFD) was fabricated in 0.13-mum logic CMOS process. The PLL can be locked from 45.9 to 50.5 GHz and output power level is around -10 dBm. The operating frequency range is increased by tracking the self-oscillation frequencies of the voltage-controlled oscillator (VCO) and the frequency divider. The PLL including buffers consumes 57 mW from 1.5/0.8-V supplies. The phase noise at 50 kHz, 1 MHz, and 10 MHz offset from the carrier is -63.5, -72, and -99 dBc/Hz, respectively. The PLL also outputs second-order harmonics at frequencies between 91.8 and 101 GHz. The output frequency of 101 GHz is the highest for signals locked by a PLL fabricated using the silicon integrated circuits technology.

Phase Regeneration of NRZ-DPSK Signals Based on Symmetric-Pump Phase-Sensitive Amplification

Abstract: Symmetric-pump phase-sensitive amplification (SP-PSA) is investigated experimentally. Symmetric pump waves are derived using carrier-suppressed return-to-zero modulation. The SP-PSA is used for phase regeneration of a phase-noise degraded nonreturn-to-zero differential phase-shift keying signal, significantly improving signal quality

A Monolithic and Self-Referenced RF LC Clock Generator Compliant With USB 2.0

Abstract: A monolithic and self-referenced radio frequency (RF) LC clock generator that is compliant with USB 2.0 is demonstrated in a system-on-chip (SoC). This work presents the first successful approach to replacing an external crystal (XTAL), the crystal oscillator (XO) and the phase-locked loop for clock generation in an IC supporting USB 2.0 using a standard CMOS fabrication process. It is shown that the primary design challenges with the implemented approach involve maintaining high frequency accuracy and low jitter. Techniques for addressing both are shown. In particular, the presented architecture exploits the effects of frequency division and low far-from-carrier phase noise to achieve low jitter. From a 1.536 GHz temperature-compensated LC reference oscillator, coherent clock signals are derived at 96MHz for the SoC logic and 12 MHz for an on-chip full-speed USB PHY. Though self-referenced, approximately plusmn400ppm total frequency accuracy is achieved over process variations, plusmn10% variation in the USB power supply voltage and temperature variation from -10 to +85degC. Measured period and cycle-to-cycle jitter are 6.78 psrms and 8.96 psrms, respectively. Fabricated in a 0.35 mum CMOS technology, the clock generator occupies 0.22 mm2 and draws 9.5 mA from a 3.3-V supply, which is derived from the 5-V USB power supply

Wideband VCO With Simultaneous Switching of Frequency Band, Active Core, and Varactor Size

Abstract: As the tuning range of integrated LC-VCOs increases, it becomes difficult to co-design the active negative resistance core and the varactor size optimally for the complete frequency range. The presented VCO design solves this by adjusting the size of the negative resistance transistors with a switched active core, with the additional benefit that this reduces parasitics and hence allows to achieve better phase noise and an even higher tuning range. Also the VCO gain variations are counteracted by employing an analog varactor that can change in size. The implementation in 0.13-mum CMOS shows a tuning range from 3.1 to 5.2 GHz, with a power consumption varying accordingly from 7.7 to 2.1 mA from a 1.2 V supply. The measured phase noise is -118 dBc/Hz at 1 MHz from a 4-GHz carrier.

A Comprehensive Tool for Modeling CMOS Image-Sensor-Noise Performance

Abstract: Accurate modeling of image noise is important in understanding the relative contributions of multiple-noise mechanisms in the sensing, readout, and reconstruction phases of image formation. There is a lack of high-level image-sensor system modeling tools that enable engineers to see realistic visual effects of noise and change-specific design or process parameters to quickly see the resulting effects on image quality. This paper reports a comprehensive tool, written in MATLAB, for modeling noise in CMOS image sensors and showing the effect in images. The tool uses accepted theoretical/empirical noise models with parameters from measured process-data distributions. Output images from the tool are used to demonstrate the effectiveness of this approach in determining the effects of various noise sources on image quality

A 1-V 17-GHz 5-mW CMOS Quadrature VCO Based on Transformer Coupling

Abstract: A 1-V 17-GHz 5-mW quadrature voltage-controlled oscillator (QVCO) based on transformer coupling is presented. Transformer coupling between two LC tank oscillators is proposed to achieve quadrature outputs with improved performance in terms of high frequency, wide tuning range, low phase noise, and low power as compared to existing active-coupling QVCOs. Implemented in a 0.18-mum CMOS process, the proposed QVCO measures a frequency tuning range of 16.5% at 17 GHz and phase noise of -110 dBc/Hz at 1 MHz offset while consuming 5 mA from a 1-V power supply and occupying a core area of 0.37 mm2.

Fundamental Limitations of Continuous-Time Delta–Sigma Modulators Due to Clock Jitter

Abstract: We examine noise due to clock jitter in single-loop low-pass continuous-time delta-sigma (Delta Sigma) modulators (CT-DSMs) employing nonreturn to zero (NRZ) feedback digital-to-analog converters (DACs). Using the discrete-time version of the Bode sensitivity integral, we derive a lower bound on jitter noise and its relationship to the noise transfer function (NTF) of the modulator. We show that NTFs with optimized zeros result in lower jitter noise than those with all zeros at the origin. We give intuition to a recent observation (arrived through numerical optimization) that NTFs with peaking in their passbands have lower jitter noise than maximally flat NTFs. We propose a design procedure that minimizes the sum of the quantization and jitter noise. The arguments regarding Delta Sigma analog-to-digital converters are extended to Delta Sigma DACs and measurement results are presented.

40GHz Wide-Locking-Range Regenerative Frequency Divider and Low-Phase-Noise Balanced VCO in 0.18μm CMOS

Abstract: A 40GHz wide-locking-range frequency divider and a low-phase-noise VCO are implemented in 0.18mum CMOS technology. The frequency divider demonstrates a locking range of 10.6GHz with 0dBm input power while the VCO exhibits a phase noise of -108.65dBc/Hz at 1MHz offset. Each of the 2 circuits consumes 6mW from a 1V supply.

LED-based multi-wavelength phase imaging interference microscopy

Abstract: LED-based multi-wavelength phase imaging interference microscopy combines phase-shifting interferometry with multi-wavelength optical phase unwrapping. This technique consists of a Michelson-type interferometer illuminated with a LED. The reference mirror is dithered for obtaining interference images at four phase quadratures, which are then combined to calculate the phase of the object surface. The 2pi ambiguities are removed by repeating the experiment using two or more LEDs at different wavelengths, which yields phase images of effective wavelength much longer than the original. The resulting image is a profile of the object surface with a height resolution of several nanometers and range of several microns. The interferographic images using broadband sources are significantly less affected by coherent noise.