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Photomask

About: Photomask is a research topic. Over the lifetime, 7917 publications have been published within this topic receiving 54524 citations. The topic is also known as: photoreticle & reticle.


Papers
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Journal ArticleDOI
TL;DR: A rapid, high-precision method for localised plasma-treatment of bonded PDMS microchannels is demonstrated, revealing a well-defined micropattern with regions less than 100 µm along the length of the microchannel.
Abstract: A rapid, high-precision method for localised plasma-treatment of bonded PDMS microchannels is demonstrated. Patterned electrodes were prepared by injection of molten gallium into preformed microchannel guides. The electrode guides were prepared without any additional fabrication steps compared to conventional microchannel fabrication. Alignment of the “injected” electrodes is precisely controlled by the photomask design, rather than positioning accuracy of alignment tools. Surface modification is detected using a fluorescent dye (Rhodamine B), revealing a well-defined micropattern with regions less than 100 µm along the length of the microchannel.

48 citations

Patent
04 Jun 1992
TL;DR: In this paper, the first and second photomasks are expanded in the direction of the first pair of sides, while the rectangular opaque part of the second mask is expanded in direction the second pairs of sides.
Abstract: In a photoresist pattern formation by exposure using first and second photomasks, the first photomask has a transparent part, a rectangular opaque part having a first pair of sides and a second pair of sides, and a phase shifter, having a first edge crossing one of the first pair of sides, so that a part of the first edge is in the transparent part, and the second photomask has a transparent part, a rectangular opaque part corresponding to the rectangular opaque part of the first photomask, and a stripe-shaped opaque part corresponding to the first part of the first edge of the phase shifter. The rectangular opaque part of the first photomask is expanded in the direction of the first pair of sides, while the rectangular opaque part of the second photomask is expanded in the direction the second pair of sides. The amount of expansion is preferably not smaller than a misalignment tolerance.

47 citations

Journal ArticleDOI
TL;DR: In this paper, a CO2 laser scriber was used to perform direct writing ablation of quartz, borofloat and pyrex substrates for the development of microfluidic chips and cell chips.
Abstract: This paper uses a widely available CO2 laser scriber (λ = 10.6 µm) to perform the direct-writing ablation of quartz, borofloat and pyrex substrates for the development of microfluidic chips and cell chips. The surface quality of the ablated microchannels and the presence of debris and distortion are examined by scanning electron microscopy, atomic force microscopy and surface profile measurement techniques. The developed laser ablation system provides a versatile and economic approach for the fabrication of glass microfluidic chips with crack-free structures. In the laser writing process, the desired microfluidic patterns are designed using commercial computer software and are then transferred to the laser scriber to ablate the trenches. This process eliminates the requirement for corrosive chemicals and photomasks, and hence the overall microchip development time is limited to less than 24 h. Additionally, since the laser writing process is not limited by the dimensions of a photomask, the microchannels can be written over a large substrate area. The machining capability and versatility of the laser writing system are demonstrated through its application to the fabrication of a borofloat microfluidic chip and the writing of a series of asymmetric trenches in a microwell array. It is shown that the minimum attainable trench width is 95 µm and that the maximum trench depth is 225 µm. The system provides an economic and powerful means of rapid glass microfluidic chip development. A rapid cell-patterning method based on this method is also demonstrated.

47 citations

Patent
05 Sep 1997
TL;DR: In this article, a phase shift mask is used to suppress the error in dimensional accuracy based on a difference between pattern intervals in pattern formation using a phase-shift mask, by varying in the phases of the transmissive regions on both sides of light shielding regions by 180°.
Abstract: PROBLEM TO BE SOLVED: To suppress the error in dimensional accuracy based on a difference between pattern intervals in pattern formation using a phase shift mask. SOLUTION: At the time of forming rest patterns by using the phase shift mask 4 varying in the phases of the transmissive regions on both sides of light shielding regions by 180°, the widths of the light shielding regions 5A and light shielding regions 5B of the mask 4 are changed according to the intervals with the adjacent patterns at the time of the exposure of the positive resist 1, by which the fine patterns of the same line width are formed with the good dimensional accuracy. COPYRIGHT: (C)1998,JPO

47 citations

Patent
02 Jan 1981
TL;DR: In this article, the four adjacent corners of each circuit topography pattern on each photomask and each wafer chip area are set aside as designated information locations for the design and production of integrated circuit photomasks and integrated circuit devices.
Abstract: System for design and production of integrated circuit photomasks and integrated circuit devices wherein the four adjacent corners of each circuit topography pattern on each photomask and each wafer chip area are set aside as designated information locations. One of the designated information locations containing a two-dimensional rectangular array of locations for use as a mask sequence array and a second of the designated information locations containing a two-dimensional rectangular array of locations for use as an alignment key pattern array. The third designated information location serves as a product identification area which may include a manufacturer name and a product identification code. The fourth designated information location is adapted to serve as a test device area and may also serve as a part identification area in semiconductor processes employing a two layer metal interconnect system.

47 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202322
202281
202150
2020124
2019179
2018195