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Photomask

About: Photomask is a research topic. Over the lifetime, 7917 publications have been published within this topic receiving 54524 citations. The topic is also known as: photoreticle & reticle.


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Patent
05 Jun 1992
TL;DR: In this paper, a method of fabricating diffraction gratings where a photomask is arranged on a substrate which is coated with a photoresist, light is to be incident thereupon at an acute angle relative to the normal direction of the photOMask, and a bright/dark pattern is formed on said photoresists by the interference of the transmission light that has passed through the photomasks and the diffraction light.
Abstract: A method of fabricating diffraction gratings wherein a photomask is arranged on a substrate which is coated with a photoresist, light is to be incident thereupon at an acute angle relative to the normal direction of the photomask, and a bright/dark pattern is formed on said photoresist by the interference of the transmission light that has passed through the photomask and the diffraction light. The invention further deals with a photomask used for the above method.

42 citations

Patent
Han Woo-Sung1, Chang-jin Sohn1
16 Apr 1996
TL;DR: In this article, a photo mask is used to increase the capacitance of a capacitor by improving the proximity effect of a mask pattern, which is suppressed by forming an optical transmittance control film pattern in the transmission area between the individual portions of the mask pattern.
Abstract: A photo mask and method for manufacturing the same increase the capacitance of a capacitor by improving the proximity effect of a mask pattern. The photo mask includes a transparent substrate, an opaque mask pattern for defining an optical transmission area on the substrate, and an optical transmittance control film pattern for suppressing proximity effect in the optical transmission area. The proximity effect is suppressed by forming an optical transmittance control film pattern in the transmission area between the individual portions of the opaque mask pattern, so that the mask pattern shape can be exactly transferred onto a substrate.

42 citations

Patent
San-De Tzu1, Shih-Chiang Tu1, Chia-Hui Lin1
17 Nov 1997
TL;DR: In this paper, a method for interlayer corrections for photolithographic patterns that are reproduced on a wafer surface capable of correcting not only the optically induced proximity effect but also the process-induced proximity effect is presented.
Abstract: The present invention discloses a novel method for interlayer corrections for photolithographic patterns that are reproduced on a wafer surface capable of correcting not only the optically-induced proximity effect but also the process-induced proximity effect. In the method, a conventional optical proximity correction is first performed on a photomask, the corrected photomask is then used to produce a pattern on a wafer surface. The various critical dimensions bias values at a multiplicity of locations are then measured and fed back to the computer aided design data file for the photomask for producing patterns that are corrected for both optically-induced and process-induced proximity effect on a wafer surface.

42 citations

Journal ArticleDOI
TL;DR: A simple method to fabricate patterned organic/inorganic hybrid 1DPCs by top-down assisted photolithography, leading the as-prepared patterned 1D PCs to be effective sensors with high selectivity.
Abstract: Herein, we report a simple method to fabricate patterned organic/inorganic hybrid 1DPCs by top-down assisted photolithography. Versatile colorful pattern with different size and shape can be produced by selectively exposing the 1DPCs under UV light with predesigned photomask directly. The period change, especially the thickness variation of the top polymer layer, is the main reason for the colorful pattern generation. Because of the swelling property of the polymer layers, the pattern color can be modulated by introducing or taking off organic solvents, leading the as-prepared patterned 1DPCs to be effective sensors with high selectivity.

42 citations

Proceedings ArticleDOI
30 Dec 1999
TL;DR: In this article, the effect of mask repairs to resist pattern images for the binary mask case is discussed and the simulated resist lines by AIMS and VSS are both compared to SEM images of resist wafers qualitatively and quantitatively using CD verification.
Abstract: As advanced process technologies in the wafer fabs push the patterning processes toward lower k1 factor for sub-wavelength resolution printing, reticles are required to use optical proximity correction (OPC) and phase-shifted mask (PSM) for resolution enhancement. For OPC/PSM mask technology, defect printability is one of the major concerns. Current reticle inspection tools available on the market sometimes are not capable of consistently differentiating between an OPC feature and a true random defect. Due to the process complexity and high cost associated with the making of OPC/PSM reticles, it is important for both mask shops and lithography engineers to understand the impact of different defect types and sizes to the printability. Aerial Image Measurement System (AIMS) has been used in the mask shops for a number of years for reticle applications such as aerial image simulation and transmission measurement of repaired defects. The Virtual Stepper System (VSS) provides an alternative method to do defect printability simulation and analysis using reticle images captured by an optical inspection or review system. In this paper, pre- programmed defects and repairs from a Defect Sensitivity Monitor (DSM) reticle with 200 nm minimum features (at 1x) will be studied for printability. The simulated resist lines by AIMS and VSS are both compared to SEM images of resist wafers qualitatively and quantitatively using CD verification.Process window comparison between unrepaired and repaired defects for both good and bad repair cases will be shown. The effect of mask repairs to resist pattern images for the binary mask case will be discussed. AIMS simulation was done at the International Sematech, Virtual stepper simulation at Zygo and resist wafers were processed at AMD-Submicron Development Center using a DUV lithographic process for 0.18 micrometer Logic process technology.

42 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202322
202281
202150
2020124
2019179
2018195