Showing papers on "Physical design published in 1970"

An integrated circuit layout design program based on a graph-theoretical approach

Abstract: A graph-theoretical method, with wiring and placement problems considered simultaneously, will be discussed. The approach has resulted in the development of a computer program affording automatic layout design of single-layer IC chips on smallest possible areas.

Validation technique for integrated circuit manufacture

Abstract: A method of making an integrated circuit involves first placing the digital information characterizing the circuit into two separate and different formats. The latter are then transmitted to the manufacturing plant where they are compared. The two formats are then used to form respective artworks depicting a mask for making the integrated circuit. The artworks are then compared. The integrated circuit is then built from the information of one of said formats and is compared with the information in the other format.

A computer-aided approach to integrated circuit layout design

Abstract: The long turn-around times usually required by the design of integrated circuits can be greatly reduced if extensive use is made of digital computers. An investigation has been carried out by the authors to determine to what extent a computer can aid the designer in drawing the masks for integrated circuit fabrication starting from the circuit schematic. As a result of this investigation, a largely computerisable procedure for the layout of single metal layer, monolithic bipolar integrated circuits has been devised. Some steps of the procedure, which is described in this paper, have to be performed by the designer working at a display console; also the other steps can be monitored, and their results interactively modified, by the designer. A circuit partitioning technique makes the procedure fast and suitable for medium-power computers and low-precision displays, even when dealing with complex circuits.

Use of Test Patterns in Evaluating the Reliability of Integrated Circuits

Abstract: The reliability of a large scale integrated circuit chip is an aggregate of the reliability of each of its constituents. Therefore, the total failure rate is determined by simply evaluating the contribution of each constituent individually and independently. This is achieved by subjecting each part (e.g. a devrice or a conductor) to stress testing and subsequently translating its failure rate to machine-use conditions. Such tests, however, cannot be performed on a complex product chip because it is impossible to isolate a desired area. The only answer to this problem is to design a test pattern for each of the necessary tests. To illustrate the effectiveness of this vehicle, a special test chip designed to evaluate the reliability of Cogar's high performance read-write memory system is described in detail.

Analog Circuit Design Automation Tool Using Genetic Algorithms

Abstract: An investigation into the application of Genetic Algorithms (GA) for the design of electronic analog circuits is presented in this paper. In this paper an investigation of the use of genetic algorithms into the problem of analog circuits design is presented. In a single design stage, circuits are produced that satisfy specific frequency response specifications using circuit structures that are unrestricted and with component values that are chosen from a set of preferred values. The extra degrees of freedom resulting from unbounded circuit structures create a huge search space. It is shown in this paper that Genetic Algorithms can be successfully used to search this space. The application chosen is a LC all pass ladder filter circuit design. Key Words: Computer-Aided Design, Analog Circuits, Artificial Intelligence.

Machine aids to the design of ceramic substrates containing integrated circuit chips

Abstract: SPICED (System of Programs for Integrated Circuit Equipment Design) is a set of machine aids to the design of ceramic substrates containing integrated circuit chips. The major functions are to build and maintain a descriptive data file, place all chips, interconnect the chips with thin film using air-insulated beam type crossovers1 where necessary, document the design, prepare the artmaster, and produce test data to verify that crossovers are not shorted or opened.

Digital network design aids - an integrated approach

Abstract: The extension of human capabilities in procedural tasks by use of computer processing is well established. Significant effort has been expended within the past decade to apply this processing capability to the tasks within engineering design.1 This paper describes the integrated approach adopted by Collins Radio Company in the development and application of computer aids to the design of digital networks.The digital networks include those networks, systems, or circuits which exhibit discrete logic states and have waveforms that may be assumed idealized with zero rise and fall times. The design aids include simulation, production test generation, and layout.The simulation algorithms provide design verification, computation of production test input/output data, trade-off analysis and timing and loading analysis. The test generation algorithms determine a set of inputs to a unit and the associated outputs for these inputs which can be used for production test of the unit. The layout algorithms provide parts placement, partitioning, pin assignment and interconnect solutions for physical implementation of the circuitry.The simulation, test generation and layout algorithms operate on a common set of data which is inputted to the processor system by the designer. This set of data is added to as simulation, test generation and layout are completed. The resultant evolved set can then comprise a functional specification of the unit.