Showing papers on "Physical design published in 1974"

Macromodeling of integrated circuit operational amplifiers

Abstract: A macromodel has been developed for integrated circuit (IC) op amps which provides an excellent pin-for-pin representation. The model elements are those which are common to most circuit simulators. The macromodel is a factor of more than six times less complex than the original circuit, and provides simulated circuit responses that have run times which are an order of magnitude faster and less costly in comparison to modeling the op amp at the electronic device level. Expressions for the values of the elements of the macromodel are developed starting from values of typical response characteristics of the op amp. Examples are given for three representative op amps. In addition, the performance of the macromodel in linear and nonlinear systems is presented. For comparison, the simulated circuit performance when modeling at the device level is also demonstrated.

Automated network design with optimal tolerances

Abstract: A new approach to network design to obtain optimal parameter values simultaneously with an optimal set of component tolerances is proposed. An automated scheme could start from an arbitrary initial acceptable or unacceptable design and under appropriate restrictions stop at an acceptable design which is optimum in the worst case sense for the obtained tolerances.

An iterative technique for printed wire routing

Abstract: Wires are routed allowing crossings in the initial layout. By spreading the wires and increasing the crossover penalties, fewer crossings occur on each iteration until a crossing free layout is achieved.

DC testing of integrated circuits and a novel integrated circuit structure to facilitate such testing

Abstract: In integrated semiconductor circuits comprising a plurality of active and passive devices interconnected by conductive means into a selected circuit configuration, the improvement wherein said circuit configuration is arranged so as to be free of possible paths displaying reactance which would be alternative to selected substantially reactanceless paths terminating in critical circuit nodes in the event of structural failure of one of said reactanceless paths, whereby the DC testing of the integrated circuit is not affected by such alternative paths.

Analysis and design of temperature stabilized substrate integrated circuits

Abstract: A generalized temperature-stabilized substrate integrated circuit system containing heat sources and temperature sensors which are distributed in an arbitrary way in two-dimensions over the surface of the chip is analyzed. A computer-aided technique for optimum placement of these components at the layout stage so as to achieve zero nominal temperature coefficient in the performance parameter of interest is described, and other practical design considerations, such as optimum choice of stabilized chip temperature, are considered. The application of this technique is illustrated with the design of a precision temperature stabilized voltage reference supply. Experimental results from this circuit are presented.

Design automation of MOS artwork

Abstract: Without sophisticated design automation techniques, the increasing complexity of custom MOS circuits requires long design cycles and large investments. Usually only a few parts of each type of custom MOS circuit are required, and the design cost becomes a significant portion of the cost of the manufactured parts. These facts prohibit many companies from using custom MOS circuits in their products. Design automation applied to custom MOS circuit design significantly lowers the total design cost by shortening the design cycle, reducing labor, and allowing error free designs to be produced before being manufactured. This makes possible the use of custom MOS circuits, even when only a few parts are required.

A three‐terminal piecewise‐linear modelling approach to dc analysis of transistor circuits

Abstract: The simulation of electronic circuits by computer has become an important part of present-day circuit analysis and design, especially in the area of integrated circuit design. One of the goals in computer simulation of integrated circuits is to have a program ‘package’ for which the input consists of chip fabrication data (mask dimensions, impurity profiles, material data such as carrier lifetimes) and the output displays the complete circuit response. This requires both an efficient modelling approach and a fast circuit analysis method. In this paper a simulation method is described which generates dc responses (in the form of operating points or transfer characteristics) of transistor circuits directly from physical parameter data. The basis of the method is a two-dimensional piecewise-linear approach to the dc modelling of bipolar transistors. The model is directly used in a piecewise-linear circuit analysis program to simulate the dc response of a given circuit.

Engineering Data Management System (EDMS) for computer aided design of digital computers

Abstract: The current technology lets a DA system handle the data on various design levels such that pure logical, logical and physical and pure physical information are mixedly used on a PCB design.The design process has not been uniformly carried out, such that the simulation of digital system, the routing and a PCB and a unit design has been carried out at the same time, and made the operation and the management be more difficult and complicated. Therefore, only extention of traditional DA systems tends to be difficult to cope with these situations.We have studied these problems and developed Engineering Data Management System - EDMS - so as to be open-ended general purpose DA system which can meet with the future innovation of the technology.

An experimental comparison of force directed placement techniques

Abstract: Force-directed placement algorithms are experimentally compared using several sample problems. Significant differences are noted in the computational efficiency of the algorithms, and in the relationship of the placement solution to the routability of the resulting board.

MAP: A user-controlled automated Mask Analysis Program

Abstract: The Mask Analysis Program is a totally general and application independent FORTRAN program for the analysis and manipulation of graphic data. It is particularly useful in integrated circuit design analysis.

Cad of masks and wiring

Abstract: • A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website. • The final author version and the galley proof are versions of the publication after peer review. • The final published version features the final layout of the paper including the volume, issue and page numbers.

A quality measure for LSI components

Abstract: Large-scale integration components are subjected to testing based on stuck fault modeling. Stuck fault testing often does not provide patterns for all possible stuck conditions that can exist in a circuit. Because of the incompleteness of test coverage, a new quality measure is needed-one that is not based on sample inspection. Such an LSI quality measure is described in this paper. The LSI quality measure can be related to component yield and is based on the stuck fault testing coverage, the physical circuit design layout, and the rate of faults occurring on elemental circuit geometries. The concept of the LSI quality measure is illustrated in this paper by an example. Starting from a block diagram and an assumed stuck fault coverage, some stuck faults are assumed to remain untested. For these untested faults, the elemental circuit geometries in a corresponding FET circuit layout are determined, and the quality measure calculated. Common sense rules are offered for optimizing the quality and lowering its cost impact on higher levels of assembly.

GERMINAL: Towards a general and integrated system for computer aided design

Abstract: In 1969 a symposium involving CAD took place in Davenport -USA- We quote from the report [1]: “we felt that the confusion regarding the definition of the term “CAD” was, in itself, a characterization of the State-of-the-art” Four years later a certain confusion still remains This is an evidence of the fact that the field of computer-aided design is still largely unexploredWe have determined three steps in the development of CAD as of the present time In the first step, computers were used to execute a set of routines, each of them defined to work autonomously and to perform a single task This task contributed to the evaluation or determination of a particular aspect of a design process in any field Because there had been an opportunity to use a computer other than in batch mode, and because it was found interesting to have the possibility of communicating between several different programs which contribute to the same design process, improvement on the first step had been attempted

“A minicomputer-based logic-fault simulator”

Abstract: A unit-gate-delay three-valued-logic parallel fault simulator handles up to 1500 gates on a minicomputer with 16K core. Capabilities, programming novelties, and performance statistics will be presented.

An improved graph-theoretic model for the circuit layout problem

Abstract: The use of topological methods for the circuit layout problem is surveyed first. In the second part an improved model is proposed, which allows pin and gate assignment in function of the layout.

Invited: The here and now of computer-aided circuit design

Abstract: Today, CACD can be cost-effective in IC design. Simulation capabilities and modeling provisions of several widely available programs will be compared. Examples from linear and digital circuit design will be offered to illustrate typical results, costs and difficulties.

A simple, efficient design automation processor

Abstract: This paper describes a design automation processor which was developed as a design, pedagogical, and research tool at Vanderbilt University. The processor was intended to provide a design aid for the development of small scale switching systems (e.g., controllers, interfaces, etc.). These designs were intended to be realized using TTL logic and TI #218763 wire-wrap boards. While the initial implementation was limited to this technology, flexibility for growth was included in the system design. In addition, although the system is primarily designed for wire-wrapped technology, a wire router is included to provide a printed circuit capability.

Microprogramming Design support System

Abstract: Recently microprogramming technique has been used in many areas such as computers, peripheral devices, terminals, and so on. Control word organization varies with each control equipment. Also integrated control technique or centralized control technique requires the integration of microprograms depending on system configuration. Therefore generalized and sophisticated design support system has been desired. Microprogramming Design support System, MDS, has been developed to meet such requirements.

An integrated circuit layout design system

Abstract: An integrated circuit layout design system is presented. The system is effectively combined with a combinatorial optimization technique and man/machine interaction. This optimization technique allows wiring and placement of components to be determined simultaneously. By means of a c.r.t. display, the layout design of an integrated circuit chip is finally improved.

Automated transistor characterization and parameter generation for linear IC design

Abstract: An integrated CAD facility for process-oriented circuit design will be described. Process, device and circuit simulators, which include multidimensional and high-level effects, comprise the facility, presently specialized for linear IC design.

A Precision Digital Phase Generator

Abstract: The design of a digital phase generator which produces two outputs of frequency f, between which the phase shift can be varied from 0 to 360° in steps of 1°, from an input frequency of 360f, is described. The system design is described in detail. The circuit design and the choice of the circuit elements are discussed. Fast logic elements have been used in the construction of the instrument. A brief analysis of the performance of the system is also given. From the experimental results, which agree with the calculated performance, it is found that the accuracy of the system varies and is as high as 0.05 percent when the phase shift is 359°. The accuracy of the system is limited only by the propagation delays of the logic elements used and therefore can be improved by using faster logic elements.

A "graphics window" to a data base for electronic system design

Abstract: This paper will explore the use of "Graphics Windows" to data bases used in the physical design of electronic equipment. The common characteristics of connectivity oriented data bases will be briefly reviewed. Then the concept of a graphics window on this type of data base will be defined and several examples given. This is followed by a detailed example of a graphics window used for editing printed circuit boards. The paper is concluded with a brief discussion of experiments conducted with the window which are aimed at developing display techniques useful for interactive design.

Control of Stray Effects in Hybrid Microcircuit Design

Abstract: Performance of high speed digital and analog hybrid microcircuits almost always differs from the ideal circult design and from a breadboard or PC board version of the same circuit to some extent due to differences in stray effects. This paper discusses computer analysis of inductive and capacitive coupling between various thick-film microcircuit elements in both conventional and multilayer chip and wire hybrid microcircuits. Also discussed are extended circuit modeling techniques for including stray effects of a given microcircuit layout in the computer analysis of the circuit design.

A partitioning technique for LSI chips including a bunching algorithm

Abstract: This paper discusses a partitioning technique which initially orders circuits according to a scoring mechanism, and thus uses a two-stage interchange technique to arrive at a final partition.

RTL - The firmware Design Automation system

Abstract: The development of firmware controlled devices poses several new requirements on Design Automation Because firmware is central to system design and reflects heavily on system speed and cost, the basic assembly parameters change after during the early design phases It is necessary to have an automation system which is able to react to design changes without reprogramming of system components Thus the standard approach of simulating firmware with a special purpose language and a special purpose assembler or assembler/simulator is no longer practical This paper discusses a general solution to the several requirements of firmware design