Showing papers on "Physical design published in 1982"

MEDUSA--A Simulator for Modular Circuits

Abstract: A modular circuit is defined as a combination of a certain number of k-modules, which are embedded in a carrier network The modules may represent subcircuits of varying complexity down to single devices Such modular circuits lend themselves to a description by a system of modular equations MEDUSA is a user-oriented simulator which utilizes system modularity during the simulation process itself, ie, for solving the underlying equations This approach enables the consistent numerical solution of both the basic equations of several bipolar devices and the network equations for a circuit environment Hence, MEDUSA in its present state is a merged device-circuit simulator meeting simultaneously the requirements of device and circuit design

Design centering by yield prediction

Abstract: Design centering is an appropriate design tool for all types of electrical circuits to determine the nominal component values by considering the component tolerances. A new approach to design centering will be presented, which starts at the initial nominal values of the circuit parameters and improves these nominal values by maximizing the circuit yield step by step with the aid of a yield prediction formula. Using a variance prediction formula additionally, the yield maximization process can be established with a few iteration steps only, whereby a compromise between the yield improvement and the decrease in statistical certainty must be made in each step. A high-quality interactive optimization method is described which allows a quantitative problem diagnosis. The yield prediction formula is an analytical approximation based on the importance sampling relation. This relation can also be used to reduce the sample size of the necessary Monte Carlo analyses. Finally the efficiency of the presented algorithm will be demonstrated on a switched-capacitor filter.

Global Wiring on a Wire Routing Machine

Abstract: A new global wiring algorithm designed for implementation on special purpose physical design machines is described. This algorithm computes more accurate estimates of wiring channel demand and supply than other known algorithms. It also makes better use of this information in determining wire routes. By exploiting the parallel processing capability of an interconnected array of microcomputers, the global wiring is completed effectively and quickly even for large chips.

Hybrid circuit design and manufacture

Abstract: Hybrid circuit design and manufacture , Hybrid circuit design and manufacture , مرکز فناوری اطلاعات و اطلاع رسانی کشاورزی

A Design Centering Algorithm for Nonconvex Regions of Acceptability

Abstract: Random variations inherent in any fabrication process may result in very low production yield. This is especially true in the fabrication of integrated circuits. Several methods have been proposed to help the circuit designer minimize the influence of these random variations. Most of these methods are deterministic and try to maximize yield by centering the nominal value of the designable parameters in the so-called region of acceptability. However, these design centering techniques require an assumption of convexity which is not valid in many real design situations. To overcome this problem a new convergent method is proposed which is based on the sequential solution of subproblems for which the convexity assumption is valid. A practical implementation of the algorithm is shown by examples to be computationally efficient.

Computer-aided design: Automating chip layout: New computer-based layout systems are faster than their human counterparts and produce designs that almost match those created manually

Abstract: Discusses how new computer-based layout systems are being used more and more to design LSIs. The new systems are faster than human designers and produce systems almost as good at reduced cost. Four basic methods in use are described.

CAD Systems for IC Design

Abstract: As integrated circuit (IC) complexities increase, many existing computer-aided design (CAD) methods must be replaced with an integrated design system to support very large scale integrated (VLSI) circuit and system design. The framework for a hierarchical CAD system is described. The system supports both functional and physical design from initial specification and system synthesis to simulation, mask layout, verification, and documentation. The system is being implemented in phases on a DECSystem 20 computer network and will support evolutionary changes as new technologies are developed and design strategies defined.

A Symbolic Design System for Integrated Circuits

Abstract: As integrated circuit design has become increasingly complex, the need for more effective data description techniques has become critical. Design verification from mask artwork data alone can consume vaste amounts of computer time for VLSI circuits, if it can be performed at all. The use of a symbolic design description, which allows the designer or synthesis program to express circuit structure as well as maintain full connectivity information, can reduce dramatically the burden placed on the verification tools. This paper describes a symbolic design system, its associated data manager, its color graphics viewport manager, and its application to a variety of design methods. The data manager can store a variety of representations of the design, including simulation data, geometric layout, symbolic layout, and schematic diagrams. The viewport manager can manage a number of viewports concurrently and the use of a model frame buffer allows it to function easily on a variety of graphics terminals and hard-copy devices. The system is designed with an engineering work station in mind.

Complex integrated circuit design strategy

Abstract: Presents a design strategy for VLSI circuits based on the use of a floor plan as an evaluation and management guide for the design of a future circuit. This approach is widely used in the microelectronic industry and allows global optimizations, which are the key to both high density and design reliability, by improving the assembly and the direct wiring of the blocks. The efficiency of such an approach may be improved by the use of a topological evaluator. This tool will give an evaluation of the shape, size, and connections of the main blocks from their specifications. It is able to take into account the topological constraints given by the designer in order to improve the assembly and connectivity of the floor plan. This tool is composed of a set of evaluation routines for the different kinds of functional blocks constituting a VLSI circuit and a supervisor for dialogue with the user.

A Bus Router for IC Layout

Abstract: This paper describes a bus router that is part of a custom IC mask layout system called CIPAR. CIPAR works with rectangular building blocks of arbitrary dimensions. The router is designed specifically to handle power and ground buses. It can route these nets completely on one metal layer. The router also automatically calculates and tapers the bus path width based on current requirements specified in the input circuit description.

Modular Description/Simulation/Synthesis using DDL

Abstract: With the increased complexity of integrated circuits, a true top-down methodology is mandatory in their design. A construct that enables a modular description of a system design is added to DDL. The Translator, Simulator and Synthesis Software has been modified to retain this modularity throughout the design cycle. These enhancements allow a multi-level simulation and multi-technology synthesis of an integrated circuit.

A Design Methodology based upon Symbolic Layout and Integrated CAD Tools

Abstract: This paper describes one of the new methodologies for IC design currently being used at the CNET. The main features detailed are the symbolic layout method called MDMOS and the integrated CAD system CASSIOPEE. Its most significant advantages are design safety, elimination of costly and inefficient checks and supply of technical specifications which are always up-to-date. This methodology is described in its entirety starting from the logical description, and including all stages up to masks generation.

Exploitation of Hierarchy in Analyses of Integrated Circuit Artwork

Abstract: The artwork of integrated circuit designs is usually available in the form of hierarchical specification, in which each cell is made up of geometric primitives and references to other cells Such a representation captures structure and repetition in the layout As the realizable device count of integrated circuits increases with every passing year there is an increasing trend towards structured design approaches that result in even greater degrees of regularity and hierarchy Yet the typical approach to design verification requires fully instantiating the hierarchical representation thereby removing all structure from it Consequently much time is spent repeating the analyses of identical cells This paper presents a general approach to exploiting hierarchy and repetition in the analysis of integrated circuit designs, and includes details of a circuit extraction algorithm that uses this approach The implementation and performance of such a system is also described

Statistical modelling for integrated circuits

Abstract: This contribution attempts to survey two alternative approaches to the characterisation of ICs for statistical design. The first is based on a direct description of the distributions of the electrical parameters of standard device models, while the second approach starts from distributions of more fundamental processing variables, and will be dealt with in more detail. After considering ways to ensure that the circuit designer's distributions are up-to-date with the process, a structure is proposed for modelling the important matching effects found in an IC. Finally, conclusions for circuit design are drawn.

Portable design rules for bulk CMOS

Abstract: It is pointed out that for the past several years, one school of IC designers has used a simplified set of nMOS geometric design rules (GDR) which is 'portable', in that it can be used by many different nMOS manufacturers. The present investigation is concerned with a preliminary set of design rules for bulk CMOS which has been verified for simple test structures. The GDR are defined in terms of Caltech Intermediate Form (CIF), which is a geometry-description language that defines simple geometrical objects in layers. The layers are abstractions of physical mask layers. The design rules do not presume the existence of any particular design methodology. Attention is given to p-well and n-well CMOS processes, bulk CMOS and CMOS-SOS, CMOS geometric rules, and a description of the advantages of CMOS technology.

A Layout Synthesis System for NMOS Gate-Cells

Abstract: A synthesis system for the automatic layout of NMOS gate cells is described. The cells are based on multigrid cell models and are intended for use as part of a chip synthesis system. An outline of the basic concepts of a CAD procedure for the layout synthesis of such cells is given. The main objective is to generate correct and compact cells with controlled growth in area when subjected to modified speed requirements. Both the layout synthesis procedure itself and algorithms are discussed.

A highly automated semi-custom approach for VLSI

Abstract: The structured approach is aimed at optimizing the chip physical design while keeping design resources and time at a reasonable level. The logic is partitioned into data flow logic and control logic; a specialized physical structure has been defined to match the data flow logic structure and the gate array has been chosen for control logic implementation, both physical structures being customizable. A general purpose library and a set of design automation programs have been developed to allow fast physical design of the functional partitions according to the applications. A bipolar 16-bit slice microprocessor has been designed with this approach and built; compared to the widely used gate array chip implementation, it shows an improvement of 2 in gate density and 1.5 in power dissipation. The physical design of this 2000 gates chip took only two months.

A Design System Approach to Data Integrity

Abstract: Due to the nature of chip design, the Very Large-Scale Integrated (VLSI) design data base is constantly changing. The changes may be caused by logical or physical design activities. In either case, there is a need to make sure that no matter what happens, the data base remains valid. This paper discusses a system which uses an Automated Data Integrity Technique (AUDIT) to eliminate errors prior to hardware build.

SDW MOSFETs in LSI analog circuit design

Abstract: Single-device-well (SDW) MOSFETs are based on merging two devices-a surface and a buried MOSFET to share the same device well and the same gate. They offer flexible circuit structures in the design of LSI analog circuit blocks with a circuit area saving which ranges typically from 30-60 percent. The authors discuss in detail the design and the analysis of SDW source followers and difference stages. It also gives examples of SDW circuit configurations for current sources, potential dividers, and output stages.

D4 Digital Channel Bank Family: Digital terminal physical design

Abstract: This article describes the physical design of the D4 and related SLC™-96 subscriber loop carrier system digital terminals. A detailed description of the bay, channel bank, and plug-in designs is also included, along with other very important considerations such as thermal design, manufacturability, and the effective use of hybrid integrated circuit technology. The D4 was designed as a system that was significantly smaller, used less power, and had a lower cost than previous digital terminals. These objectives were realized by using the latest technology and the optimal physical design format. Since these are relatively high-production terminals, the basic design has been aggressively reduced in cost and has proliferated with expanding D4 and SLC-96 subscriber loop carrier terminal capabilities, lightguide applications, and the use of the D4 hardware in other systems.

Measurements of a VLSI Design

Abstract: This paper presents data about three facets of a recently-completed VLSI design containing 45000 transistors. The first set of data describes the mask-level features of the circuit, from which it is seen that almost all features have at least one small dimension. The second set of data analyzes the hierarchical cell structure used by the designers to specify the circuit. The measurements show that composite cells have a different structure from primitive cells, and that, outside of arrays, cells are rarely re-used. The third set of data concerns the usage of an interactive layout program during the circuit's design. In spite of the circuit's size, the most frequently invoked commands were all simple.

Integrated signal processing circuit

Abstract: Disclosed is an integrated circuit in which more than two kinds of information outputs are superimposed on the same output terminal and the output level of an output terminal is varied in more than three steps in order to apply many information outputs to a small number of output terminals and transmit the operation state of the internal circuit externally. The structure of the integrated circuit is simplified, because the number of terminals in the integrated circuit and the number of connection wires between internal and external circuits can be reduced.