Showing papers on "Physical design published in 1983"

Integrated circuit yield statistics

Abstract: The random failure statistics for the yield of mass-produced semiconductor integrated circuits are derived by considering defect and fault formation during the manufacturing process. This approach allows the development of a yield theory that includes many models that have been used previously and also results in a practical control model for integrated circuit manufacturing. Some simpler formulations of yield theory that have been described in the literature are compared to the model. Application of the model to yield management are discussed and examples given.

Palladio: An exploratory environment for circuit design

Abstract: Palladio is a circuit design environment for experimenting with methodologies and knowledge-based, expert-system design aids. Its framework is based on several premises about circuit design: (1) circuit design is a process of incremental refinement; (2) it is an exploratory process in which design specifications and design goals coevolve; and (3) most important, circuit designers need an integrated design environment that provides compatible design tools ranging from simulators to layout generators, that permits specification of digital systems in compatible languages ranging anywhere from architectural to layout, and includes the means for explicitly representing, constructing, and testing such design tools and languages. The Palladio environment is part of a growing trend toward creating integrated design environments and away from isolated design aids. Recently several commercial computer-aided engineering (CAE) workstations have emerged, providing multiple-level, circuit-specification entry systems and integrated analysis aids. Integrated circuit designers have a special need for such workstations because of the complexity of large integrated circuits and the high costs of prototyping them.

CAzM: A circuit analyzer with macromodeling

Abstract: A prototype circuit simulator, based on a revised formulation of the circuit equations, is described. The formulation is based on functional models of active elements, which can be derived from either equivalent-circuit or black-box models. The implementation is oriented towards the simulation of digital MOS circuits and takes advantage of the special form of such circuits. Some of the implementation issues are discussed, particularly the hierarchical structuring of the circuit equations and the use of splines to facilitate macromodeling; continuation methods for computing transfer curves are also discussed. Finally, the results of computational experiments are presented.

Process for forming complementary integrated circuit devices

Abstract: A process for forming chanstops in complementary transistor integrated circuit devices which involves only a single extra masking step yet permits close control of the doping in the chanstops. The process is advantageously used starting with a twin-tub structure for forming CMOS integrated circuit devices.

Hierarchical design methodologies and tools for VLSI chips

Abstract: Hierarchical design methods are considered to be a means of managing the VLSI design problem. This paper will consider why this problem exists and discuss alternative means that can be used to arrive at a solution. The merits of design methodologies, with emphasis on hierarchical techniques, will be compared with those of automated design approaches. The discussion of hierarchy will lead to the conclusion that the method requires formal abstraction facilities in order to be effective. Hierarchical design methods permit the creation of a new generation of CAD programs that can both give a designer better support and can be much more efficient than the present generation of tools. An example of such a tool, VOILA, will be given.

OYSTER: a study of integrated circuits as three-dimensional structures

Abstract: This paper presents a design for a software system (OYSTER) for the parametric simulation and analysis of the fabrication steps of very large scale integrated circuit devices. The system is based on a solid geometric modeling approach in which the component parts of an integrated circuit are represented at any step as three-dimensional solid objects in a geometric data base. The simulation of a fabrication step transforms the data base representation of the geometry and the relations among component parts from their state before the step to their state after the step. At any step, and particularly after the final step, the component parts may be analyzed automatically to determine geometric, mechanical, thermal, and electrical properties. Statistical effects may be incorporated to allow investigation of alignment tolerance build-up and yield. A prototype study is described in which an existing geometric modeling system is used to transform a set of planar masks for an FET device through 28 process steps into 3-D models which are used to compute device capacitances.

Electrical Design of a High Speed Computer Packaging System

Abstract: A methodology for optimizing the design of an electrical packaging system for a high speed computer is described The pertinent parameters are first defined and their sensitivities are derived so that the proper design trade-offs can ultimately be made. From this procedure, a set of rules is generated for driving a computer-aided design (CAD) system. Finally there is a discussion of design optimization and circuit and package effects on machine performance.

Automatic hardware synthesis

Abstract: The complexity of the circuit that can fit on an integrated circuit (IC) chip has reached the level of a million transistors with the advent of Very-large-Scale Integration (VLSI). Several automatic synthesis systems have evolved that "aid" the human designer in managing this complexity. This paper surveys such efforts. The synthesis is viewed as the process of transforming a high-level design specification into a lower level design specification that includes more structural details, leading to the physical design of the IC. The characteristics of ten automatic synthesis systems are summarized.

Differential cascode current switch (DCCS) master slice for high efficiency/custom density physical design

Abstract: A master slice designed for storage in sub-stock and for use in producing very large scale integrated circuits in an automated placement and wiring environment is described that is made from a semiconductor electronic quality wafer and the like, the wafer having a "brickwall" set of active elements such as bipolar transistors together with associated passive elements arranged in a master slice image. The master slice is personalized using optimization techniques including among other steps, the steps of modeling, developing and validating primitive logic diagrams, determining element placement by a Monte Carlo simulated annealing method, selecting hierarchical wiring by a maze runner algorithm and further validation.

Computer-produced circuit board

Abstract: A method of manufacturing a circuit board from a copper clad board comprises the steps of designing a circuit configuration of the circuit board on a computer-aided design system and then determining a desired circuit configuration outline on the computer-aided design system from the circuit configuration. The desired circuit configuration outline is provided to a computer-aided machining system which controls a laser, milling machine and the like to remove conductive material along the outline, leaving conductive material formed adjacent the removed material as the circuit configuration.

A Vertically Integrated VLSI Design Environment

Abstract: A VLSI design system called VIVID is the heart of a newly developed, vertically integrated design environment. This environment provides support for all phases of design from high-level system specification through on-site fabrication to construction of prototype systems. Key features already implemented include: the use of a circuit description language at the level of a silicon assembler; a fast, highly interactive combination floor planner and layout editor; fast interactive timing simulation; and layout made free from design-rule constraints by the use of virtual-grid compaction. Functional specification and verification, automated routing, standard cell layout, and semi-automated layout from schematics are being built upon the foundation formed by VIVID.

Database design: a survey of logical and physical design techniques

Abstract: This paper summarizes a study conducted by the authors which investigated methodologies presently available to assist in the process of database design. The study also examined the current status of database design in a variety of organizations (manufacturing, financial government, service, and other). The findings show that familiarity with logical design methodologies is fairly high, but that actual use of these techniques is quite low. Familiarity with physical design methodologies is less than that with logical design methodologies and so too is actual use of these physical techniques.

Methodical aspects of logic synthesis

Abstract: The increasing complexity of integrated circuits demands improved design quality. For system developments with small- or medium-scale integrated circuits, successive steps of the design process are interconnected loosely. Therefore, design checks, tests, and even redesigns could be performed without affecting large fractions of the overall design. With large scale integration (LSI) and especially very large scale integration (VLSI), the situation has changed drastically. The technological capability of these techniques allows designers to put a whole digital system on a few chips or even on one single chip. Consequently, all design steps between the definition of the system and its realization as a semiconductor structure must be strongly interconnected to yield successful and economic solutions. Reduced possibilities for testing and correcting design errors do not permit design concepts that follow the principle of trial and error. But up to now, the so-called logic design has been dominated by manually generated solutions. Because of the inherent possibilities of misinterpretation of the design task or of local design errors, analytical tools like simulation have to demonstrate the correctness of a design. But the restricted model accuracy, incomplete sets of test data, and excessive request for computing time are limiting factors of this design strategy in the context of VLSI. Therefore, other concepts for logic design are necessary that avoid analytical tools as much as possible but support the design process by synthesis. This paper discusses some methodical aspects of this problem, and it mentions some properties of logic design tools that are of practical importance.

Computer-aided synthesis of pla-based systems

Abstract: VLSI (Very Large Scale Integration) circuit design requires the use of computer aids in conjunction with a structured and hierarchical methodology to be economically feasible. Programmable Logic Arrays (PLAs) are regular structures widely used in the design of complex digital circuits, such as microprocessors. PLA-based systems can implement combinational and sequential functions and are amenable to automated synthesis. Optimal automated design of PLA-based systems is addressed here. Design of PLAs involves four basic steps: functional, logic, topological and physical design. In particular, new techniques for logic and topological design of PLA-based systems are introduced. Folding and partitioning are two topological design techniques that involve the reorganization of the array to reduce the silicon area occupied and improve the switching-time performance. Folding allows to implement a PLA in a smaller area, by rearranging the positions of the active devices and interconnections. Optimal PLA compaction is studied in connection with the problem of interconnecting the array to other circuit building-blocks. A new technique, multiple constrained folding, allows to achieve a minimal PLA area implementation with constrained positions of electrical inputs and outputs. Several new folding algorithms are described. Experimental results, obtained by computer program PLEASURE, are reported. Partitioning exploits the use of redundant columns and/or rows to transform a PLA into an array having the same functionality and a conveniently partitionable structure. Partitioned PLAs are implemented as block-folded arrays or as the parallel connection of PLA sub-units. An algorithm based on a graph representation of the PLA partitioning problem is presented. Experimental results, obtained by computer program SMILE, are reported. Logic design of PLA-based implementations of sequential functions, represented by Finite State Machines (FSMs), is then addressed. In particular, the optimal state assignment problem is studied in connection with logic minimization of the combinational component of the FSM. A binary encoding of the states (assignment) is optimal when the unfolded/unpartitioned PLA area is minimal. Due to the computational complexity of the problem, a heuristic technique for state assignment is presented. First the class of present-state assignments that minimize the PLA rows is determined. Then a minimal-length assignment (leading to a minimal-column PLA) is selected. Experimental results, obtained by computer program KISS, are reported.

A Layout Verification System for Analog Bipolar Integrated Circuits

Abstract: A new layout verification system, called ALAS (A Layout Analysis System) is presented. Its main intention is to tackle the particular verification problems of analog bipolar circuits. At present, the system comprises four main parts: a device recognition program produces a list of devices, a plot program converts these data to a layout-oriented circuit diagram, a connectivity analysis program yields device-oriented or net-oriented descriptions of the derived circuit and a network comparison program tests the consistency of this actual circuit with the intended nominal one. A fifth program, that will calculate the parameters of the actual circuit, is under development. To derive the actual circuit from layout ALAS uses geometrical mask data only; no additional circuit information is needed. If not available from the design system, a description of the nominal circuit may be supplied manually in a SPICE-like input format.

A methodology for custom VLSI layout

Abstract: In this paper, we present a new methodology for custom VLSI layout which aims at a low turnaround time and a high quality of design. VLSI circuits are highly complex, and to speed up the design process we exploit the hierarchical structure of a design, splitting the problem domain into several levels. The process of layout at each level is divided into steps such as placement of rectangular blocks, determining block dimensions, determining interconnection paths, etc. In order to obtain high quality designs, we have systematically analyzed the relationship among the parameters being computed at various steps and have accordingly organized the flow of data and control through these steps. There are two novel features in our scheme. First, we do not follow the usual pure top-down or pure bottom-up approach, so as to take into account the influence of design decisions at the higher levels on design decisions made at the lower levels, as well as vice versa. For example, we determine the geometry of a block taking into consideration the context in which it is placed, as well as the geometries of the lower level blocks it encloses. Second, we perform a look-ahead operation when the values of some. parameters are needed before they are actually deterministically computable by the process. For example, at the time of placement, the area required for routing is estimated statistically (before doing the actual routing) so that a more routable placement can be obtained, thereby avoiding some unnecessary iterations.

IC process modeling and topography design

Abstract: The device features in the third dimension in VLSI affect packing density and circuit performance. Establishing techniques to characterize and design these nonplanar device features is a major goal of the research on IC process modeling and simulation. Simulation is well accepted as a means of optimizing individual lithography, etching, and deposition processes. It is also well suited for studying the complex tradeoffs between conflicting physical mechanisms in the context of complete multistep process sequences. The success of modeling and simulation has created a demand for more extensive models and new applications. IC process modeling and simulation will not only contribute heavily to technology design but also offers a potential window through the layout role bottleneck for more complete design insight and optimization.

Design Automation for Integrated Circuits

Abstract: With the ever-increasing complexity of integrated circuits, manual design methods have become intolerably slow and error-prone. The use of computers to automate some or all of the design process is necessary to minimize both design time and error incidence. In this article are discussed the design and fabrication of integrated circuits, selected techniques of design automation, and the problems associated with such automation.

A Logic Design Front-End for Improved Engineering Productivity

Abstract: We have developed Design and Verification (DAV) as a new design front-end for the IBM Engineering Design System. DAV is a menu-driven system with powerful graphics capabilities for the entry and verification of a logic design. The design is hierarchically structured, using high-level technology-independent operators that can be simulated and verified at a purely logical level, then transformed into specific technologies and checked for LSSD rules and physical design constraints. The stated goals of DAV are for the product to get to the market in 30% less time, with 40% lower design cost, and with 98% percent of the errors removed prior to hardware prototyping. We expect to achieve these goals fully.

Compaction of hierarchical cells with minimum and maximum constraints

Abstract: • A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website. • The final author version and the galley proof are versions of the publication after peer review. • The final published version features the final layout of the paper including the volume, issue and page numbers.

Digitizing, layout, rule checking—The everyday tasks of chip designers

Abstract: The layout phase is most critical in the design of integrated circuits (IC's) because of the cost of the phase itself, since it involves expensive tools and a large amount of human intervention, and also because of the consequences for production Cost. Several approaches are used that need more or less computer and/or man time. The compromise is difficult because of the number of parameters to be taken into account. This paper presents the methods most commonly used with their advantages and disadvantages.

Microcomputer-Aided Circuit Design Preprocessor

Abstract: The need for care in designing input graphics programs (preprocessors) for Computer-Aided Circuit Design packages is discussed. A graphics preprocessor and associated algorithm is described whereby a picture presentation by the designer is converted to analysis information by the input graphics program of SPLAP — Sunderland Polytechnic Linear Analysis Program.

A proposed design approach for vlsic/vhsic based on mcdonnell douglas corporation's 1750a chip set design experience

Abstract: This paper describes a proposed design system and design methodology to efficiently design and test custom integrated circuits for use in military and aerospace systems. The experience obtained at McDonnel 1 Douglas Corporation (MDC) during the design of such integrated circuits as a chip level implementation of MIL-STD-1750A sewed as a basis for determining critical points in the design cycle which must be improved in order to design the more complex VLSIC/VHSIC systems of the future.

Integrated Computer Aided Design, Documentation and Manufacturing System for PCB Electronics

Abstract: This paper describes an integrated computer aided design, documentation and manufacturing system, which assures data integrity from physical design to manufacturing with the aid of one phase data input and integrated parts data base. Unique features of the system are comprehensive documentation support for PCB electronics, one-phase user friendly data input, intensive input data checking, support for part and document numbering and PCB numbering, user definable document formats and languages and fully automatic generation of N.C. programs for insertion machines and input data for test equipment. Although the design support is highly automatic, the system is just computer aided allowing the user to control the work flow and by providing the possibility for the user to overdrive the data base information. The designer experience, intuition and imagination can be fully utilized.

32-bit VLSI system

Abstract: The design of a fully integrated 32-bit VLSI multiprocessor is outlined. Since this is a high performance design implemented in MOS technology, special system and circuit design tradeoffs have been made to preserve high throughput. These include special packaging, clock generation and system protocols. 2 references.