Showing papers on "Physical design published in 1984"

A historical review of circuit simulation

Abstract: Within the Circuits and Systems (CAS) Society, developments in computer-aided circuit analysis and circuit design commenced in the early 1950's using the earliest digital computers. Initially, computer-aided circuit analysis of linear circuits was used in design optimization, design centering, and in determining the effects of parasitics on circuit performance. Although this use of computer-aided circuit analysis has continued, computer-aided design (CAD) and circuit design automation within the CAS Society are now principally concerned with problems associated with the overall design and evaluation of very large circuits and systems. This paper is a review of a major thread of CAD activity which has occurred within CAS from the earliest and remains of major interest. This thread involves computer-aided circuit analysis (circuit simulation) and its use in CAD systems. Fortunately, several excellent review papers have appeared within the past year or two to document well the technical milestones, as well as the problems of interest at the present time. It is possible then, in this paper, to concentrate on the developments in our present capability of circuit simulators, stressing the significant trends, noting some early developments which did not become major aspects, and observing the interchange between theory and practice.

Algorithm Design for Computer System Design

Abstract: MODELS OF THE TASK ASSIGNMENT PROBLEM IN DISTRIBUTED SYSTEMS Mario Lucertini Dipartirnento di Informatica e Sistemistica dell'Universiti di Roma e Istituto di Analisi dei Sistemi ed Informatica del C.N.R., Viale Manzoni 30, 00185, Roma The paper presents a model for optimum partitioning of tasks over a multiple-processor system. The minimization of the interprocessor. communications overhead and/or the message average delay are considered as a design criterion. The algorithmic approaches to the problem are briefly described and improuvements to the case of multiple copies of tasks are considered. A large set of references covering the area are included.

An algorithm for CMOS timing and area optimization

Abstract: Delay-time optimization for integrated circuits is discussed. A design truly optimized for delay time is seldom practical because the silicon area increases very rapidly when the minimum delay time is approached. The author presents an algorithm which facilitates an intelligent compromise between the delay time and the silicon area of a logic chain. A computer software based on this algorithm can interactively assist the designer in the selection of logic pattern, the number of stages, and the sizes of the transistors. Some basic assumptions are made in this algorithm in order to keep the mathematics manageable. Consequently, some random parameters related to layout and interconnection are not addressed. The intended use of this algorithm is to guide the designer to arrive at an approximately optimized design during the logic definition stage and before the layout stage. Later, when the layout is completed, a circuit simulator should be used to fine-tune the design by incorporating these random layout parameters.

Prediction of error probabilities for integrated digital synchronizers

Abstract: Synchronization errors occur when asynchronous digital signals are received by clocked digital systems Digital synchronizers are designed to minimize the probability of such errors Empirical determination of error probabilities, as used in the past, is not a viable method for large-scale integrated circuit because it is cumbersome, interferes with the circuit performance, and does not account for tolerances of circuit parameters The authors describe a complete method for predicting synchronization-error probabilities using circuit simulation and theoretical analysis The analysis includes the efforts of random noise The simulation model readily takes into account tolerances of the circuit parameters The direct observability of all parameters of the model enhances the understanding of the synchronization process and the reliability of the predictions

A wide-band technique for vector summation and RMS-DC conversion

Abstract: A circuit configuration is presented for wideband analog computation of both the vector-sum function and the RMS-DC conversion function. Design of the circuit is based on a systematic approach to translinear circuit synthesis. Errors due to finite transistor current gain are compensated by means of a novel technique. Measured performance results based on an experimental monolithic implementation in a standard bipolar process are presented. Bandwidths of 25 and 80 MHz are achieved for vector summation and RMS-DC conversion, respectively.

A Class of Cellular Architectures to Support Physical Design Automation

Abstract: Special-purpose hardware has been proposed as a solution to several increasingly complex problems in design automation. This paper examines a class of cellular architectures called raster pipeline subarrays--RPS architectures--applicable to problems in physical DA that are (1) representable on a cellular grid, and (2) characterized by local functional dependencies among grid cells. Machines with this architecture first evolved in conventional cellular applications that exhibit similarities to grid-based DA problems. To analyze the properties of the RPS organization in context, machines designed for cellular applications are reviewed, and it is shown that many DA machines proposed/constructed for grid-based problems fit naturally into a taxonomy of cellular machines. The implementation of DA algorithms on RPS hardware is partitioned into local issues that involve the processing of individual cell neighborhoods, and global issues that involve strategies for handling complete grids in a pipeline environment. Design rule checking and routing algorithms are examined in an RPS environment with respect to these issues. Experimental measurements for such algorithms running on an existing RPS machine exhibit significant speedups. From these studies are derived the necessary performance characteristics of RPS hardware optimized specifically for grid-based DA. Finally, the practical merits of such an architecture are evaluated.

Optimization of device area and overall delay for CMOS VLSI designs

Abstract: This paper addresses specific design tradeoffs that should be considered relative to CMOS VLSI designs using gate-array, semi-custom, or full-custom implementations. The main focus is on design optimization for speed and device area and on meeting the on-chip load drive requirements using one- and two-dimensional expansion techniques. Detailed comparisons are made between the effectiveness of the various design options in their ability to yield a specific performance within speed and/or area constraints while driving on-chip loads with and without geometrical constraints. These comparisons result in a number of design curves that cover the range of full CMOS custom design, for which two-dimensional scaling can be optimally utilized, to those cases involving semi-custom and gate-array designs for which geometric constraints exist (fixed height cells or fixed device sizes). A figure of merit is defined that relates speed and area to each specific circuit implementation, indicating that it can be used to make an effective comparison between overall performance and design option. It is finally suggested that a chip layout approach can be adopted that is useful for implementing any of the design options discussed.

A metal-oriented layout structure for CMOS logic

Abstract: A design method is described for the realization of large digital modules of random logic for custom integrated circuits in CMOS technology. The layout structure is based on the gate matrix concept with a metal orientation instead of a polysilicon orientation. The symbolic layout is obtained by using 11 different microcells with simple assembly rules. It is derived from the functional specifications of the circuit (Karnaugh maps) using a very simple and attractive method. A CAD program for translating the symbolic layout into a geometrical one is described. It works by assembling geometrical microcells. The advantages and disadvantages of the metal-oriented structure are analyzed through examples of industrial designs. The technique is not suitable for fast circuits. However, it results in an improvement of productivity by a factor of about four and a packing density for large modules which is at least comparable with that of nonoriented hand layouts.

Microwave Integrated Circuits--An Historical Perspective

Abstract: Before attempting an historical view of microwave integrated circuits, it was necessary to consider just what a microwave integrated circuit is. If someone can come up with a clear, noncontroversial, universally accepted definition, he's a better man than I am. In the broadest sense, a microwave integrated circuit is any combination of circuit functions which are packaged together without a user accessible interface. This definition, however, opens the door to great kluges of waveguide bends and components which have been brazed or welded together, and that is clearly not the intent of this review. I have, therefore, limited the scope to planar integrated circuits which make use of process control manufacturing techniques for a significant portion of the integrated circuit, This would include such transmission-line techniques as stripline, rnicrostrip, slotline, finline, co-planar waveguide, and to a slightly lesser extent, lumped element circuits, image guide dielectric waveguides, and planar waveguide packages which are becoming a viable technique for integrated circuits at millimeter-wave frequencies.

An interactive system for VLSI chip physical design

Abstract: The Federal Systems Division has developed a structured design methodology and a companion chip physical design system that has been used to build seven large VLSI chips (ranging in size from 7K to 36K logic primitives). Using the MVISA system, a logic designer has complete control and responsibility for the total chip design. Our experience has been that when this highly interactive software and methodology is used, chip physical design requires less than two weeks. This is a significant savings in design time; but more importantly the designer can allocate more schedule for logic design and simulation. This paper describes how FSD's unique interactive physical design system has improved productivity of VLSI design.

The Structure and Operation of a Relational Database System in a Cell-Oriented Integrated Circuit Design System

Abstract: An important use for a database management system is in the storage and handling of information for engineering design, particularly integrated circuit design. However, most discussions on this topic have concentrated on the layout of shapes necessary to form the various circuit elements, or connections between user-defined cells. Equally important, but often disregarded, is the necessity to support other design tools in addition to graphics for circuit layout. These include simulators and automatic layout programs that take a description of a circuit at one level and convert it to a lower level. In addition, if cells are part of a library defined and maintained by others, operations must be included to handle the maintenance of generations or versions of a cell design. These aspects of a database management system for engineering design are discussed in light of the tools being developed at the University of Utah and an extended version of System R, developed at the IBM San Jose Research Laboratory. The Utah approach emphasizes the use of previously designed and tested cells, with interconnects at fixed locations, placed on a grid. Because it is unlikely that the designers of circuits designed all (or any) of the cells used in their circuits, special database management operations are necessary to assure that a consistent, working circuit results.

Integrated circuit for the color decoder of a television set

Abstract: An integrated circuit is provided for the color decoder of a television receiver set and in particular for a multistandard decoder for NTSC, PAL and SECAM Conventionally employed external components used for synchronizing and amplitude calibration are replaced by circuits forming part of an integrated circuit, which automatically adjust for the desired operational mode such as NTSC, PAL or SECAM in each case This system saves previously required external components such as trimming resistors, potentiometers or quartz crystals A digital automatic frequency control circuit can provide the synchronization of oscillators within the integrated circuit which oscillators generate the required reference carriers required for the decoding of the chrominance carrier In addition, the switches for the processing of signals of various color television standards can be incorporated within the integrated circuit

Monolithic semiconductor integrated circuit with programmable elements for minimizing deviation of threshold value

Abstract: An integrated circuit includes a plurality of threshold-value compensatory programmable elements integrally incorporated into a semiconductor integrated circuit, wherein, during the inspection process after assembly, the programmable elements store stationary data related to varied threshold voltages occurred during assembly process so that the varied substrate bias voltages can be restored to an ideal level by applying compensations as required. This circuit is extremely advantageous in that it effectively compensates for even the slightest variation of the threshold voltage in the integrated circuit using its extremely simplified circuit configuration, and in light of the conventional tendency in which redundant circuits containing a variety of chip parts each having a substantial area are used, against the needs for high-density part installation, the circuit embodied by the present invention effectively and securely provides means for realizing higher yield of monolithic semiconductor integrated circuits.

An interactive optimization technique for the nominal design of integrated circuits

Abstract: The purpose of the paper is to present an approach to the nominal design of integrated circuits by interactive optimization. In solving the nominal design problem, proper values must be assigned to the set of designable parameters of an integrated circuit (IC) such that the requirements of circuit characteristics are fulfilled. The approach is based on a boundary curve of the optimization problem. This boundary curve is used as an assessment criterion to visualize the problem condition and to control the entire optimization process. A standardized representation of the boundary curve suited for graphic terminals is presented as well as an analysis of its characteristics and computational methods for the evaluation of the boundary curve. The approach is demonstrated by an application to a multiple objective design problem of an integrated circuit.

In pursuit of the one-month chip: The objective is to describe the functions required of an as yet nonexistent integrated circuit, then have it delivered in 31 days or less

Abstract: The development of the so-called one-month chip is explored in a five-part special report by IEEE Spectrum editors. The objective is to describe the functions required of an as yet nonexistent integrated circuit, then have it delivered in 31 days or less. The technological underpinnings of the new trend are examined from the standpoints of design, fabrication, and testing. The report is based on extensive interviews with engineers from all aspects of IC manufacturing and includes two round-table discussions with experts.

Cast Leads for Surface Attachment

Abstract: The attachment of leadless integrated circuit packages to printed circuit (PC) substrates is receiving growing attention as surface mounting technology advances to meet the demands of present and future product designs. The reliability issues associated with surface attachment of these packages continue to be addressed and characterized with respect to package configuration, material properties, and interconnection methods. A novel technique is introduced for reliable and economical attachment of leadless integrated circuit (IC) packages to circuit substrates. Known as the cast lead process, it is based on a concept for controlling solder joint geometry in order to improve the stress and strain distributions within the joints. The basic sequence of operations established for cast lead fabrication and for surface mounting of processed packages will be presented and results for several reliability studies will be discussed.

A Technology Independent MOS Multiplier Generator

Abstract: A layout generator for technology independent implementation of the MOS multiplier is described. The modified Booth's algorithm with a structured floor plan has been used. The layout has been optimized and described as a program in a high level layout language. The fabrication process related information is maintained in a separate technology database that is coupled with the layout program at the time of execution to generate the mask data. The user can choose from a variety of architectures for speed, area, and power trade-off's. The user can also specify geometric and electrical constraints tailored to his system specification.

Users View

Abstract: The complexity of communications systems and products developed and manufactured by AT & T demands a sophisticated set of Computer Aided Engineering tools. These tools are required to manage the complexities ranging from the integrated circuit level, through the circuit pack level, to the levels of shelves and frames of equipment. They are used at the very onset of the design process, starting with initial design intent capture, through fabrication of prototypes and models, and culminating in information transfer and manufacture. To meet these needs within a common design environment, a CAE system is required which possesses considerable technical depth, great flexibility, and the capacity to evolve to meet changing needs.The Unified CAD System is a comprehensive and integrated system of CAE tools used at AT & T for the design, development, and manufacture of electronic circuit packs and backplanes. This system was conceived and developed at AT & T Bell Laboratories and is now in heavy use by AT & T product development and manufacturing organizations. When used in its complete form, the system provides a totally data driven process from design capture to manufactured product. This is achieved with a minimum of manual intervention and with the availability of audits to verify the integrity of data at each step along the way.This paper addresses the users view of the system. At AT & T, the users consist of design engineers, specialists in physical design realization, documentation, and information transmittal, and manufacturing engineers.This paper presents a description of how the system is used today, its performance in these environments, and a users view of future directions.We find that the Unified CAD System improves quality, reduces costs, reduces intervals, and improves human interfaces. Use of the system has resulted in fewer design iterations, reduced design activity, and elimination of duplication of effort. The system has had a profound effect in bringing designs into manufacture, and the users are anxious to extend its benefits into even more aspects of the product development and manufacturing process.

A Hierarchy-Driven Amalgamation of Standard and Macro Cells

Abstract: A new methodology for the automatic layout of integrated circuits is presented. The methodology, based on a hierarchical description of the circuit, is a hybrid between standard cell and fully custom, having the advantages of both. It has the ease of placement and routing of standard cell, combined with the ability to handle large numbers of diverse cells as in fully custom. The methodology has been implemented and applied to several circuits, with very encouraging results.

An analytical investigation into record structuring and physical database design of generalized logical data structures (optimization, formulation, heuristics)

Abstract: This research concerns itself with the efficient design of the physical database. Within physical database design, its emphasis is on the definition of the record structures of the various computerized files in the database. Specifically, efficient physical database designs are generated so as to minimize the page access and/or storage cost of the database; given a generalized logical data structure (LDS), activities on the data and the computer system characteristics. A generic model for physical database design is used which allows aggregation (storing related instances of two entities together) and pointers for representing relationships in the LDS. In order to obtain optimal or near optimal solution to the design problem, six heuristics have been developed. Four of them are based on problem specific pairwise entity information and two are based on generic principles of optimization. Recommendations have been made on the proper use of the heuristics. In addition, the heuristics have been evaluated using a comprehensive experimental design. Further, some guidelines for physical design have been proposed; and a sensitivity analysis of design factors has been made. In addition, a non-linear zero-one integer program has been formulated for a subcase of the general problem. Several approaches have been proposed to optimally solve the integer program. The formulation will serve as the basis for future mathematical programming efforts. In support of the heuristic methods, an evaluator/simulator has been written in FORTRAN to evaluate the access and storage costs of a given physical design. Embedded in the evaluator are certain new mathematical expressions and formulas that facilitate evaluation. Finally, the feasibility of implementing the physical design, as generated by this process, on commercial DBMSs has been examined. This has been demonstrated on two commercial DBMSs, namely IMS of IBM and CODASYL based DBTG systems.

Two algorithms for three-layer channel routing

Abstract: A channel router is an important design aid in the design automation of VLSI circuit layout. Many algorithms have been developed based on various wiring models with routing done on two layers. With the recent advances in VLSI process technology, it is possible to have three independent layers for interconnection. In this paper two algorithms are presented for three-layer channel routing. The first assumes a very simple wiring model. This enables the routing problem to be solved optimally in a time of O ( n log n ) . The second algorithm is for a different wiring model and has an upper bound of O( n 2 ) for its execution time. It uses fewer horizontal tracks than the first algorithm. For the second model the channel width is not bounded by the channel density.

The Channel Expansion Problem in Layout Design

Abstract: In order to develop an efficient method of routing channels in the layout design process, an algorithm which solves the channel expansion problem is presented. This algorithm guarantees the minimum number of rerouted channels with respect to a single channel in a given placement. In addition, examples are given to illustrate various aspects of the algorithm.

DC Statistical Circuit Analysis for Bipolar IC's Using Parameter Correlations-An Experimental Example

Abstract: Statistical analysis simulates circuit performance variations caused by tolerance variations and other circuit production factors. The procedure of statistical circuit simulation is illustrated with the help of a simple circuit example. Measurements are made on a sample of this circuit. These measured results are compared with the simulation results from worst-case and statistical analyses without and with model parameter correlations for the devices used in the circuit. The necessity for properly including the model parameter correlations is evident from this comparison.

Gateway: a teaching exercise in gate-array technology

Abstract: The Gateway gate array design exercise has been developed as a vehicle for exposing students to as many of the techniques and disciplines of microelectronic design (and gate array technology in particular) as is possible within the constraints of an academic course. The exercise has been streamlined to carry the student through the stages of logic design, circuit design and computer-aided design of an integrated circuit. On completion of the design, each student's chip is manufactured, and packaged chips are then returned to the student for testing. The paper discusses the technology, software and results obtained from the Gateway exercise undertaken by undergraduate students.

Custom and Semi-Custom Design Techniques

Abstract: Over the past decade, a variety of techniques have been developed and refined for the synthesis of custom and semi-custom IC layout. Choice of technology (CMOS, NMOS, etc.), electrical design style (e.g., static, dynamic, etc.), and layout design style (gatearray, building-block, PLA, etc.) all play an important role in determining the overall performance of the final component and the chip design time. Now, an equally important consideration is the availability of computer-aided design (CAD) tools to support the synthesis and testing of such chips. The rapid advances in each of the aforementioned areas often makes it difficult to determine the best combination of each of these techniques for a particular custom or semi-custom design system. While there is no single design method that is suitable for all cost-performance-design time tradeoffs, even for a specific set of tradeoffs, the best choice of design techniques is not clear. Combinations of various semi-custom design techniques, with detailed comparisons with other approaches for implementing the same circuits, are being reported. This includes rapid design turnaround, achieved by using building-blocks, standard cell, and automated PLA design as well as a number of mixed custom and semi-custom design styles. Speakers will also cover a differential CMOS electrical design style and its application to a large circuit design. This technique is supported by a powerful CAD system and has been used to implement a circuit containing over 20,000 transistors. The use of module generators for the automated synthesis of complex IC buildingblocks was introduced at ISSCC 83. Two more excellent examples of this new approach to circuit design will be described. Not only have these module generators been used to implement digital circuits, but a system for synthesizing analog building-blocks with specified gain, noise margin, and slew rate has been developed. Additional projects to be discussed include an advanced electron-beam circuit test strategy which permits both random-access read and random-access write of circuits during operation.

A wire-wrap design aid, written in PROLOG

Abstract: Wire-wrap based prototypes are widely used to evaluate electronic circuit designs. In the course of evaluation, the design may change, and the prototype must be modified accordingly. Much effort is required both to design an initial prototype implementation, and subsequently to modify an existing prototype to conform to design changes. Some of the problems associated with prototype design and modification are discussed, and the basic aspects of a program which addresses them are presented. An interesting feature of the program is that it uses a novel method, based on optimization by simulated annealing, to minimize wire connection lengths. The entire program is written in Prolog.

A Graph Model and the Embedding of MOS Circuits

Abstract: The direct automated transformation of a circuit into the "best" physical layout is hard. An alternative is the transformation of a circuit into a suitable intermediate form, the layout topology. Each layout topology defines an equivalence class of physical layouts. A few layout topologies can be chosen according to their likeliness for leading to the "best" design. Each of these layout topologies can then be transformed into a physical layout that will be optimized. The final design can be chosen from the set of optimized physical layouts. Each optimized physical layout corresponds to a unique layout topology. A circuit is modeled as a graph, The circuit's graph model is analyzed by the embedding algorithm. The embedding algorithm determines the set of layout topologies that will be transformed into the physical layouts for further processing. A layout topology is specified as a graph together with the set of cyclic orders of the vertices, and the layer assignment of the edges.