Showing papers on "Physical design published in 1985"

Principles of CMOS VLSI Design: A Systems Perspective

Abstract: Introduction to CMOS Circuits. Introduction. MOS Transistors. MOS Transistor Switches. CMOS Logic. Circuit Representations. CMOS Summary. MOS Transistor Theory. Introduction. MOS Device Design Equation. The Complemenatry CMOS Inverter-DC Characteristics. Alternate CMOS Inverters. The Differential Stage. The Transmission Gate. Bipolar Devices. CMOS Processing Technology. Silicon Semiconductor Technology: An Overview. CMOS Technologies. Layout Design Rules. CAD Issues. Circuit Characterization and Performance Estimation. Introduction. Resistance Estimation. Capacitance Estimation. Inductance. Switching Characteristics. CMOS Gate Transistor Sizing. Power Consumption. Determination of Conductor Size. Charge Sharing. Design Margining. Yield. Scaling of MOS Transistor Dimensions. CMOS Circuit and Logic Design. Introduction. CMOS Logic Structures. Basic Physical Design of Simple Logic Gates. Clocking Strategies. Physical and Electrical Design of Logic Gates. 10 Structures. Structured Design Strategies. Introduction. Design Economics. Design Strategies. Design Methods. CMOS Chip Design Options. Design Capture Tools. Design Verification Tools. CMOS Test Methodolgies. Introduction. Fault Models. Design for Testability. Automatic Test Pattern Generation. Design for Manufacturability. CMOS Subsystem Design. Introduction. Adders and Related Functions. Binary Counters. Multipliers and Filter Structures. Random Access and Serial Memory. Datapaths. FIR and IIR Filters. Finite State Machines. Programmable Logic Arrays. Random Control Logic.

Inductive Fault Analysis of MOS Integrated Circuits

Abstract: Inductive Fault Analysis (IFA) is a systematic Procedure to predict all the faults that are likely to occur in MOS integrated circuit or subcircuit The three major steps of the IFA procedure are: (1) generation of Physical defects using statistical data from the fabrication process; (2) extraction of circuit-level faults caused by these defects; and (3) classification of faults types and ranking of faults based on their likelihood of occurrence Hence, given the layout of an IC, a fault model and a ranked fault list can be automatically generated which take into account the technology, layout, and process characteristics. The IFA procedure is illustrated by its applications to an example circuit. The results from this sample led to some very interesting observations regarding nonclassical faults.

Timing Influenced Layout Design

Abstract: We present a new approach to the automatic layout design for VLSI chips which incorporates timing information to influence the placement and wiring processes. This approach is an extension of the hierarchical layout method, in which placement and wiring are performed simultaneously [1]. We add a third phase of timing to the hierarchy, without affecting the computational complexity of the basic algorithm. Prior to the physical design, timing analysis is performed using statistical estimates for the unknown parameters; namely the lengths of interconnecting wires. The output of this analysis includes a measure for each net that indicates the degree of its contribution to the timing problem. This set of measures is used to bias the placement at the highest level of the hierarchy. Since wiring is performed after each level of partitioning, lengths of interconnecting nets among the partitions become available. These data are used to update the timing information that bias the design. Preliminary results show that, while delays due to interconnections are reduced, wireability of the chip does not deteriorate.

An Integrated Automated Layout Generation System for DSP Circuits

Abstract: An integrated CAD system for the automated design of digital signal-processing (DSP) circuits for audio and telecommunication applications is described. The system uses as unique input a symbolic description of algorithm. This representation is translated into an actual layout using a two-step process. First, the symbolic input is mapped into the target architecture, which consists basically of a set of concurrent processors and dedicated I/O circuitry. The resulting hardware configuration is compiled into a layout description through a full exploitation of the hierarchy and the modularity of the architecture, calling consecutively a tiler, a floorplanner, and a global placement and routing tool. All these layout generation tools are able to support a wide range of technologies. The provision of a dedicated register transfer level simulator allows for the efficient debugging and algorithmic checking of the real-time operating signal-processing algorithms. The efficiency and the usefulness of this design methodology has been demonstrated by multiple examples. Experiments have shown that the use of these techniques can reduce the complete design process to a few months.

VLSI circuit layout : theory and design

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VHSIC Hardware Description Language

Abstract: In March 1980, the US Department of Defense (DoD) launched the Very High Speed Integrated Circuits program to advance the state of the art in highspeed integrated circuit technology, specifically for defense systems. In 1981 the Institute for Defense Analyses (IDA) arranged a workshop to define the requirements for such a standard. The DoD used the final report of the IDA workshop as a basis for defining a set of language requirements for the VHSIC Hardware Description Language (VHDL), issuing a request for proposal for a two-phase procurement of VHDL and its support environment. VHDL supports the design, documentation, and efficient simulation of hardware from the digital system level to the gate level. While designed to be independent of any underlying technology, design methodology, or environment tool, the language is also extendable toward various hardware technologies, design methodologies, and the varying information needs of design automation tools. The authors begin their discussion of VHDL by describing the concept of design entity, the language's primary abstraction mechanism. They then present a time-based execution model and describe VHDL's features, using a coded four-bit adder to illustrate the use of the most significant ones. Various figures are presented that contain the block diagrams and the code for this example.

The VLSI Design Automation Assistant: From Algorithms to Silicon

Abstract: Our ability to fabricate complex VLSI chips is outrunning our ability to design them. To reduce the design time for complex chips we are creating an expert design assistant?programs that automate as many of the design tasks as possible while allowing the human designer to control the synthesis process. A series of programs translates an algorithm into a chip layout. Some programs are expert systems while others use traditional algorithms. Our early results lead us to believe that a knowledge-based expert system is an appropriate tool for bridging the gap between logical and physical design.

Standard cell VLSI design: A tutorial

Abstract: The design aspects and methodology from concept to manufacture of standard cell VLSI circuits are covered. A broad treatment of the subject and of what design aids are available to help designers get their jobs done efficiently and reliably is provided. The treatment is directed toward the new VLSI designer.

Numerical simulation of resistive interconnects for integrated circuits

Abstract: When interconnects for integrated circuits have been modeled, it has been normal to consider them only as straight tracks. In any practical circuit this is not the case and a more rigorous analysis is performed by the authors. The effects of corners and T-junctions are analyzed using finite elements and some models are presented which can be used by circuit designers to simulate circuit performance.

Integrated circuit having a built-in self test design

Abstract: An integrated circuit having a built-in self test design, the integrated circuit including a combinatorial logic circuit, a first register coupled to an output of the combinatorial logic circuit and a feedback path via which output signals from the first register are fed back to an input of the combinatorial logic circuit. A multiplexer is provided between the first register and the feedback path, and there is also provided a second register responsive to a signal which is originated to initiate a test function for feeding test signals via the multiplexer and the feedback path to the input of the combinatorial logic circuit.

Technology Independent Device Modeling for Simulation of Integrated Circuits for FET Technologies

Abstract: A novel approach to device modeling for circuit simulation of integrated circuits is presented. This approach is based on general nonlinear network models in tensor product spline representation. As a consequnce this device modeling approach is technology independent and automatable. Tensor product spline representations of nonlinear branch elements are particularly useful, since the controlling variables are typically directionally dominant and only low rank tensors are needed. The basic properties of splines are reviewed for circuit simulation applications. Device model generation, software implementation, user interfaces and the circuit simulation environment within SPICE are described in detail. Realistic comparisons with conventional device models are given. The approach has been applied to several integrated circuit technologies (1/2-μm silicon MESFET logic, 7-μm CMOS/SOS logic, and 5-μm metal gate bulk silicon CMOS logic). Device models and simulated circuit results are in all cases in excellent agreement with measured device and circuit characteristics. This novel device modeling approach is particularly suitable for circuit design in quickly changing technological environments and for submicron VLSI.

Hierarchical Layout Verification

Abstract: This article presents a hierarchical cell structure that has been Used successfully to improve the performance of Intel's connectivity verifier and design rule checker. A unique algorithm for performing design rule checks efficiently in a hierarchical environment is discussed in detail. To undersize and oversize in a hierarchical environment without disrupting the cell structure, the definition of sizing must be changed so that geometries inside a cell and touching the cell boundaries do not pull away and geometries outside the cell do not extend inside. There are also a few Pathologies?caused mostly by looking at only a small portion of the layout, outside of the context where it is used. Nevertheless, careful use of hierarchical design can deliver order-of-magnitude improvements in layout checking runtime.

An Integrated Design Automation System for VLSI Circuits

Abstract: Our Integrated Design Automation System consists of an integrated design database, automated design processors, verification tools, and an interactive capture system. The automatic logic synthesis program, Angel, and the hierarchical layout system Champ/Alpha, have been particularly important in reducing the total design effort. A unified design language, HSL-FX, has been developed to broaden LSI design system coverage and to obtain better results from automatic logic synthesis. Using this system, a 10K-gate CPU has been designed in two man-months?from function-level description to layour pattern.

ACORN: A Local Customization Approach to DCVS Physical Design

Abstract: Differential cascode voltage switch (DCVS) trees are high performance, high functionality CMOS circuits, which, because they have a large number of inputs and internal connections, are difficult to wire on a large scale. Wirability is substantially improved by local customization at the tree level. This paper describes a DCVS customization procedure that exploits the fact that a Boolean function has more than one physical realization. Using ACORN, an automated physical design system based on this concept, we have placed and wired several designs, the largest of which is a group of three interconnected macros comprising approximately 800 DCVS trees.

LSI implementation of a pattern matching algorithm for speech recognition

Abstract: Many speech recognition systems contain the foUowing functional blocks: a voice input circuit, a feature extractor (analyzer), a unit for calculating the distance between input and standard patterns at every frame, a memory for storing standard patterns, a unit for matching whole word patterns (a pattern matching circuit), and a final decision and system control circuit. The pattern matching circuit is independent of the recognition algorithm and requires many conventional integrated circuits for implementation. Therefore, we decided to develop a custom integrated circuit for the pattern matching function. Due to its original architecture, our integrated circuit is able to execute in real time a continuous nonlinear matching process and is able to handle large volumes of data. This integrated circuit has been designed to be suitable for both isolated word recognition and connected speech recognition. The circuit has been tested in a pilot isolated-word and connected-speech recognition system. In this paper, the authors describe this integrated circuit's specifications, architecture, and performance, as well as its application in the model system.

Hierarchical Circuit Verification

Abstract: One of the crucial steps in designing VLSI circuits is to verify the correctness of the layout of the circuitry. Traditionally, this verification step is done by first flattening out the circuit hierarchy. This approach requires a substantial amount of computational overhead even for circuits that are relatively small. In this paper, a connectivity verification algorithm which exploits circuit hierarchy is presented. This algorithm works most efficiently with big circuits and is therefore useful for verifying VLSI circuits.

MCNC's Vertically Integrated Symbolic Design System

Abstract: This paper describes the VIVID (Vertically Integrated VLSI Design) System developed at the Microelectronics Center of North Carolina. The system is based on a symbolic, virtual-grid design methodology that greatly reduces the design time for custom VLSI circuits. This methodology has made it possible to provide, in a single integrated system, several unique features: technology independent tools for a wide range of MOS processes (CMOS, nMOS, SOI); scale independent circuit designs; open architecture that simplifies both integration with existing tools and creation of new tools; fast layout debugging using symbolic level circuit simulation; and fully automated mask generation and automated chip assembly.

Hardware Acceleration of Gate Array Layout

Abstract: In this paper we describe the hardware and software of a system which we have implemented to accelerate the physical design of gate arrays. In contrast to nearly all other reported approaches, our approach to hardware acceleration is to augment a single-user host workstation with a general-purpose microprogrammable slave processor having a large private memory. One or more such slaves can be attached. We have implemented placement improvement on the system, achieving a 20 x speedup vs. a high-level host implementation. We give performance results, which are comparable to those reported elsewhere for mainframe implementations.

Gutting chip-testing costs: Designing VLSI circuits for testability is the most efficient way to reduce the relative costs of assuring high chip reliability

Abstract: Testing now accounts for 10% of the total cost of manufacturing a 1-kb random-access-memory chip. For a 64K RAM chip, the figure rises to 40%. New techniques, however, promise to hold down costs by tackling the circuit-testing problem in the design stage. The new methods include computer programs that assess during design how easily a circuit can be tested, scan-design techniques for testing sequential circuitry, and ways of partitioning chips into blocks of manageable size for testing. Random testing and built-in self-testing are also employed in some cases to avoid exhaustive testing for every possible fault in a circuit. These new methods are described.

Faults and fault effects in NMOS circuits - impact on design for testability

Abstract: VLSI circuits currently being designed are so complex that it is now extremely difficult to test them adequately to determine whether or not they have been processed correctly. Design for testability (DFT) techniques are often used in an attempt to ease this problem by identifying and redesigning potentially ‘difficult-to-test’ parts of the circuits. The ‘testability’ of the circuit is usually evaluated in terms of the stuck-at fault model. However, there have been growing doubts over the ability of this model to cover certain common faults that can occur in MOS processing (at present, the dominant VLSI technology). The paper describes software simulations of faults in simple NMOS logic circuits showing that not all fault effects in NMOS circuits are modellable as ‘stuck’ nodes. An improved fault model which would better reflect MOS fault effects has yet to be defined. Until such an improved model is available, DFT rules for MOS circuits are best regarded as provisional. We therefore conclude with a discussion of ad hoc ‘physical design for testability’ techniques that exploit current understanding of the relation between MOS faults and their fault effects.

Fabrication of integrated circuits incorporating in-process avoidance of circuit-killer particles

Abstract: In the manufacture of an integrated circuit, steps of the process are dynamically augmented, so as to fabricate the integrated circuit at wafer locations which avoid the presence of circuit-killing particulates. During the respective steps of fabrication, the components employed in the process are scanned to locate and identify particulates. This information is compared with a previously defined component/interconnect layout to determine whether the particulates reside at locations that will not detrimentally impact the completed circuit or whether further processing will incorporate the defect into the circuit and render it effectively useless. In this latter circumstance the intended geometries of the circuit are modified, so as to effectively rearrange or shift prescribed components (e.g. semiconductor regions, contact apertures, interconnect tracks) to a location of the wafer which are not coincident with the location of the particulates.

Parallel simulation of digital lsi circuits

Abstract: Integrated circuit technology has been advancing at a phenomenal rate over the last several years, and promises to continue to do so. If circuit design is to keep pace with fabrication technology, radically new approaches to computer-aided design will be necessary. One appealing approach is general purpose parallel processing. This thesis explores the issues involved in developing a framework for circuit simulation which exploits the locality exhibited by circuit operation to achieve a high degree of parallelism. This framework maps the topology of the circuit onto the multiprocessor, assigning the simulation of individual partitions to separate processors. A new form of synchronization is developed, based upon a history maintenance and roll back strategy. The circuit simulator PRISM was designed and implemented to determine the efficacy of this approach. The results of several preliminary experiments are reported, along with an analysis of the behavior of PRISM.

The 5ESS switching system: Physical design/hardware

Abstract: The reliability, availability, and versatility of the 5ESS™ switch are highly dependent on the physical design of the hardware. We present a comprehensive description of the system and equipment designs, with particular emphasis on the advanced interconnection technology used, such as the fine-line, multilayer, printed wiring boards; ceramic substrates for functional modules; and high-performance, device-level packaging. The system design features described include new cabinet and office arrangements, the use of Fastech™ equipment, and new power and alarm systems. The office layout is flexible to allow growth in any size installation, and the modular architecture of the 5ESS switch makes it easy to install. We also present various testing and installation methods and summarize the physical design requirements and objectives for all equipment in the 5ESS system.

Algorithms and architecture for multiprocessor-based circuit simulation

Abstract: Accurate electrical simulation is critical to the design of high-performance integrated circuits. Logic simulators can verify function and give first-order timing information. Switch-level simulators are more effective at dealing with charge-sharing than standard logic simulators, but cannot provide accurate timing information or discover DC problems. Delay estimation techniques and cell-level simulation can be useful in constrained design methods, but must be tuned for each application, and circuit simulation must still be used to generate the cell models. None of these methods has the guaranteed accuracy that many circuit designers desire, and none can provide detailed waveform information. Detailed electrical-level simulation can predict circuit performance if devices and parasitics are modeled accurately. However, the computational requirements of conventional circuit simulators make it impractical to simulate current large circuits. In this dissertation, the implementation of Iterated Timing Analysis (ITA), a relaxation-based technique for accurate circuit simulation, on a special-purpose multiprocessor is presented. The ITA method is an SOR-Newton, relaxation-based method which uses event-driven analysis and selective trace to exploit the temporal sparsity of the electrical network. Because event-driven selective trace techniques are employed, this algorithm lends itself to implementation on a data-driven computer. Initial results indicate that data-driven multiprocessors, working with a conventional host, can provide performance improvement for electrical circuit simulation limited only by the size and structure of the circuit under analysis. This particular class of machines also seems well-suited to other network-graph-based, event-driven algorithms, such as fault simulation and many non-electrical problems.

The Property of Separability And Its Application to Physical Database Design

Abstract: A theoretical approach to the optimal physical design of a large multifile database is presented. The approach is based on the concept that, given a set of access structures and transaction processing methods that satisfy a certain property called separability, the problem of optimally assigning access structures to the whole database can be reduced to the collective subproblems of optimizing individual (smaller) objects in the database independently of one another. The formal concept is introduced, and applications to both relational and network model database systems are discussed. The approach presented significantly reduces the complexity of the design problem which has the potential of being combinatorially explosive.