Showing papers on "Physical design published in 1989"

Logic synthesis for vlsi design

Abstract: Very Large Scale Integration (scVLSI) currently allows hundreds of thousands of transistors in a single application-specific integrated circuit. The trend of increasing levels of integration has stressed the ability of the designer to keep pace. Traditional integrated circuit design has relied on analysis tools to measure the quality and correctness of a circuit before fabrication. However, only recently have synthesis tools been used to assist in the design process. The advantages of automatic synthesis include reduced design time, reduced probability of design error, and higher quality designs because more effort is focused at higher-levels in the design. Automatic placement and routing, a form of physical design synthesis, has become widely accepted over the last five years; however, logic design has, for the most part, remained a manual task. Logic synthesis is the automation of the logic design phase of scVLSI design; that is, choosing the specific gates and their interconnection to build a desired function. For digital integrated circuits which are partitioned into control and data-path portions, design of the control logic is often the most time-consuming. It is generally on the critical path for timing, and, because of the complexity of producing a correct description of the control, it is often on the critical path for completion of the design. Therefore, tools to assist in logic design will have a large impact on the design of integrated circuits. However, the benefits of automatic logic design are lost if the result does not meet its area, speed, or power constraints. Therefore, a critical aspect of automatic logic synthesis is the optimization problem of deriving a high-quality design from an initial specification. This thesis provides a set of logic optimization algorithms which together form a complete system for logic synthesis in a scVLSI design environment. Efficient, optimal algorithms are proposed for two-level minimization, multiple-level decomposition, and technology mapping. The techniques described in this thesis have been implemented in a software program called scMIS. The design of a complex digital circuit is included as part of this thesis to demonstrate the application of logic synthesis to a realistic design problem.

Analog circuit design optimization based on symbolic simulation and simulated annealing

Abstract: A methodology for the automatic design optimization of analog integrated circuits is presented. A non-fixed-topology approach is realized by combining the optimization program OPTIMAN with the symbolic simulator ISAAC. After selecting a circuit topology, the user invokes ISAAC to model the circuit. ISAAC generates both exact and simplified analytic expressions, describing the circuit's behavior. The model is then passed to the design optimization program OPTIMAN. This program is based on a generalized formulation of the analog design problem. For the selected topology, the independent design variables are automatically extracted and OPTIMAN sizes all elements to satisfy the performance constraints, thereby optimizing a user-defined design objective. The global optimization method used on the analytic circuit models is simulated annealing. Practical examples show that OPTIMAN quickly designs analog circuits, closely meeting the specifications, and that it is a flexible and reliable design and exploration tool. >

Method and apparatus for designing integrated circuits

Abstract: A method and apparatus for determining integrated circuit layouts from a virtual circuit description and specification of a technology. Starting with high-level descriptions of a circuit, a virtual geometric description of the circuit is developed using a virtual grid described in terms of reference points relative to a substrate surface. The relationships among the reference points are expressed as fractions of variables that can also be used to define the design rules. When the technology is specified, the relationships among the reference points is determined, as in the layout of the integrated circuit.

Performance-Driven Placement of Cell Based IC's

Abstract: The increasingly important role of the interconnect in the timing performance of present and future integrated circuit technologies underscores the need to reconsider conventional physical design CAD tools, and devise new ways to influence performance during layout. Interconnects are not perfect conductors, they introduce parasitic elements that load the logic gates and distort the temporal properties of the design as viewed by the logic designer. Cell placement that minimizes wirelength as the sole objective does not solve the problem, leaving a margin for performance improvement that has not been fully exploited. This paper presents a novel approach to performance-driven placement, combining timing analysis and physical design to dynamically optimize the performance of the chip during placement. The ideas are embodied in a program named Allegro, and preliminary results tested on Sea-of-Gate designs are encouraging.

IRSIM: An Incremental MOS Switch-Level Simulator

Abstract: This paper describes IRSIM, an incremental switch-level simulator for MOS transistor circuits. In IRSIM, the circuit under simulation can be modified and then incrementally resimulated. This allows error correction and circuit operation verification to be performed in time proportional to the size of the modifications rather than the size of the entire circuit. To accomplish this incremental simulation, IRSIM maintains a history of circuit activity during simulation and only resimulates the sections of the circuit that deviate from their history. The program was tested on several corrections to errors that actually occurred in the design of a VLSI microprocessor. These errors were corrected and the circuit was incrementally resimulated 1.6 to 3500 times faster than simulating the entire circuit.

Timing driven placement

Abstract: The authors address the problem of incorporating timing constraints into the physical design of integrated circuits. First they formulate the problem and discuss graph models suitable for its analysis. Next, they describe algorithms resulting in placements of improved performance in comparison to placements whose objective is to minimize the summation of wire lengths on the chip. Finally, the authors show preliminary results of their placement programs for the sea-of-gates designs. >

Integrated silicon-software compiler

Abstract: A computer-aided system and method is disclosed for designing an application specific integrated circuit (ASIC) whose intended function is implemented both by a hardware subsystem including hardware elements on the integrated circuit and by a software subsystem including a general purpose microprocessor also on the integrated circuit. The system also generates software instructions for use by the software subsystem. The system utilizes a knowledge based expert system, with a knowledge base extracted from expert ASIC designers, and thus makes it possible for ASIC's to be designed and provided quickly and economically by persons not having the highly specialized skill of an ASIC designer.

Techniques for area estimation of VLSI layouts

Abstract: The standard cell design style is investigated. Two probabilistic models are presented. The first model estimates the wiring space requirements in the routing channels between the cell rows. The second model estimates the number of feedthroughs that must be inserted in the cell rows to interconnect cells placed several rows apart. These models were implemented in the standard cell area estimation program PLEST (PLotting ESTimator). PLEST was used to estimate the areas of a set of 12 standard cell chips. In all cases, the estimates were accurate to within 10% of the actual areas. PLEST's estimation of a chip layout area takes only a few seconds to produce, as compared with more than 10 h to generate the chip layout itself using an industrial layout system. >

A synthesis strategy for mechanical devices

Abstract: Good mechanical designs are often composed of highly integrated, tightly coupled components in which the interactions among the components are essential to the function and economic execution of the design. This assertion runs counter to design methodologies in other engineering fields, such as software design and circuit design, that advocate designs in which each component fulfills a single function with minimal interaction. Because of the geometry, weight, and cost of mechanical components, converting a single functional requirement into a single component is usually not practical. Each component may contribute to the performance of more than one function, and the performance of each function may be distributed over many components. In fact, most mechanical components perform not only the desired function, but also have many additional, unintended behaviors. In good mechanical designs, these additional behaviors often are exploited. We describe a synthesis strategy to utilize these behaviors by transforming design specifications in a function-preserving manner to obtain function structures which correspond closely to collections of available components. This strategy is elaborated in the context of simple gearbox design. We feel that design strategies derived from characteristics of good designs will foster improved design practice and facilitate the development of computer-based assistance to the designer.

Efficient quadratic approximation for statistical design

Abstract: A highly efficient approach to quadratic approximation of circuit responses is presented. Because it uses a fixed pattern of base points, this approach requires extremely small amounts of CPU time and storage space. Using this approach, a major obstacle for the traditional quadratic approximation for dealing with large problems, namely, the prohibitive requirement for storage and computational effort, is effectively eliminated. The accuracy and efficiency of this quadratic approximation approach are demonstrated by two statistical circuit design examples. >

Silicon-compiler method and arrangement

Abstract: A silicon-compilation method, a silicon-compiler arrangement, an abstract-circuit synthesis module usable in such arrangement, a machine-generated abstract circuit produced by such module, an electronic circuit generated by such method and a reset-free circuit produced by such arrangement. There are described a method and arrangement for silicon compilation. First, an algorithmic procedure to be executed by the electronic circuit is expressed in an imperative concurrent language. This, under execution of lexical, syntactic and semantic analysis is converted to a structure tree as an abstract representation of said procedure. This structure tree then is converted into an abstract circuit, wherein each basic component is a program module and each abstract channel corresponds to a program channel. Thereafter, the abstract circuit is converted into a concrete circuit, while obeying timing-organization constraints, circuitry-type constraints and technology constraints. Finally, the concrete circuit is converted into a very large-scale integrated-circuit layout.

Layout-driven test generation

Abstract: Conventionally, test vectors are generated using gate-level models to represent the circuit design and abstract fault models (e.g. the stuck-fault model) to describe all of the processing defects causing circuit failure. The authors demonstrate that test vectors can be generated using realistic defect models and actual IC layouts, which should lead to test vectors with a higher defect detectability. The layout-driven generation of the faults has a computational complexity which is similar to that of design-rule checking, i.e. O(n log n). >

iSMILE: A Novel Circuit Simulation Program with emphasis on New Device Model Development

Abstract: The laborious task of implementing a new device model in a circuit simulator has long been recognized as a painful bottleneck to device modeling. In contrast to the conventional circuit simulators which employ a built-in model library approach, iSMILE generates and links all the necessary codes automatically from a minimal set of model descriptions contained in a user's model input file. Users are completely shielded from the internal complexity of the program when implementing new models. This flexibility of extraction and by comparing circuit simulation results in terms of performance and accuracy. iSMILE has been used successfully as a CAD tool for the development of new models for high-speed optoelectronic integrated circuits.

Technique for modifying an integrated circuit layout

Abstract: An existing integrated circuit layout is modified or revised in order to shrink it, update it, modify it for merger with another circuit on a single chip, or the like, in a manner which assures, prior to implementing the modified layout in an integrated circuit chip, that the electronic circuit implemented by it has not inadvertently been modified in the process. Data of the existing layout is first run on a net list extractor computer software program in order to determine its net list. After the layout is modified by usual computer techniques, the modified layout data is run on the extractor program to obtain another net list, and the net lists are then compared for any undesired differences. Once the modified layout has been determined to be free of any such differences, a set of masks are made from the modified database. The masks are used then used to manufacture the integrated circuit.

Optimum Design of Reliable IC Power Networks Having General Graph Topologies

Abstract: This paper deals with the problem of sizing integrated circuit power and ground distribution systems external to the logic modules constituting an integrated circuit. Several constraints associated with the reliability of the power and ground distribution systems are formulated. Algorithms are developed to determine the widths of the power and ground routes so that the area required by the routes is minimized subject to the constraints imposed. Run time results are included.

Excellerator: custom CMOS leaf cell layout generator

Abstract: A description is given of a program, Excellerator, which automatically generates full-custom symbolic CMOS cell layouts. The input is a transistor-level netlist with optimal constraints on layout shape and I/O port positions. The output is a high-quality virtual-grid-based layout suitable for use in a two-dimensional tiling methodology. I/O port locations can be optimized. Versatile support for different layout shapes and port locations makes this system ideal for use in a top-down, fully automatic physical design system. Transistor routing is provided by a novel, recursive version of the A-Star search procedure. This technique reduces the frequency and seriousness of routing blockages by finding near-optimal compromises between new connections and reroutes of previous connections. Routing occurs in two metal layers plus polysilicon and diffusion, and is easily extendable to any number of routing layers. Routing priority can be given to critical nodes. >

GENAC: An Automatic Cell Synthesis Tool

Abstract: We present a solution to the layout problem of cell synthesis, which achieves multiple optimization objectives. In particular, we propose a new hierarchical method for fast and optimal placement of the transistors in a cell. The method minimizes the number of diffusion breaks, and allows a further pursuit of a secondary optimization objective, such as routing channel density. For cells with non-uniform transistor widths, the transistors are folded in such a way as to optimize a cost function which is a good approximation to the area of the final (compacted) layout of the cell. We also analyze the characteristic nature of routing in cell generation problem, and design an algorithm for doing routing over the transistors; such routing reduces the routing channel density in the central region of the cell. The routing in the central region is completed by a new channel router at, or near, the channel density. The algorithms are implemented in a system call GENAC. The input to GENAC is a transistor net list, describing the connectivity as well as the size and type of each transistor. The output is a synthesized layout of the cell in symbolic language.

Single-Layer Wire Routing and Compaction

Abstract: This pioneering study of two-dimensional wiring patterns develops powerful algorithms for the physical design of VLSI circuits. Its homotopic approach to circuit layout advances the state of the art in wire routing and layout compaction, and will inspire future research. By viewing wires as flexible connections with fixed topology, the author obtains simple and efficient algorithms for CAD problems whose previous solutions employed, unreliable or inefficient heuristics."Single-Layer Wire Routing and Compaction" is the first rigorous treatment of homotopic layouts and the techniques for optimizing them. In a novel application of classical mathematics to computer science, Maley characterizes the ideal routing of a layout in terms of simple topological invariants. He derives practical algorithms from this theoretical insight. The algorithms and their underlying ideas are intuitive, widely applicable, and presented in a highly readable style.F. Miller Maley is a Research Associate in the Computer Science Department at Princeton University. "Single-Layer Wire Routing and Compaction" is included in the series Foundations of Computing, edited by Michael Garey and Albert Meyer.

Physical modeling of GaAs MESFETs in an integrated CAD environment: from device technology to microwave circuit performance

Abstract: The linkage between a physical device simulator for small- and large-signal characterization and CAD (computer-aided design) tools for both linear and nonlinear circuit analysis and design is considered. Efficient techniques for the physical DC and small-signal analysis of MESFETs are presented. The problem of physical simulation in a circuit environment is discussed, and it is shown how such a simulation makes possible small-signal models accounting for propagation and external parasitics. Efficient solutions for physical large-signal simulation, based on deriving large-signal equivalent circuits from small-signal analyses under different bias conditions, are proposed. The small- and large-signal characterizations allow physical simulation to be performed efficiently in a circuit environment. Examples and results are presented. >

A highly flexible sea-of-gates structure for digital and analog applications

Abstract: A sea-of-gates structure optimized for digital random logic applications as well as for regular arrays and analog circuits is described. Associated with a dedicated design procedure and a systematic metallization strategy, the structure features a full cell-abutment capability and true channelless routing. After reviewing the advantages and limitations of currently available arrays, the main characteristics of the array architecture are presented, and applications to different circuit families are detailed. Design automation tools suited to the structure and design methodology are reviewed. Design results and performance are presented for several macroblocks and are compared with other semicustom approaches. A set of rules which allows an automatic transformation of the sea-of-gates layout into a topologically equivalent full-custom layout, converting semicustom prototypes to full-performance circuits, is presented. >

Accurate prediction of physical design characteristics for random logic

Abstract: An accurate model is presented for the prediction of physical design characteristics, such as interconnection lengths and layout areas, for standard cell layouts. This model produces accurate shape constraint functions (height versus width of the layout over a range of aspect ratios) by considering the logic design specification, the physical design process, and the physical implementation technology. Random and optimized placements, global and detailed routing are each abstracted by procedural models that capture the important features of these processes. Equations that define the procedure model are presented. Predictions of layout characteristics that are within 10% of the actual layouts are achieved over a range of circuit functions and sizes. The authors have verified both the global characteristics (total interconnection length and layout area) and the detailed characteristics (wire length and feedthrough distributions) of the model. Accurate prediction of physical design characteristics is useful for floorplanning, evaluating the fit of a logic design to a fabrication technology, and studying placement algorithms. >

LADIES: an automatic layout system for analog LSI's

Abstract: The authors have developed a prototype system for analog LSI layout design which ensures the functionality of circuits. The procedural initial layout program is based on a clustering algorithm and a river routing algorithm and it manipulates mathematically specified layout constraints. Before and after this program the system uses a knowledge base to manipulate complex conditions and thereby avoid circuit malfunction. Using circuit descriptions and knowledge about layout constraints as related to the circuits, a preprocessing program generates specific layout constraints which ensure the functionality of circuits. A postprocessing program eliminates unused space, taking the various constraints into account. The authors have also developed a predictive inference mechanism which selects suitable actions to get better results. In an experiment involving a 71-element block, the authors obtained a layout which follows all constraints and is only 8% larger than the manual layout. >

A CMOS-based analog standard cell product family

Abstract: Successful integration of mixed analog-logic standard cells has been demonstrated in a 1.0- mu m CMOS-based technology. Considerations for analog cell area, power distribution, noise immunity, circuit library design, and product test are described. >

Operational amplifier compilation with performance optimization

Abstract: A design methodology is described for analog circuits in which topological design is followed by simultaneous device sizing and layout design. By merging circuit and layout design into a single design process, analog circuits can be optimally designed, taking layout parasitics fully into account. Based on the methodology, a CMOS operational amplifier compiler (OAC) has been developed. Given a set of performance specifications and process parameters, OAC generates a layout with circuit performance optimized to meet specified performance constraints. A novel procedural layout technique is used for generating compact and practical layouts. A nonlinear optimization method is applied for device sizing that relies on the results of simulations based on the circuit extracted from the layout. Design experiments have shown that OAC can produce satisfactory results with respect to both circuit performance and layout density

Integrating the logical and physical design of electronically linked objects

Abstract: The interconnection costs of electronically linked objects is minimized by the successive partitioning of the initial logic design. The partitioning is based upon the electrical properties of the drivers and loads of the linked objects forming the design. Further, time critical connections are weighted so as to further minimize interconnection cost. A further method refines the result of the successive partitioning by calculating each linked object's contribution to the overall delay of the design. Both the design of device function and timing and the physical realization of the electronically linked objects are solved jointly to make use of the information available from the logical and physical designs.

IBM RISC chip design methodology

Abstract: An overview is given of the chip design methodology of the IBM Austin, Texas Advanced Workstation Division. The primary components of this methodology are a high-level language (DSL); a common database (CDB); synthesis, simulation, and floor planning tools; and custom-built circuit elements. The methodology and tools support a top-down design that begins with a high-level logic specification. The hierarchical nature of the methodology permeates all aspects of the design environment, beginning with logic entry, proceeding through physical implementation, and terminating with checking. New additions to the methodology include a high-level language, a synthesis tool, a hardware simulator, a third metal layer for better IO handling, a new min-cut placement program, and an RC estimator/calculator. >

ESD protection: design and layout issues for VLSI circuits

Abstract: The electrostatic discharge (ESD) design issues for input, output, and power bus protection of metal-oxide semiconductor very-large-scale integration (VLSI) devices are reviewed. For input pins, the critical layout techniques that determine primary and secondary protection circuits are reported. For output pins, the effective use of the output buffer itself as a protection circuit is discussed. An effective primary circuit for rapidly discharging large amounts of stress current is a thick-oxide device with optimized layout. This device with a grounded source diffusion can provide up to 6 kV of ESD protection for the human body stress model. Some of the recent advanced process features for enhancement of VLSI circuit reliability are presented, as well as their impact on the protection circuit design and layout. >

The design of a microprocessor

Abstract: 1. Introduction.- 1. Introduction.- 1.1. Overview.- 1.2. Structure of the Book.- 1.3. S/370 Architecture.- 1.4. Layered Processor Structure.- 2. Logic Design.- 2.1. Design Overview.- 2.1.1 Introduction.- 2.1.1.1 Design Goals.- 2.1.1.2 Processor Structure.- 2.1.2 Chip Set Description.- 2.1.2.1 Processing Unit (CPU) Chip.- 2.1.2.2 Memory Management Unit (MMU) Chip.- 2.1.2.3 Storage Controller (STC) Chip.- 2.1.2.4 Clock Chip.- 2.1.2.5 Control Store (CS) Chip.- 2.1.2.6 Floating Point Unit (FPU) Chip.- 2.1.3 Chip Interconnection Busses.- 2.1.4 Cache Timing Considerations.- 2.1.5 Miscellaneous.- 2.1.5.1 Reliability, Availability, Serviceability (RAS).- 2.1.5.2 System Measurement Interface (SMI).- 2.1.5.3 Other Processor Components.- 2.2. Processing Unit Chip.- 2.2.1 Design Considerations.- 2.2.2 Block Diagram Description.- 2.2.3 Modes of Operation.- 2.2.3.1 S/370 Mode.- 2.2.3.2 Micromode.- 2.2.3.3 Forced Operations.- 2.2.4 Pipelining.- 2.2.5 Data Local Store Layout.- 2.2.6 Micro Instructions.- 2.2.6.1 Data Local Store Addressing.- 2.2.6.2 Microinstructions Types and Formats.- 2.2.6.3 Reducing the Number of Branch Microinstructions.- 2.2.7 Data Flow Logic.- 2.2.7.1 ALU, Shift, Units and DLS.- 2.2.7.2 Bus Unit and Processor Bus Operations.- 2.2.8 Prefetch Buffer.- 2.2.9 Floating-Point Coprocessor Interface.- 2.3 Timer Support.- 2.3.1 Introduction to the Timer Functions.- 2.3.2 Format of the Timer Binary Counters.- 2.3.3 Functional Description and Block Diagram.- 2.3.4 Communication with the CPU.- 2.3.5 Programmable Clock Cycle Time.- 2.4. Memory Management Unit Chip.- 2.4.1 Overview.- 2.4.2 Storage Hierarchy Elements.- 2.4.2.1 Virtual Storage Addressing.- 2.4.2.2 Translation-Lookaside Buffer.- 2.4.2.3 Cache Operation.- 2.4.2.4 Key Store.- 2.4.2.5 Combined Operation.- 2.4.3 MMU Chip Data Flow.- 2.4.4 Array Macros.- 2.4.4.1 Translation-Lookaside Buffer (TLB).- 2.4.4.2 Cache Directory.- 2.4.4.3 Cache Array.- 2.4.4.4 Keystore.- 2.4.5 Storage Controller Interface.- 2.5. Storage Controller Chip.- 2.5.1 STC Chip Structure.- 2.5.1.1 Memory Control Unit.- 2.5.1.2 Error Correction Unit.- 2.5.1.3 STC Chip Interfaces.- 2.5.2 Memory Organization and Control.- 2.5.2.1 Overview.- 2.52.2 Memory Card.- 2.5.2.3 Memory Performance.- 2.5.2.4 Fetch Operation.- 2.5.2.5 Store Operation.- 2.5.3 Data Integrity.- 2.5.3.1 Refresh.- 2.5.3.2 ECC (Error Correction Codes).- 2.5.3.3 Complement Retry.- 2.5.3.4 Redundant Bit.- 2.5.3.5 Scrub.- 2.5.3.6 Address Fault Protection.- 2.5.4 Diagnostics.- 2.5.5 Personalization.- 2.6. Floating Point Coprocessor.- 2.6.1 General Description.- 2.6.2 Floating-Point Instructions and Data Format.- 2.6.3 FPU Interface and Communication.- 2.6.4 Chip Logical Description.- 2.6.4.1 Overview.- 2.6.4.2 Exponent Dataflow.- 2.6.4.3 Mantissa Dataflow.- 2.6.5 Reliability, Checking and Testing.- 2.6.5.1 Reliability.- 2.6.5.2 Checking.- 2.6.6 Performance.- 2.7. Bus Interface Chips.- 2.7.1 Overview.- 2.7.2 MBA Chip.- 2.7.3 BCU Chip.- 2.8. Clock Chip.- 2.8.1 Central Clock Generation Versus Distributed Clock Generation.- 2.8.2 Logical Implementation.- 2.8.3 Timing Tolerances, Reset and Checking.- 2.9. Clocking.- 2.9.1 Clock Signal Types.- 2.9.2 Clock Generation Flow.- 2.9.3 Clock Pulse Generation.- 2.9.4 Evaluation of the Clock Skews.- 2.9.5 Logic Chip Clock Distribution.- 2.9.5.1 Standard On-Chip Clock Distribution.- 2.9.5.2 High Performance On-Chip Clock Distribution.- 2.9.6 Evaluation of the Clocking Scheme.- 2.9.7 Clock Variation.- 2.10. Processor Bus.- 2.10.1 Processor Bus Connections.- 2.10.2 Processor Bus Implementation.- 2.10.3 Processor Bus Operation Example.- 2.11. Reliability, Availability, Serviceability.- 2.11.1 Overview.- 2.11.2 RAS Strategy and Requirements.- 2.11.3 Initial Chip Set Start and Loading.- 2.11.4 Error Detection.- 2.11.5 Machine Check Handling.- 2.11.6 Support Interface.- 2.11.6.1 Unit Support Interface Description.- 2.11.6.2 Unit Support Interface Operation.- 3. Logic Design Tools.- 3.1. Logic Design System Overview.- 3.2. Hardware Design Language.- 3.2.1 Overview.- 3.2.2 The Design Level.- 3.2.3 Design Rules Checks.- 3.2.4 The Macro Level.- 3.2.5 The System Level.- 3.2.6 Design System Dataflow.- 3.2.7 Overall Comparison with VHDL.- 3.3. Logic Synthesis.- 3.3.1 Overview.- 3.3.2 Logic Synthesis Methodology.- 3.3.3 LSS Overview.- 3.3.4 Technology Information.- 3.3.5 Partitioned Synthesis.- 3.3.6 Synthesis Experience.- 3.4 Logic Synthesis Design Experience.- 3.4.1 Overview.- 3.4.2 The Design System.- 3.4.3 Challenges in Using LSS.- 3.4.4 Delay Optimization and the Use of LSS.- 3.4.5 Results and Designers' Echo.- 3.4.6 Discussion.- 3.4.7 Conclusions.- 3.5. Timing Analysis and Verification.- 3.5.1 Overview.- 3.5.2 Delay Equations.- 3.5.3 Capacitance Estimate.- 3.5.4 Multiple Clock Designs.- 3.5.5 Multiple Cycle Paths.- 3.5.6 Global Timing Correction for Logic Synthesis.- 3.6. Logic Design Verification.- 3.6.1 Overview.- 3.6.2 The Concept of Using Logic Simulation.- 3.6.3 Modelling Requirements.- 3.6.4 The Phases in Logic Design Verification.- 3.6.5 What Drives the Simulation - Testcases.- 3.6.6 The Testcase Execution Control Program.- 3.7. Logic Simulation.- 3.7.1 Overview.- 3.7.2 Hardware Specification Languages.- 3.7.3 Compilation Techniques.- 3.7.4 Simulation Control.- 3.7.5 Distributed Simulation.- 4. CWp Technology.- 4.1 Chip Technology Overview.- 4.1.1 Technology.- 4.1.2 Circuit Libary and Chip Image.- 4.2. Master Image Chip.- 4.3. VLSI Book Library and Array Macros.- 4.3.1 Cell Design.- 4.3.2 Circuit Library.- 4.3.3 Sub-Circuit Elements.- 4.3.4 Macro Design.- 4.4. A New I/O Driver Circuit.- 4.4.1 Problem Definition.- 4.4.2 Driver Family.- 4.4.3 Dynamic Control.- 4.5. Embedded Array Macros.- 4.5.1 Array Configurations.- 4.5.2 Storage Cell and Circuit Design.- 4.5.3 Array Integration.- 4.5.4 Testing of Embedded Arrays.- 4.6. Packaging.- 4.6.1 Overview.- 4.6.2 First Level Packaging.- 4.6.3 Electrical Considerations.- 4.6.4 Second Level Package.- 5. Semiconductor Technology.- 5.1. Design for Testability.- 5.1.1 Overview.- 5.1.2 Failure Types and Failure Models.- 5.1.3 Structural Test.- 5.1.4 Design for Testability.- 5.1.5 LSSD (Level Sensitive Scan Design).- 5.1.5.1 Overview.- 5.1.5.1 LSSD Rules and Partitioning.- 5.1.6 Additional Test Features.- 5.1.6.1. Internal Tristate Driver.- 5.1.6.2 Observation Points.- 5.1.6.3 Logic Circuit Layout Optimized for Defect Sensitivities.- 5.1.7 Random Pattern Testing.- 5.1.8 Auto Diagnostic.- 5.2. Test and Characterization.- 5.2.1 Wafer and Module Test.- 5.2.1.1 Test Overview.- 5.2.1.2 Process Parameter Test.- 5.2.1.3 Logic Test on Wafer and Module.- 5.2.1.4 Functional Pattern Test.- 5.2.1.5 Logic Test Equipment.- 5.2.2 Failure Localization and Characterization.- 5.2.2.1 Second Metal Test.- 5.2.2.2 Internal Probing Station.- 5.2.2.3 Fail Locating by Internal Probing.- 5.2.2.4 Performance Verification.- 5.3. Semiconductor Process / Device Design.- 5.3.1 The Semiconductor Process.- 5.3.2 Layout Rules.- 5.3.3 Electrical Device Properties.- 5.4. Failure Analysis.- 5.4.1 Purpose of Failure Analysis.- 5.4.2 Failure Analysis Strategy and Methods.- 5.4.3 Failure Analysis Examples.- 5.4.3.1 Particles.- 5.4.3.2 Metal Interruptions at Steep Steps.- 5.4.3.3 Oxide Residues in Contact Holes.- 5.4.3.4 Leakage between Vdd and Ground.- 5.4.3.5 Signal to Ground Leakage.- 5.4.3.6 Source-Drain Leakage.- 5.4.3.7 Latch-Up.- 6. Physical Design Tools.- 6.1 Physical Design Concept.- 6.2 Hierarchical Physical Design.- 6.2.1 Methodology.- 6.2.2 Partitioning and Floorplanning.- 6.2.3 Implantation.- 6.2.4 Detailed Processing.- 6.2.5 Chip Assembly.- 6.3 Hierarchical Layout and Checking.- 6.3.1 Chip Layout.- 6.3.2 Chip Merge and Final Data Generation.- 6.3.3 Checking.- 6.4. Delay Calculator and Timing Analysis.- 6.4.1 Circuit Delay.- 6.4.2 Calculation Method and Simulation.- 6.4.3 Fitting Method (Least Square Fit).- 6.5. Physical Design Experience.- 6.5.1 Master Image Development.- 6.5.2 Physical Design.- 6.5.3 Hardware Bring-Up.- 6.5.4 Lessons Learned.- 7. System Implementation.- 7.1. ES/9370 System Overview.- 7.2. High Level Microprogramming in 1370.- 7.2.1 Overview.- 7.2.2 Concepts and Facilities.- 7.2.2.1 Processor Structure.- 7.2.2.2 Instruction Interpretation.- 7.2.2.3 Control Spaces and Associated Instructions.- 7.2.2.4 Mode Control and Associated Instructions.- 7.2.3 ES/9370 Realization.- 7.2.3.1 ES/9370 System Structure.- 7.2.3.2 Service Processor to I/O Controller Communication.- 7.2.3.3 Extending the Kernel Functions.- 7.2.3.4 Simulation Concept for I370 Programs.- 7.2.4 Conclusions and Outlook.- 7.3. System Bring-Up and Test.- 7.3.1 Overview.- 7.3.2 Bring-Up Strategy.- 7.3.3 Basic Bring-Up Process.- 7.3.3.1 Sub-Architectural Verification.- 7.3.3.2 Architecture Verification.- 7.3.3.3 Testing Under the PAS Control Program.- 7.3.3.4 System I/O and Interaction Testing.- 7.3.4 System Bring-Up.- 7.3.5 Regression Testing.- 7.3.6 Bring-Up Results and Error Corrections.- 7.3.6.1 Basic Bring-Up.- 7.3.6.2 System Bring-Up.- 7.3.7 Summary and Conclusions.- 7.4. Outlook.- Authors.- References.

A framework to evaluate technology and device design enhancements for MOS integrated circuits

Abstract: A hierarchical framework which connects device and technology design parameters to specific circuit applications is presented. The functional circuit blocks which are used in the framework are defined. Examples of the use of this framework for design-intensive circuits are given, and experimental data which show the impact of device design on these circuit applications are presented. Technology-intensive circuit examples are also given which demonstrate the effect of technology enhancements on specific circuit applications. >