Showing papers on "Physical design published in 1993"

Application generator for use in verifying a hierarchical circuit design

Abstract: A computer based system and method is provided for generating a design verification scheme for a hierarchical circuit design. A set of directives received describing design checks to be performed on a hierarchical circuit design. The directives are functionally decomposed into primitive functions required to perform them. A primary iteration level is established for each directive, and a data flow dependency is determined for the directives. Based on the data now dependency, a sequence or operations is organized. The operations are optimized in one or more ways to improve the efficiency of the design verification process. The optimized operations are coded into an application program which executes in a computer processor. The application program accesses the VLSI circuit design under review and performs the directives using the data structures allocated during schema generation.

Carafe: an inductive fault analysis tool for CMOS VLSI circuits

Abstract: Traditional fault models for testing CMOS VLSI circuits do not take into account the actual mechanisms that precipitate faults in CMOS circuits. As a result, tests based on traditional fault models may not detect all the faults that occur in the circuit. This paper discusses the Carafe software package which determines which faults are likely to occur in a circuit based on the circuit's physical design, defect parameters, and fabrication technology. >

An integrated multicomponent synthesis environment for MCMs

Abstract: The multicompact synthesis (MSS) integrated design environment for multichip modules (MCMs) is discussed. The MSS environment is centered in VHDL (very-high-speed integrated circuit hardware description language), WAVES (waveform and vector exchange specification), and PDL (performance description language). MSS provides four levels of automated synthesis support all the way from the behavioral level to MCM placement and routing, three levels of simulation support including behavioral, register, and switch levels, and tools for automated test-bench compilation and design validation for all synthesized designs. Three tutorial examples illustrate MSS algorithms and results. The primary example is the Find, which performs a bubble sort followed by binary search. It is used as the running example because it is small. Such small specifications, however, do not require MCMs. Two larger examples, the Move Machine and the Viper Microprocessor, are used to illustrate the results. >

Analog circuit testing based on sensitivity computation and new circuit modeling

Abstract: Analog circuit testing is considered to be a very difficult task, due mainly to the lack of fault models and accessibility to internal nodes. An approach is presented for analog circuit modeling and testing to overcome this problem. This circuit modeling is based on a sensitivity computation and on circuit structure, which are crucial in analog circuit testing. The testability of the circuit is achieved for the simple fault model and by functional testing. Component deviations are deduced by measuring a number of output parameters, and through sensitivity analysis and tolerance computation. Using this approach, adequate tests are identified for testing both catastrophic and soft faults. Some experimental results are presented. >

On the Physical Design of PRAMs

Abstract: We sketch the physical design of a prototype of a PRAM architecture based on Ranade’s Fluent Machine. We describe a specially developed processor chip with several instruction streams and a fast butterfly connection network. For the realization of the network we consider alternatively optoelectronic and electric transmission. We also discuss some basic software issues.

System and method for verifying a hierarchical circuit design

Abstract: A computer-based system and method is provided for building a representation of a hierarchical circuit design and component intrusions for the components making up the circuit design, as well as for verifying a design so-represented. For a subject hierarchical circuit design, a VLSI circuit design component representing a leaf design entity is isolated. A set of locations in the design where the component appears is determined. These locations represent unique instances of the leaf design entity. A set of links is associated with the VLSI circuit design component and the locations. The links connect various ones of the locations to one another to denote placement of the component within the hierarchical circuit design. To complete the representation, a set of instance counts is computed, one instance count for each location in the design where the component is represented. Each instance count denotes the number of instances of the component represented at the location with which the instance count is associated. Additional features of the invention include applicability to numerous types of design components (e.g., devices, nets, microprocessors, resistors), correspondence between each node of the inverse layout graph and a unique placement in the hierarchical circuit design, and the ability to determine intrusions according to any measure of proximity.

Design for manufacture

Abstract: The application of the design for manufacture (DFM) approach to the design of printed circuit boards is discussed. A system of design rules is used to ensure that designs meet manufacturing-related needs. The rules capture the requirements of factory processes, so that the needs of manufacturing are considered automatically in the design process. Further, they are flexible, and can be easily adapted to the requirements of different products, factories, and manufacturing processes. Bare-board testing and in-circuit test audits are run to ensure that the board will be testable after fabrication and assembly. >

Linear IC parasitic element simulation methodology

Abstract: Linear IC design requires an intimate understanding of how the physical circuit realization affects the electrical performance of the circuit. An overview of parasitic elements of consequence in linear IC design is followed by a straightforward methodology to include these physical considerations into the electrical schematic such that the circuit simulations will take these elements into account. A design example including normal simulation, parasitic simulation, and bench test results is presented. This methodology allows the designer to more completely describe the circuit and improve the chances for first time design success. >

A genetic algorithm for channel routing in vlsi circuits

Abstract: A new genetic algorithm for channel routing in the physical design process of VLSI circuits is presented. The algorithm is based on a problem-specific representation scheme and problem-specific genetic operators. The genetic encoding and our genetic operators are described in detail. The performance of the algorithm is tested on different benchmarks, and it is shown that the results obtained using the proposed algorithm are either qualitatively similar to or better than the best published results.

Automatic generation of parasitic constraints for performance-constrained physical design of analog circuits

Abstract: A design methodology for the physical design of analog circuits is proposed. The methodology is based on the automatic generation of constraints on parasitics introduced during the layout phase from constraints on the functional performance of the circuit. In this novel performance-constrained approach, the parasitic constraints drive the layout tools to reduce the need for further layout iterations. Parasitic constraint generation involves (1) generation of a set of bounding constraints on the critical parasitics of a circuit to provide maximum flexibility to the layout tools while meeting the performance constraints; and (2) deriving a set of matching constraints on the parasitics from matched-node-pair and matched-branch-pair information in differential circuits. The constraint generator PARCAR is described and results presented for test circuits. >

A timing driven N-way chip and multi-chip partitioner

Abstract: With the growing complexity of integrated circuits and the advent of new technologies and new generations of packaging technologies, an essential physical design tool is a flexible physical partitioner. We therefore present a timing driven n-way chip and multi-chip partitioner which we call Tomus. The partitioner enables an automatic layout package to (1) divide and conquer the physical design process of field programmable gate array (FPGA) circuits or mixed macro/standard cell circuits and (2) physically partition a circuit onto n chips for a multichip package. Using a two-phased natural and adaptive clustering method, the annealing-based N-way partitioner executes four to 22 times faster with improved partitioning results. The placement results for industrial FPGAs were improved by 90% over the only available industrial placement tool. Our partitioner outperformed an industrial FPGA partitioner by 95% in MCM partitioning.

System and method for formulating subsets of a hierarchical circuit design

Abstract: A computer-based system and method is provided for building subsets of a hierarchical circuit design. A VLSI circuit design component is stored in computer memory. The design component identifies a leaf design entity in the hierarchical circuit design. A set of placements is determined representing positions in the hierarchical circuit design where the VLSI circuit design component appears. The placements form a subset of instances of the leaf design entity. A set of links is created. The links are associated in memory with both the VLSI circuit design component and the placements, and connect various ones of the placements to one another to further denote placement of the VLSI circuit design component within the hierarchical circuit design. A subset list is appended to the VLSI circuit design component in computer memory. The subset list denotes the previously-determined subset and includes placements where the VLSI circuit design component is identified in the hierarchical circuit design. The identified placements may indicate exclusion of a particular instance of a design component from the hierarchical circuit design, or inclusion of a particular instance.

A communications-based technique for interdisciplinary design team management

Abstract: A technique for interdisciplinary design team management that focuses on information processing and communication between team members is presented. A cognitive model of communication-related failure mechanisms of design groups is developed. Strategies for defining and assigning subtasks among individuals or subgroups that are based on the communications model are described. A technique for evaluating the expected effectiveness of a design team configuration is also presented. The cognitive model and task definition and assignment strategies are integrated into a tool which is traditionally used to evaluate only the physical design artifact itself, failure modes and effects analysis (FMEA). By determining communication failure mechanisms and how they can affect the design artifact, the authors are able to develop strategies that minimize their impact and an analytic tool to determine design team effectiveness. An illustrative application to the problem of designing a program for computer-assisted instruction is presented. >

Hierarchical design space exploration for a class of digital systems

Abstract: This paper presents an architectural synthesis approach for a widely used class of digital systems characterized by inherent regularity in their description. This approach relies on a novel modeling or abstraction of the problem domain to facilitate a hierarchical solution method. The modeling is based on exploiting the inherent regularity in the system description to cluster its behavioral operations. The method emphasizes prudent postponement of design decisions until enough physical design information is available to estimate layout effects like wiring; we use well-known area-delay estimators for this purpose. The approach has the advantage that it keeps track of a set of potentially good candidate solutions, rather than narrowing down to a single solution very early in the design process. Through an extensive set of experiments on well-known DSP design examples, we demonstrate the advantages that such distinctive features have to offer; the impact of hierarchy on several important issues, such as interconnection area, extent of design space explored, etc., is presented. >

General framework for configuration design: Part 1—methodology

Abstract: SUMMARY Configuration design is a type of conceptual design activity in which physical systems are synthesized from a set of predefined components that can be combined only in certain ways. A general framework for automated configuration of systems is presented in this paper. In this framework, design specifications are separated into functions, performance goals and constraints. Starting with design specifications, a skeletal design comprising essential functions is first configured. The process of mapping functions to physical devices is interleaved with the function decomposition process. The level at which a function is mapped to a physical device is directly related to the stringency of performance goals and constraints. Configuration design issues, such as function sharing, detail resolution of the building blocks and the possible explosion of the number of feasible permutations, are also discussed. This paper ( Part 1) describes organization of the design knowledge and the design methodology. Based...

Using transformations and verification in circuit design

Abstract: We show how machine-checked verification can support an approach to circuit design based on transformations. This approach starts with a conceptually simple (but inefficient) initial design and uses a combination of ad hoc and algorithmic transformations to produce a design that is more efficient (but more complex).

Power management for programmable logic devices

Abstract: A programmable circuit is provided with a number of current regulating circuits, such as sense amplifiers, by which the user can regulate the amount of current drawn by any of a number of circuit functions within the programmable circuit. Additional current regulating circuits are associated with circuit elements which can be programmably shared between one or more circuit functions. The user can therefore programmably control the current consumption, and thereby the speed, of each circuit function as well as circuit functions interacting via the shared circuit elements.

Rapid estimation for parameterized components in high-level synthesis

Abstract: An important benefit of high-level synthesis is rapid design space exploration through examination of different design alternatives. However, such design space exploration is not feasible without fast and accurate area and delay estimates of the synthesized designs. These estimates must factor in physical design effects and technology-specific information in order to achieve accuracy. High-level synthesis tools often use abstract, parameterized component generators for describing the synthesized RT design, and thus need to be supported by fast and accurate estimators for these parameterized RT-components. Ideally, one would like to obtain the actual area and delay attributes of each component by constructing (or generating) the designs. However, such constructive methods require excessive run times, prohibiting on-line integration with the tasks of scheduling and allocation. This paper describes a fast (constant-time) method for estimating the area and delay of regular-structured generic RT components that are tuned to a particular technology library. The estimation models are generated using a least-square approximation on a set of sample data points from selected component implementations. The authors performed an extensive set of experiments to validate the estimation technique on combinational as well as sequential RT component generators. The results show a prediction of the area and delay to within 10% of the actual values. These models have also been integrated with a high-level synthesis system to permit on-line estimation of a component's area and delay. >

Method and device for designing layout of milliwave or microwave integrated circuit.

Abstract: A method of layout designing a milliwave or a microwave IC using a CAD system includes a step of displaying each of a plurality of kinds of concentrated constant circuit elements and distributed constant transmission lines of an IC chip to be designed on a CRT display (16) with a drawing object closed on the plane, which area and dimension represent electrical data, a step of connecting the drawing objects on the CRT display (16) by overlapping edges with each other and producing a virtual IC, a step of optimizing the layout of the virtual IC by changing the areas, dimensions, or arrangement of the respective drawing objects of the virtual IC so that the entire area of the virtual IC is as minimum as possible and the electrical characteristics of the virtual IC are desired ones, and a step of producing a mask pattern for IC production by logical operation between the drawing objects of the layout data of the virtual IC by utilizing the virtual IC which comprises collections of the drawing objects closed on the plane. Therefore, the data for optimizing layout of the IC comprises only the data required for electrical design of the integrated circuit to be designed, a memory required for executing a circuit simulation for optimizing the electrical characteristics is reduced, and the processing speed of the circuit simulation is reduced.

Automatic layout of analog and digital mixed macro/standard cell integrated circuits

Abstract: This thesis presents computer algorithms for the design of electronic integrated circuits or microchips. As consumer demand increases for such circuits, IC manufacturers are continually faced with a dilemma; provide superior products in shorter time frames. Provided within are advantageous techniques to relieve this time-to-market crisis. Specifically, algorithms are presented to reduce the time of the physical design (layout) phase, the placement and interconnection of the transistors which constitute the integrated circuit. TimberWolf version 7, a new fully automatic placement and routing system is described. This tool exploits the advantages of the semicustom design style through the combination of macro and standard cells. Additionally, we will present a simulated annealing macro cell layout program which features new methods for statistical wiring estimation, placement refinement, and detailed routing. Performance and area are the fundamental objectives of layout tools. A novel algorithm which controls timing delay without the need for user path specification is presented. This algorithm was able to increase the speed of the fract benchmark chip by 34% at an area cost of only 2.5%. We will present the first generalized row-based global router suitable for standard cell, gate-array, sea-of-gates, and FPGAs that explicitly minimizes chip area. This new global router adapts to technologies enabling it to outperform its predecessors.

Design for packageability-early consideration of packaging from a VLSI designer's viewpoint

Abstract: Designing VLSI dies without considering packaging issues may result in a suboptimum system. It is argued that before the design of VLSI dies is completed, packaging issues should be evaluated, since they may affect choices in VLSI circuit design and layout. To illustrate this, the design of an image processing chip-set of three integrated circuits for wire-bond printed circuit board (PCB) and flip-chip multichip module deposited (MCM-D) technologies is reviewed. It is shown that the characteristics of these chips vary, since they are designed with different packaging in mind. >

Pin programmable dram that provides customer option programmability

Abstract: The described embodiments of the present invention provide a circuit and method for selecting an organization and for programming mode options of an integrated circuit. The embodiment described provides this function for a dynamic random access memory but is applicable to any integrated circuit. The integrated circuit includes programming lead pins, connected to respective programming bond pads, which are selectably connectable to an external reference potential. Circuitry on the integrated circuit provides logical signals that select the operational organization and mode options of the integrated circuit.

Practical methods for worst-case and yield analysis of analog integrated circuits

Abstract: Worst-case analysis is commonly used in integrated circuit design to verify a satisfactory circuit performance with regard to changes in the manufacturing conditions. However, worst-case analysis is often carried out using approximate worst-case parameter sets. This paper presents a new approach to the worst-case design of integrated circuits that takes account of fluctuations in the operating conditions. It provides exact and unique worst-case manufacturing conditions and worst-case operating conditions for given circuit specifications. These specifications may be either performance limits or minimum yield requirements. The method is illustrated with the parametric design of integrated CMOS bias stages.

Coupling a Statistical Process-Device Simulator with a Circuit Layout Extractor for a Realistic Circuit Simulation of VLSI Circuits

Abstract: This paper discusses methodology of statistical simulation of an IC design which includes disturbances described by independent random variables, spatially correlated random disturbances and deterministic process parameters distribution on a wafer. The method of coupling of a process/device simulator with a circuit extractor is proposed. Practical example of an operational amplifier design optimization is presented.

Linking register-transfer and physical levels of design

Abstract: Author(s): Kurdahi, F J.; Gajski, D. D.; Ramachandran, C.; Chaiyakul, V. | Abstract: System and chip synthesis must evaluate candidate Register-Transfer (RT} architectures with respect to finished physical designs. Current RT level cost measures, however, are highly simplified and do not reflect the real physical design. Complete physical design, on the other hand, is quite costly, and infeasible to be iterated many times. In order to establish a more realistic assessment of layout effects, we proposed a new layout model which efficiently accounts for the effects of wiring and floorplanning on the area and performance of RT level designs, before the physical design process. Benchmarking has shown that our model is quite accurate.

Logic design system and circuit transformation rule compiler

Abstract: A plurality of types of circuit transformation rules have condition parts and conclusion parts. An inference control knowledge includes a knowledge related to a method of inferring the circuit transformation rules and a knowledge related to a relation between the circuit transformation rules. The circuit transformation rules are compiled into circuit transformation programs by use of the inference control knowledge. Already-existing programs include a procedural process of a logic design and various functions necessary for an execution of the circuit transformation programs. The circuit transformation programs and the already-existing programs are combined into a logic design program. A circuit transformation process is executed in accordance with the logic design program.

Efficient statistical analysis of microwave circuit performance using design of experiments

Abstract: Variations of circuit dimensions and material parameters about their nominal values result in microwave circuits that do not perform as expected. The authors describe how the method of design of experiments (DOE) may be used with circuit simulations to statically characterize the effects that variations of these circuit factors have on circuit performance. When applied to circuit simulations, the method allows the design engineer to assess the manufacturability and robustness of a linear microwave circuit design early in the design process. The results of a study that uses DOE for the reflection coefficient performance of an antenna radiator circuit are presented. >

Tutorial on design for testability (DFT) "An ASIC design philosophy for testability from chips to systems"

Abstract: This is a comprehensive tutorial on DFT with emphasis on concepts of digital Application Specific Integrated Circuit (ASIC) testing incorporating boundary scan architecture in ASIC design. This tutorial covers discussion and features of Institute of Electrical and Electronics Engineers (IEEE) Standard 1149.1, Joint Test Action Group (JTAG) test technique, that can be implemented during design and development of digital ASIC and systems. These test techniques can be applied to test device mounted multi-layer Printed Circuit Boards (PCBs) and Multi Chip Modules (MCMs). >

Design verification techniques for system level testing using ASIC level BIST implementations

Abstract: Requirements and design verification techniques for system level testing using BIST implementations in ASICs are discussed. A logic simulation technique is presented which determines whether reproducable BIST results can be obtained during system level testing. Using this approach, problems which could lead to nonreproducible BIST results during system level testing can be easily identified and corrected during device level of design,. >

An integrated approach to pin assignment and global routing for VLSI building-block layout

Abstract: An efficient algorithm integrating global routing, pin assignment, block reshaping and positioning, which is based on a rip-up and reroute and the simulated evolution technique, is presented. Experimental results show that the proposed algorithm achieves up to 10.5% reduction of chip area and up to 34.6% reduction of total wire length compared with previous methods. >