Showing papers on "Physical design published in 1995"

Minimizing power consumption in digital CMOS circuits

Abstract: An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. The most important technology consideration is the threshold voltage and its control which allows the reduction of supply voltage without significant impact on logic speed. Even further supply reductions can be made by the use of an architecture-based voltage scaling strategy, which uses parallelism and pipelining, to tradeoff silicon area and power reduction. Since energy is only consumed when capacitance is being switched power can be reduced by minimizing this capacitance through operation reduction choice of number representation, exploitation of signal correlations, resynchronization to minimize glitching, logic design, circuit design, and physical design. The low-power techniques that are presented have been applied to the design of a chipset for a portable multimedia terminal that supports pen input, speech I/O and full-motion video. The entire chipset that performs protocol conversion, synchronization, error correction, packetization, buffering, video decompression and D/A conversion operates from a 1.1 V supply and consumes less than 5 mW. >

Rectangle-packing-based module placement

Abstract: The first and the most critical stage in VLSI layout design is the placement, the background of which is the rectangle packing problem: Given many rectangular modules of arbitrary size, place them without overlapping on a layer in the smallest bounding rectangle. Since the variety of the packing is infinite (two- dimensionally continuous) many, the key issue for successful optimization is in the introduction of a P-admissible solution space, which is a finite set of solutions at least one of which is optimal. This paper proposes such a solution space where each packing is represented by a pair of module name sequences. Searching this space by simulated annealing, hundreds of modules could be successfully packed as demonstrated. Combining a conventional wiring method, the biggest MCNC benchmark ami49 is challenged.

Integrated circuit yield management and yield analysis: development and implementation

Abstract: Integrated circuit manufacturing yields are not necessarily a function of chip area. Accurate yield analysis shows how the yield depends on circuit design and layout. By determining the probabilities of failure and critical areas for different defect types, it is possible to control and manage the yield of integrated circuits. This includes the manufacture of DRAM's, SRAM's, CMOS logic, ASIC's, and CMOS and biCMOS microprocessors. Examples explain the method of meeting yield objectives by setting targets for yield components. In addition, the yield management approach allows for a systematic allocation of resources. Required defect-density learning determines the contamination levels for clean rooms and process equipment. >

Layout method for semiconductor integrated circuit and layout apparatus for semiconductor integrated circuit

Abstract: There is disclosed a layout method for a semiconductor integrated circuit for use in design by a symbolic layout which expresses a configuration of the semiconductor integrated circuit by symbols. The layout method comprises the steps of extracting a mask layout to be processed, changing dimensions of a symbolic layout included in the mask layout, replacing transistor symbols included in the mask layout with symbols having diffusion layer terminals each having a constant length in the channel width direction and not having extent in the channel length direction, shortening a length of wiring included in the mask layout in the channel width direction of the transistor, and compacting the mask layout in the channel length direction of the transistor.

Worst-case analysis and optimization of VLSI circuit performances

Abstract: In this paper, we present a new approach for realistic worst-case analysis of VLSI circuit performances and a novel methodology for circuit performance optimization. Circuit performance measures are modeled as response surfaces of the designable and uncontrollable (noise) parameters. Worst-case analysis proceeds by first computing the worst-case circuit performance value and then determining the worst-case noise parameter values by solving a nonlinear programming problem. A new circuit optimization technique is developed to find an optimal design point at which all of the circuit specifications are met under worst-case conditions. This worst-case design optimization method is formulated as a constrained multicriteria optimization. The methodologies described in this paper are applied to several VLSI circuits to demonstrate their accuracy and efficiency. >

Circuit designing apparatus of an interactive type

Abstract: A circuit designing apparatus of an interactive type which enables a simplified and high-speed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.

Energy consumption modeling and optimization for SRAM's

Abstract: The recent trends in portable computing technologies have established the need for energy efficient design strategies. To achieve minimum energy design goals, system designers need a technique to accurately model the energy consumption of their design alternatives without performing a full physical design and full-circuit simulation. This paper presents and compares five approaches for modeling the energy consumption of CMOS circuits. These five modeling approaches have been chosen to represent the various levels of model complexity and accuracy found in the current literature. These modeling approaches are applied to the energy consumption of SRAM's to provide examples of their use and to allow for the comparison of their modeling qualities. It was found that a mixed characterization model-using a CV/sup 2/ prediction for digital subsections and fitted simulation results for the analog subsections-is satisfactory (within /spl plusmn/1 process variation) for predicting the absolute energy consumed per cycle. This same model is also very good (within 2%) for predicting an optimum organization for the internal structures of the SRAM. Several common architectures and circuit designs for SRAM's are analyzed with these models. This analysis shows that global, rather than local improvements, produce the largest energy savings. >

Computer implemented method for producing optimized cell placement for integrated circiut chip

Abstract: In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement. Alternatively, the processors can perform different optimization processes simultaneously on a single initial placement, with the resulting processed placement having the highest fitness being selected as the optimized placement. The processors can further selectively reprocess areas of a placement having high cell interconnect congestion or other low fitness parameters.

Program and method for establishing a physical database layout on a distributed processor system

Abstract: A method and program for use with a massively parallel processor (MPP) system or a distributed computer system for providing a physical design layout database across several nodes of the system. A user inputs a first datafile representing the physical configuration of the distributed processor system, and inputs a second datafile representing application tablespaces and/or database system files to be stored in the distributed processor system. The program optionally assigns the tablespaces in the second datafile to the physical configuration of the distributed processor system as specified in the first datafile and per the number of nodes, number of disks per node, and the size of the disks. The user may optionally use the physical design layout of the program, may change a portion of the intermediate physical design layout, or may provide the entire physical database design layout, as desired. The program generates a logical volume map for the tablespaces distributed over the distributed processor system, and further generates scripts to implement the tablespace structure into a physical database.

Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints

Abstract: A process for designing an integrated circuit chip includes specifying a set of cells, a set of wiring nets for interconnecting the cells, and a set of regions on the chip in which the cells are to be placed. An assignment of the cells of the set to the regions is generated, and the set of cells is randomly divided into a first subset of cells which remain in the assignment, and a second subset of cells which are removed from the assignment. Penalties are computed for assigning the cells of the second subset to the regions respectively, and the cells of the second subset are assigned to the regions such that a total penalty thereof is minimized. The process is repeated iteratively with the size of the second subset being progressively reduced relative to the size of the first subset until an end criterion is reached.

Coping with RC(L) interconnect design headaches

Abstract: Physical interconnect effects have a dominant impact on today's deep submicron IC designs. In this tutorial paper we will describe the technology trends which have brought about this interconnect dominance, then consider some of the modeling and analysis approximations available for both pre- and post-layout interconnect design. This coverage will not be an exhaustive summary, but one that is primarily focused on moment-based analysis techniques, from the Elmore delay, to the more recent advances in moment-matching approximations, and the corresponding nonlinear driver/load interfaces. Future modeling, analysis, and design challenges will be considered throughout this paper.

Timing-driven integrated circuit layout through device sizing

Abstract: A method and apparatus for determining the layout of an integrated circuit, in accordance with timing constraints, by means of sizing the buffers in the layout. A nominal netlist for the layout of the integrated circuit is used to determine critical paths through the circuit. The time-critical paths are determined and the instances of the buffers along the path are resized so that the time delays in the time-critical paths are either brought within the predetermined timing criteria, or no further improvement in any time-critical path is possible.

Programming programmable transistor devices using state machines

Abstract: An integrated circuit with programmable transistors is programmed via a state machine on the integrated circuit For example, the integrated circuit may be a programmable logic device, and the state machine may be a JTAG state machine Each integrated circuit may have on it a register containing data indicating how long a particular programming operation should continue in order to be successful for that circuit External programming control apparatus first reads that data and then at least partly bases the timing of programming instructions applied to the integrated circuit on that data The integrated circuit may have an on-board programming voltage generating circuit which is turned on only by appropriate instructions from the external programming control apparatus The external programming control apparatus controls the sequence and timing of all programming operations via the state machine port of the integrated circuit

Analog IC design automation. I. Automated circuit generation: new concepts and methods

Abstract: The research presented in this paper is concerned with the automation of analog integrated circuit design and, in particular, with a description of methods and techniques employed by the ISAID design system developed at Imperial College, UK. ISAID is comprised of two modules: the circuit generator and the circuit corrector. The circuit generator is based on newly developed methods that are used to handle hierarchical generation of topologies and size MOS transistors so that the performance of designed circuits compare satisfactorily with their specifications. To avoid long design times, simulation is used only after the generation of an initial circuit topology. Simulated performances may therefore be found to differ from the required. One novel feature of the proposed methodology is that in such cases a circuit corrector is invoked to correct the initial design. The circuit corrector is essentially a novel application of qualitative reasoning, which, without iterative simulation analyses performance trade-offs, thereby selects circuit adjustments-transistor size adjustments or topological modifications-that would improve the problematic performances. Several design examples have demonstrated the benefits of the ISAID design approach. >

Method and apparatus for making incremental changes to an integrated circuit design

Abstract: An incremental circuit design methodology using logic synthesis where comparisons are made between netlists corresponding to two separate versions of a design to determine similarities between the two. The similarities are then used to ensure the same physical implementation for the unchanged portion of the design. Therefore, information from the physical implementation of the previous design may be used in implementing the later design.

Power estimation techniques for integrated circuits

Abstract: With the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. Recently, a variety of power estimation techniques have been proposed, most of which are based on: 1) the use of simplified delay models, and 2) modeling the long-term behavior of logic signals with probabilities. The array of available techniques differ in subtle ways in the assumptions that they make, the accuracy that they provide, and the kinds of circuits that they apply to. In this tutorial, I will survey the many power estimation techniques that have been recently proposed and, in an attempt to make sense of all the variety, I will try to explain the different assumptions on which these techniques are based, and the impact of these assumptions on their accuracy and speed.

Interactive circuit designing apparatus

Abstract: The invention provides an interactive circuit designing apparatus wherein a logic design, a layout design and a speed analysis can cooperate with each other in processing. The interactive circuit designing apparatus comprises a logical designing section for logically designing a design object circuit, a layout designing section for performing mounting arrangement of logical components constituting a design object circuit based on a result of the logical design and performing wiring between the logical components, and a speed analysis section for performing a speed analysis based on calculation of a delay for each of paths on the design object circuit in accordance with a result of the layout. The logical designing section, the layout designing section and the speed analysis section are connected to each other so as to cooperate with each other when necessary. The interactive circuit designing apparatus is applied to an apparatus for designing a circuit of an LSI, a printed circuit board or a like element.

Hierarchical floorplanner for gate array design layout

Abstract: A set of logic cells is hierarchically grouped to form groups to be placed on an integrated circuit for gate array layout. A user interface allows a user to interact with a placement system. The system is supplied with input design files defining the integrated circuit, the cells to be grouped, the groups to be placed, and input/output buffers to be placed on the perimeter of the integrated circuit for connecting the groups with external circuitry. The system reads the input design files to create a database used for placing desired input/output buffers and for hierarchically grouping the cells and placing the groups. The groups are defined by their size, determined using utilization and aspect ratio values of the areas where the cells are to be placed. The user is allowed to move the buffers and groups to any valid locations within the integrated circuit.

Automating photolithography in the fabrication of integrated circuits

Abstract: Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing. Manufacturing data including process and yield parameters is then transferred back to the Rayleigh processor for use in the designing of subsequent circuits. In this way, a direct coupling exists between the measurement of wafer process parameters and the automated sizing of semiconductor devices, enabling the production of circuits having the smallest manufacturable device sizes available for the given lithography and wafer process.

Semiconductor integrated circuit for developing a system using a microprocessor

Abstract: An application system using a large scale semiconductor integrated circuit is provided with a connection. A programmable semiconductor integrated circuit is connected to the application system via the connection and an input/output terminal of the programmable semiconductor integrated circuit. The programmable semiconductor integrated circuit is provided with a microprocessor connector, to which a probe of an ICE is connected. The programmable semiconductor integrated circuit functions as a peripheral circuit contained in the large scale semiconductor integrated circuit, so that the conventional ICE can be used.

Method and apparatus for the cross-sectional design of multi-layer printed circuit boards

Abstract: Disclosed is a design tool and a method of fabricating a multi-layer printed circuit board. The method utilizes the design tool. The knowledge base means has both (1) printed circuit board cross sectional geometric parameter to transmission line parameter data and (2) "IF . . . THEN . . . " production rules for lamination, registration, circuitization, testability, test tools, and test procedures. These tools relate to manufacturability, cost, test development, second level packaging and printed circuit board. The printed circuit board begins with the user entering the printed circuit board design parameters and performance parameters into the input/output interface. Next, the knowledge base production rules are applied to the printed circuit board design and performance parameters to generate a set of cross section designs meeting the user specified parameters. The printed circuit board is then built up in accordance with one of the generated cross section designs.

Programmable multiplexing input/output port

Abstract: An input/output port design for integrated circuits which improves communications bandwidth. Through multiplexing techniques the design creates virtual input/output pins (40, 41) while utilizing a single physical pin (44, 45). The virtual pins improve the communications bandwidth while minimizing the physical design of the integrated circuit. The invention can be utilized in a variety of integrated circuits, including programmable logic devices and field programmable gate arrays (14).

Method and apparatus for a universal programmable boundary scan driver/sensor circuit

Abstract: A circuit and technique is described for adding boundary scan test capability to circuit boards and systems, thereby improving the ability to test and verify proper operation of such systems using nonintrusive methods. An integrated circuit consisting of a serial path of input/output buffers, an instruction register, and a serial test access port circuit is described. The integrated circuit can be coupled to a number of input and output signals, and the serial test bus is then used in conjunction with the test access port and instruction register circuitry to observe or control any or all of the signals present at the pins of the integrated circuit. Each pin may be programmed as an input or output for a particular operation. Because the integrated circuit is programmable and can be applied to any system, the need for design of special test hardware is eliminated, and the user may build in boundary scan capability into any arbitrary system. This is of particular importance when adding test capability to systems comprised of an array of off-the-shelf components, many of which do not have these capabilities.

Integrated circuit design and manufacturing method and an apparatus for designing an integrated circuit in accordance with the method

Abstract: A method for designing an integrated circuit involves a four step process. First, a behavioral circuit model (BCM) is read which contains assignment statements which identify the logical operation of an integrated circuit (IC). The BCM is translated to a data file which described a plurality of interconnected logic gate functions to duplicate the operation of the BCM. The gates in the data file are then assigned a specific Vdd and ground rail size, a specific drive strength for speed considerations, and a cell pitch or height to optimize physical layout, in any order. The result in a physical design file which may be used to form masks and integrated circuits having optimized speed and optimized circuit area in a short design cycle.

Efficient generation of fill shapes for chips and packages

Abstract: An efficient method for modifying a chip or package design allows for the creation of small shapes without excessive expansion of design data. A computer program takes a physical design, represented in a computer data file, and generates a modified version of the design in which fill shapes have been added. Subsequently, when the modified design is processed, the resulting semiconductor chip or package will contain physical images of the added fill shapes, with the effect of making local pattern density more uniform and hence reducing process-induced variations in feature size and shape.

LSI design automation system

Abstract: An improved LSI design automation system is disclosed which is implemented by making optimum reuse of previously applied design method information. This LSI design automation system includes the following: an input unit, a circuit component storage unit, a circuit component selection unit, a design method decision unit, a design process unit, and a component entry unit. The input unit receives LSI function and performance information as a requirements specification and LSI component configuration information. The circuit component storage unit collectively stores a circuit data item, design method information items, and performance information items, as a circuit component. The circuit component selection unit selects a circuit component from the circuit component storage unit for implementation of a desired circuit. The design method decision unit selects an optimum design method information item from the design method information items held by each circuit component. The design process unit generates, modifies, and evaluates a circuit. The component entry unit enters a result of the modification made during the design and a newly generated circuit component into the circuit component storage unit.

High-Frequency Analog Integrated Circuit Design

Abstract: Integrated Circuit Processing Technology MESFET Design and Modelling Schottky Diode and Passive Components Basic Building Blocks Wideband Amplifiers Operational Amplifiers Mixers and Oscillators Data Conversion Circuits Synthesis of Linearized Conductance Functions.

Automated method and system for designing an optimized integrated circuit

Abstract: An automated method and system for designing an integrated circuit are disclosed which construct an initial substrate layout of the integrated circuit in response to receipt of a high-level functional description of an integrated circuit. The initial substrate layout, which includes a number of subcircuits electrically connected by a number of interconnects, is constructed based upon estimated timing characteristics of the subcircuits. Next, particular subcircuits are arranged to optimize performance of the substrate layout of the integrated circuit. Performance characteristics of the substrate layout, including timing characteristics of the number of subcircuits and resistive and capacitive characteristics of the number of interconnects, are then determined. In response to a determination of the performance characteristics of the substrate layout, operating power levels of selected subcircuits and resistances of selected interconnects are adjusted to optimize performance of the substrate layout. Thereafter, the step of determining performance characteristics of the substrate layout is repeated. In response to the repeated determination of the performance characteristics of the substrate layout, routing of the number of interconnects electrically connecting the number of subcircuits is finalized. Thus, performance of the substrate layout of the integrated circuit is optimized by iteratively refining the initial substrate layout utilizing performance characteristic data.

Method of stabilizing component and net names of integrated circuits in electronic design automation systems

Abstract: A method used by an electronic design automation system for stabilizing the names of components and nets of an integrated circuit from one design version to another. A previous integrated circuit design version and a current integrated circuit design version are partitioned into multiple cones of logic design. Each cone of logic design is defined by a path from a logic designer-defined apex net to a logic designer-defined base net affecting the apex net. Selected cones of logic design are compared. If the selected cones have identical logical structure, the component and net names of the previous integrated circuit design version are transferred to the current integrated circuit design version. If the selected cones of logic design do not have identical structure, then the component and net names for subsections of the selected cones of logic design that do have identical logical structure are transferred to the current integrated circuit design version, and new component and net names are assigned to those subsections of the selected cones of logic design from the current integrated circuit design version which did not exist in the previous integrated circuit design version.

Logic gate size optimization process for an integrated circuit whereby circuit speed is improved while circuit area is optimized

Abstract: An integrated circuit, when designed, must adhere to timing constraints while attempting to minimize circuit area. In order to adhere to timing specifications while arriving at a near-optimal circuit surface area, an iterative process is used which selectively increases logic gates sizes by accessing logic gates from a memory stored logic gate library. A circuit representation is read along with timing constraints for circuit paths. Each circuit path in the circuit is processed to find it's actual circuit path delay. A most out-of-specification circuit path (in terms of speed) is chosen in the circuit and a sensitivity calculation is performed for each logic gate in the most out-of-specification circuit path. The logic gate in the circuit path with the maximized sensitivity (sensitivity=Δspeed/Δarea) is increased in size by accessing a larger gate in the library in order to improve speed at the expense of area. The above process continues iteratively until no out-of-specification circuit paths are found.