Showing papers on "Physical design published in 1999"

The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout

Abstract: For Pt.I see ibid., vol.7, pp.191-7 (1999). Field-programmable gate arrays (FPGA's) are now widely used for the implementation of digital systems, and many commercial architectures are available. Although the literature and data books contain detailed descriptions of these architectures, there is very little information on how the high-level architecture was chosen and no information on the circuit-level or physical design of the devices. In Part I of this paper, we described the high-level architectural design of a static random-access memory programmable FPGA. This paper will address the circuit-design issues through to the physical layout. We address area-speed tradeoffs in the design of the logic block circuits and in the connections between the logic and the routing structure. All commercial FPGA designs are done using full-custom hand layout to obtain absolute minimum die sizes. This is both labor and time intensive. We propose a design style with a minitile that contains a portion of all the components in the logic tile, resulting in less full-custom effort. The minitile is replicated in a 4/spl times/4 array to create a macro tile. The minitile is optimized for layout density and speed, and is customized in the array by adding appropriate vias. This technique also permits easy changing of the hard-wired connections in the logic block architecture and the segmentation length distribution in the routing architecture.

A circuit representation technique for automated circuit design

Abstract: We present a method of automatically generating circuit designs using evolutionary search and a set of circuit constructing primitives arranged in a linear sequence. This representation has the desirable property that virtually all sets of circuit-constructing primitives result in valid circuit graphs. While this representation excludes certain circuit topologies, it is capable of generating a rich set of them including many of the useful topologies seen in hand-designed circuits. Our system allows circuit size (number of devices), circuit topology, and device values to he evolved. Using a parallel genetic algorithm and circuit simulation software, we present experimental results as applied to three analog filter and two amplifier design tasks. In all tasks, our system is able to generate circuits that achieve the target specifications. Although the evolved circuits exist as software models, detailed examinations of each suggest that they are electrically well behaved and thus suitable for physical implementation. The modest computational requirements suggest that the ability to evolve complex analog circuit representations in software is becoming more approachable on a single engineering workstation.

EMC and the printed circuit board : design, theory, and layout made simple

Abstract: Samenvatting:Mark I. Montrose, the best-selling author of PRINTED CIRCUIT BOARD DESIGNTECHNIQUES FOR EMC COMPLIANCE, now brings you his newest book, EMC ANDTHE PRINTED CIRCUIT BOARD. This accessible, new reference work shows howand why RF energy is created within a printed circuit board and themanner in which propagation occurs. With lucid explanations, this bookenables engineers to grasp both the fundamentals of EMC theory and signalintegrity and the mitigation process needed to prevent an EMC event.Author Montrose also shows the relationship between time and frequencydomains to help you meet mandatory compliance requirements placed onprinted circuit boards. Using real-world examples the book features:*Clear discussions, without complex mathematical analysis, of fluxminimization concepts *Extensive analysis of capacitor usage for variousapplications *Detailed examination of components characteristics withvarious grounding methodologies, including implementation techniques *Anin-depth study of transmission line theory *A careful look at signalintegrity, crosstalk, and termination

A methodology for correct-by-construction latency insensitive design

Abstract: In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the design functionally insensitive to the latency of long wires. Given a synchronous specification of a design, we generate a functionaly equivalent synchronous implementation that can tolerate arbitrary communication latency between latches. By using latches we can break a long wire in short segments which can be traversed while meeting a single clock cycle constraint. The overall goal is to obtain a design that is robust with respect to delays of long wires, in a shorter time by reducing the multiple iterations between logical and physical design, and with performance that is optimized with respect to the speed of the single components of the design. In this paper we describe the details of the proposed methodology as well as report on the latency insensitive design of PDLX, an out-of-order microprocessor with speculative-execution.

A comprehensive delay macro modeling for submicrometer CMOS logics

Abstract: The increasing need for high-performance, cost-effective, application-specific integrated circuits, associated to the reduction of design cycle time, compels designers to manage and optimize the circuit speed performance at each step of the design flow. Circuits are usually designed at gate level; the gate selection or sizing and their placement are driven by estimated delay, hence the need for accurate estimations at the logical level. In the submicrometer range, the gap between gate-level logical estimations and transistor-level electrical simulations dramatically increases. We propose here a comprehensive analytical modeling of the speed performance of CMOS gates with an accuracy comparable to electrical simulators. A design-oriented expression of delay is first developed for CMOS inverters, considering input slope, input-to-output capacitance coupling, and short-circuit current effects. The extension to more complex gates is proposed using a serial array reduction technique taking account of the gate input dependency and the input-slope-induced nonlinearity. Validations are obtained over a large range of design, load, and input slope conditions by comparison with SPICE simulations (level 6 with 0.65-/spl mu/m foundry specified card model) used as a reference.

Globally-asynchronous locally-synchronous architectures to simplify the design of on-chip systems

Abstract: A novel methodology for realizing Globally-Asynchronous Locally-Synchronous (GALS) architectures is reported. We developed a library of predesigned modules that facilitate the assembly of independently clocked modules to on-chip systems. The components of this library establish high-performance data exchange channels which are instrumental in constructing flexible architectures. The validity of our concept is proven by applying it to an ASIC design with real-world complexity.

Evolving more efficient digital circuits by allowing circuit layout evolution and multi-objective fitness

Abstract: We use evolutionary search to design combinational logic circuits. The technique is based on evolving the functionality and connectivity of a rectangular array of logic cells whose dimension is defined by the circuit layout. The main idea of this approach is to improve quality of the circuits evolved by the genetic algorithm (GA) by reducing the number of active gates used. We accomplish this by combining two ideas: 1) using multi-objective fitness function; 2) evolving circuit layout. It will be shown that using these two approaches allows us to increase the quality of evolved circuits. The circuits are evolved in two phases. Initially the genome fitness is given by the percentage of output bits that are correct. Once 100% functional circuits have been evolved, the number of gates actually used in the circuit is taken into account in the fitness function. This allows us to evolve circuits with 100% functionality and minimise the number of active gates in circuit structure. The population is initialised with heterogeneous circuit layouts and the circuit layout is allowed to vary during the evolutionary process. Evolving the circuit layout together with the function is one of the distinctive features of proposed approach. The experimental results show that allowing the circuit layout to be flexible is useful when we want to evolve circuits with the smallest number of gates used. We find that it is better to use a fixed circuit layout when the objective is to achieve the highest number of 100% functional circuits. The two-fitness strategy is most effective when we allow a large number of generations.

Method and apparatus for providing multiple electronic design solutions

Abstract: An electronic computer aided design system provides for automated operation of a plurality of design tools to produce multiply design solutions to an initial circuit layout Through the user entry of relative weights for: power, timing and area, different solutions to an initial layout can be generated exhibiting the requested balance of improvements over the original layout A novel parts placement process is disclosed which prioritizes the reconfiguration of the initial design in a manner which assures that the multiple solutions will be generated which exhibit improved performance over the original layout in accordance with the priorities established by the user

CMOS IC Layout: Concepts, Methodologies, and Tools

Abstract: Introduction Background Layout Design Specific Layout Design Flows Advanced Techniques for specialized building block layout design Advanced techniques for Building Block Interconnect Layout Design Layout Design techniques to address Electrical characteristics Layout considerations due to process requirements Layout design techniques in an uncertain environment Layout CAD Tools

Mechanisms for making and inspecting reticles

Abstract: A reusable circuit design for use with electronic design automation EDA tools in designing integrated circuits is disclosed, as well as reticle inspection and fabrication methods that are based on such reusable circuit design. The reusable circuit design is stored on a computer readable medium and contains an electronic representation of a layout pattern for at least one layer of the circuit design on an integrated circuit. The layout pattern includes a flagged critical region which corresponds to a critical region on a reticle or integrated circuit that is susceptible to special inspection or fabrication procedures. In one aspect of the reusable circuit design, the special analysis is performed during one from a group consisting of reticle inspection, reticle production, integrated circuit fabrication, and fabricated integrated circuit inspection.

The design of an SRAM-based field-programmable gate array. I. Architecture

Abstract: Field-programmable gate arrays (FPGAs) are now widely used for the implementation of digital systems, and many commercial architectures are available. Although the literature and data books contain detailed descriptions of these architectures, there is very little information on how the high-level architecture was chosen, and no information on the circuit-level or physical design of the devices. This paper describes the high-level architectural design of a static-random-access memory programmable FPGA. A forthcoming Part II will address the circuit design issues through to the physical layout. The logic block and routing architecture of the FPGA was determined through experimentation with benchmark circuits and custom-built computer-aided design tools. The resulting logic block is an asymmetric tree of four-input lookup tables that are hard-wired together and a segmented routing architecture with a carefully chosen segment length distribution.

A novel VLSI layout fabric for deep sub-micron applications

Abstract: Proposes a new VLSI layout methodology which addresses the main problems faced in deep sub-micron (DSM) integrated circuit design. Our layout "fabric" scheme eliminates the conventional notion of power and ground routing on the integrated circuit die. Instead, power and ground are essentially "pre-routed" all over the die. By a clever arrangement of power/ground and signal pins, we almost completely eliminate the capacitive effects between signal wires. Additionally. We get a power and ground distribution network with a very low resistance at any point on the die. Another advantage of our scheme is that the arrangement of conductors ensures that on-chip inductances are uniformly negligible. Finally, characterization of the circuit delays, capacitances and resistances becomes extremely simple in our scheme, and needs to be done only once for a design. We show how the uniform parasitics of our fabric give rise to a reliable and predictable design. We have implemented our scheme using public domain layout software. Preliminary results show that it holds much promise as the layout methodology of choice in DSM integrated circuit design.

Analysis and Design of Integrated Circuit Antenna Modules

Abstract: From the Publisher: With communications technologies rapidly expanding, the traditional separation of electronic circuits and antenna systems design is no longer feasible. This book covers various design approaches applicable to integrated circuit-antenna modules with the goal of placing the antenna, transmitter, and receiver all on a single chip. It emphasizes analysis and design involving the integration of circuit functions with radiating elements and addresses trends in systems miniaturization.

Challenges in testing core-based system ICs

Abstract: Advances in semiconductor design and manufacturing technology enable the design of complete systems on one IC. To develop these system ICs in a timely manner, traditional IC design in which everything is designed from scratch, is replaced by a design style based on embedding large reusable modules, the so-called cores. Effectively, the design of a core-based IC is partitioned over the core provider(s) and the system-chip integrator. The development of tests should follow the same partitioning. We describe the differences between traditional and core-based test development, and present an overview of current industrial approaches. We list the future challenges regarding standardization, tool development, and academic and industrial research.

Defect and fault tolerance FPGAs by shifting the configuration data

Abstract: The homogeneous structure of field programmable gate arrays (FPGAs) suggests that the defect tolerance can be achieved by shifting the configuration data inside the FPGA. This paper proposes a new approach for tolerating the defects in FPGA's configurable logic blocks (CLBs). The defects affecting the FPGA's interconnection resources can also be tolerated with a high probability. This method is suited for the makers, since the yield of the chip is considerably improved, specially for large sizes. On the other hand, defect-free chips can be used as either maximum size, ordinary array chips or fault tolerant chips. In the fault tolerant chips, the users will be able to achieve directly the fault tolerance by only shifting the design data automatically, without changing the physical design of the running application, without loading other configurations data from the off-chip FPGA, and without the intervention of the company. For tolerating defective resources, the use of spare CLBs is required. In this paper, two possibilities for distributing the spare resources (king-shifting and horse-allocation) are introduced and compared.

Structured design of integrated MEMS

Abstract: MEMS design methodologies in wide use today do not support hierarchical representations suitable for verification-based iterative design. Adoption of a structured design methodology which borrows hierarchy from the electronics design paradigm enables rapid design verification of complex electronic and micromechanical trade-offs inherent in integrated MEMS. A hierarchical MEMS circuit representation is analogous to and compatible with transistor-level circuits for electronics. Design of a capacitive lateral accelerometer illustrates the structured design flow from a system description, to circuit representation, layout and fabrication. Tools for layout synthesis, layout extraction, and verification specifically tailored for MEMS are an integral part of the design flow. The accelerometer is fabricated in a low-cost CMOS micromachining process that is especially suited to rapid prototyping of integrated MEMS.

Method of estimating performance of integrated circuit designs

Abstract: A technique to verify, evaluate, and estimate the performance of an integrated circuit is embodied in a computer software program that is executable by a computer system. The technique accurately estimates of the performance (e.g., transient delays) of an integrated circuit, and has fast execution times. The technique is applicable to small circuits having relatively few transistors, and especially well suited for integrated circuits having millions of transistors and components. The technique handles the effects of deep-submicron integrated circuit technology.

Interactive circuit designing apparatus which displays a result of component placement and wire routing from a layout design unit

Abstract: A circuit designing apparatus of an interactive type which enables a simplified and highspeed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.

Rethinking deep-submicron circuit design

Abstract: Interconnect delay need not increase as CMOS process geometries shrink, and current IC design methods should suffice for modules of up to 50,000 gates. Beyond that, designers must focus on a new concept - global interconnect design. We consider the effects of both devices and interconnect, and our analysis shows that interconnect delay actually decreases for deep-submicron (DSM) processes in a modular design approach. The physical explanations of these DSM effects shed insight into this and other potential impacts on future high-performance ASIC designs.

Physics- and process-based bipolar transistor modeling for integrated circuit design

Abstract: Many applications require circuits to be operated close to the performance limits of current silicon (production) processes to meet the required circuit specifications for, e.g., high speed, low noise, and low power consumption. Therefore, the circuits must be carefully optimized by selecting the individual transistor configurations. As a consequence, model parameters for a large variety of configurations (100 or more) are often requested. Unfortunately, most present design tools and modeling methods do not support an efficient generation of the respective parameter sets for bipolar compact models. This paper describes an approach that is physics and process based; facilitates an extremely fast generation of consistent model parameter sets, even during the initial phase of process development; and reduces parameter extraction efforts significantly. This allows one to quickly explore various process options in advance and to align process development with circuit product requirements. The approach is supported by a computer-aided-design tool named TRADICA, which can be combined with circuit simulators allowing the emitter size and number of emitter, base, and collector contacts to be the only model parameters visible to designers. Related modeling and parameter extraction issues are also discussed because these areas are often unknown and tend to be underestimated by circuit designers and process developers but have a significant impact on the flexibility, capability, and accuracy of circuit design.

A review of substrate coupling issues and modeling strategies

Abstract: This tutorial paper reviews the technologies behind substrate coupling and modeling. The key focuses throughout are the importance of suitable substrate models and a sufficient understanding of the substrate coupling in the circuit being designed. Discussions include Radio Frequency (RF) and Mixed-Signal (MS) designs, but also touch upon System-on-Chip (SoC). An example RF circuit is simulated with a substrate model and the effect of substrate process variations on the circuit's performance is discussed.

Challenges in clockgating for a low power ASIC methodology

Abstract: Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activity in the logic modules as well as by eliminating power dissipation in the clock distribution network. There is an inherent pitfall though in implementing gating groups for hierarchical gated clock distribution because the groups are typically developed at the logic level with no information of the physical layout of the clocktree. Depending on the distribution of underlying sinks, maintaining gating groups can cause a wiring overhead that is potentially greater than the savings due to reduced switching. We look at modifications of zero-skew tree algorithms to consider both the physical and logical aspects of hierarchical gating. The algorithms are applied to data taken from a low power ASIC design. The best gated clocktree is created using both physical and logical information.

Noise-tolerant dynamic circuit design

Abstract: Noise in deep submicron technology combined with the move towards dynamic circuit techniques for higher performance have raised concerns about reliability and energy efficiency of VLSI systems in the deep submicron era. To address this problem, a new noise-tolerant dynamic circuit technique is presented. In addition, the average noise threshold energy (ANTE) and the energy normalized ANTE metrics are proposed for quantifying the noise immunity and energy efficiency, respectively, of circuit techniques. Simulation results in 0.35 micron CMOS for NAND gate designs indicate that the proposed technique improves the ANTE and energy normalized ANTE by 2.54X and 2.25X over the conventional domino circuit. The improvement in energy normalized ANTE is 1.22X higher than the existing noise-tolerance techniques. A full adder design based on the proposed technique improves the ANTE and energy normalized ANTE by 3.7X and 1.95X over the conventional dynamic circuit. In comparison, the static circuit improves ANTE by 2.2X but degrades the energy normalized ANTE by 11%. In addition, the proposed technique has a smaller area overhead (69%) as compared to the static circuit whose area overhead is 98%.

Layout synopsizing process for efficient layout parasitic extraction and circuit simulation in post-layout verification

Abstract: A process is provided for generating a synoptic layout database for efficient layout parasitic extraction and circuit simulation in post-layout verification of an integrated circuit (IC) design for a system having a plurality of repetitive subcircuits. The process includes the steps of: receiving an input layout database including a plurality of geometric objects including cells representing the IC design, each of the cells including a plurality of polygons; identifying a plurality of repetitive cells of the input layout database, the repetitive cells being associated with the repetitive sub-circuits; recognizing at least one pattern of the repetitive cells; defining at least one cut region of the input layout database, the cut region being defined by physical layout coordinates, the cut region intersecting a corresponding pattern of the repetitive cells; and generating a synoptic layout database.

Automated optimal synthesis of microaccelerometers

Abstract: The rapid layout synthesis of a lateral accelerometer from high-level functional specifications and design constraints is demonstrated. Functional parameters such as sensitivity, minimum and maximum detectable acceleration are satisfied while simultaneously optimizing a design objective, such as device area. The optimal synthesis tool allows exploration of micromechanical device and system design issues and objectives. Layout synthesis couples optimization-based design to determine the values of layout geometry followed with layout generation to translate the desired device performance into a device layout. This rapid layout generation allows for an 'on-the-fly' cell library generation methodology for use in design of integrated microsystems. In particular, the optimization-based approach to design allows the designer to determine the crucial design tradeoffs in meeting the system-level performances, as shown by synthesis results presented.

Method and apparatus for edge-endpoint-based VLSI design rule checking

Abstract: The method and apparatus for performing design rule checking on Manhattan structures in VLSI circuit layouts. The method and apparatus provides an edge-endpoint-based technique for checking the geometry and spacing of the VLSI circuit layout. The edge-endpoint-based technique uses a scanline algorithm that detects errors between adjacent structures that do not simultaneously intersect the scanline. The method also provides efficient error compilation. The apparatus allows for the design rules to be changed as the VLSI circuit layout evolves. The apparatus can process the VLSI circuit layout with a single processor, and the apparatus provides for multiple processors to process slices of the VLSI circuit layout, thereby enhancing the speed of the design rule checking over traditional software-only techniques.

Hierarchical design and test of integrated microsystems

Abstract: This article presents emerging results of an integrated mixed-domain design methodology similar to the mixed-signal design methodologies in the VLSI community. This methodology is based on a hierarchical mixed-domain design representation and includes a Spice-like nodal simulation environment, an "on-the-fly" component layout-synthesis module, a layout extractor for design verification, and a fault model generator for test methodology development.

Pre-synthesis test point insertion

Abstract: A method of and system for inserting test points within an integrated circuit design. According to the present invention, test points are inserted early in the electronic design process and prior to logic synthesis such that the problem of design constraint violation can be avoided. One embodiment of the present invention includes the computer implemented steps of receiving an unmapped netlist of an integrated circuit design, and receiving from an external source, data that indicates the location and the desired functionality of the test point to be inserted. Thereafter, the present invention inserts a generic test point circuit at the indicated location and generates a modified unmapped netlist. Subsequently, the present invention performs a logic synthesis process on the modified unmapped netlist where the generic test point circuit is degenerated into an actual test point circuit for performing the desired functionality. The actual test point circuit may also be merged with other circuitries of the integrated circuit to produce a more efficient design.

New and exact filling algorithms for layout density control

Abstract: To reduce manufacturing variation due to chemical-mechanical polishing and to improve yield, layout must be made uniform with respect to density criteria. This is achieved by layout postprocessing to add fill geometries, either at the foundry or, for better convergence of performance verification flows, during layout synthesis. This paper proposes a new min-variation objective for the synthesis of fill geometries. Within the so-called fixed dissection regime (where density bounds are imposed on a predetermined set of windows in the layout), we exactly solve the min-variation objective using a linear programming formulation. We also state criteria for fill pattern synthesis, and discuss additional criteria that apply when fill, must be grounded for predictability of circuit performance. We believe that density control for CMP will become an important research topic in the VLSI design-manufacturing interface over the next several years.

Subwavelength optical lithography: challenges and impact on physical design

Abstract: We review the implications of subwavelength optical lithography for new tools and ows in the interface between layout design and manufacturability. After discussing the necessity of corrections for optical process e ects (i.e., use of optical proximity correction (OPC) and phase-shifting masks (PSM)), we focus on the implications of OPC and PSM for layout and veri cation methodologies. Our discussion addresses the necessary changes in the design-tomanufacturing ow, including infrastructure development in the mask and process communities as well as opportunities for research and development in physical layout and veri cation.