scispace - formally typeset
Search or ask a question

Showing papers on "Physical design published in 2001"


Book
01 Jan 2001
TL;DR: The design of next generation microprocessors in deep submicron CMOS technologies is covered, and a broad range of circuit styles and VLSI design techniques are covered, an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers.
Abstract: From the Publisher: This book covers the design of next generation microprocessors in deep submicron CMOS technologies. The chapters in Design of High Performance Microprocessor Circuits were written by some of the world’s leading technologists, designers, and researchers. All levels of system abstraction are covered, but the emphasis rests squarely on circuit design. Examples are drawn from processors designed at AMD, Digital/Compaq, IBM, Intel, MIPS, Mitsubishi, and Motorola. Each topic of this invaluable reference stands alone so the chapters can be read in any order. The following topics are covered in depth: Architectural constraints of CMOS VLSI design Technology scaling, low-power devices, SOI, and process variations Contemporary design styles including a survey of logic families, robust dynamic circuits, asynchronous logic, self-timed pipelines, and fast arithmetic units Latches, clocks and clock distribution, phase-locked and delay-locked loops Register file, cache memory, and embedded DRAM design High-speed signaling techniques and I/O design ESD, electromigration, and hot-carrier reliability CAD tools, including timing verification and the analysis of power distribution schemes Test and testability Design of High-Performance Microprocessor Circuits assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit styles and VLSI design techniques. Packed with practical know-how, it is an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers. It is also an essential text for VLSI design courses.

751 citations


Journal ArticleDOI
TL;DR: The theory of latency-insensitive design is presented as the foundation of a new correct-by-construction methodology to design complex systems by assembling intellectual property components to design large digital integrated circuits by using deep submicrometer technologies.
Abstract: The theory of latency-insensitive design is presented as the foundation of a new correct-by-construction methodology to design complex systems by assembling intellectual property components. Latency-insensitive designs are synchronous distributed systems and are realized by composing functional modules that exchange data on communication channels according to an appropriate protocol. The protocol works on the assumption that the modules are stallable, a weak condition to ask them to obey. The goal of the protocol is to guarantee that latency-insensitive designs composed of functionally correct modules behave correctly independently of the channel latencies. This allows us to increase the robustness of a design implementation because any delay variations of a channel can be "recovered" by changing the channel latency while the overall system functionality remains unaffected. As a consequence, an important application of the proposed theory is represented by the latency-insensitive methodology to design large digital integrated circuits by using deep submicrometer technologies.

435 citations


Patent
04 Jan 2001
TL;DR: In this article, the authors present a method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system and, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip.
Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

343 citations


Patent
06 Mar 2001
TL;DR: In this paper, a method for design optimization using logical and physical information is provided, which includes a behavioral description of an integrated circuit or a portion of an Integrated Circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements.
Abstract: A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.

314 citations


Patent
02 Mar 2001
TL;DR: The STANDARD BLOCK architecture as discussed by the authors provides a new level of abstraction with a granularity and regularity that is most appropriate for the physical implementation of complex, large scale deep-submicron IC designs.
Abstract: A STANDARD BLOCK architecture for integrated circuit (IC) design. The STANDARD BLOCK architecture provides a new level of abstraction with a granularity and regularity that is most appropriate for the physical implementation of complex, large scale deep-submicron IC designs. To this end, the STANDARD BLOCK architecture combines the advantages of standard-cell-based and functional-block-based architectures. The STANDARD BLOCK architecture includes a STANDARD BLOCK form that is physically constrained having one fixed or quantized dimension and one variable dimension that ranges between predefined limits. The STANDARD BLOCK granularity is larger than the standard cell granularity such that each STANDARD BLOCK includes a plurality of standard cells. In the STANDARD BLOCK architecture, each STANDARD BLOCK has flexible physical design properties. In this design style, the STANDARD BLOCKs are provided as general abstractions akin to black boxes whose selected global design aspects are visible to a top-level design tool and whose selected local design aspects are invisible to the top-level design tool. The global design aspects of each STANDARD BLOCK include its fundamental architectural and structural characteristics, including its physically constrained form, and its fundamental power, timing, clock and signal integrity properties. With the STANDARD BLOCK architecture, quantization of the STANDARD BLOCKs' form dimensions relative to IC dimensions can be substantially constant and scalable with increased IC complexity. Thus, STANDARD BLOCK architecture can be applied to any IC designs as well as any intellectual property (IP) designs.

293 citations


Journal ArticleDOI
TL;DR: Watermarking-based IP protection as mentioned in this paper addresses IP protection by tracing unauthorized reuse and making untraceable unauthorized reuse as difficult as recreating given pieces of IP from scratch, where a watermark is a mechanism for identification that is nearly invisible to human and machine inspection; difficult to remove; and permanently embedded as an integral part of the design.
Abstract: Digital system designs are the product of valuable effort and know-how. Their embodiments, from software and hardware description language program down to device-level netlist and mask data, represent carefully guarded intellectual property (IP). Hence, design methodologies based on IP reuse require new mechanisms to protect the rights of IP producers and owners. This paper establishes principles of watermarking-based IP protection, where a watermark is a mechanism for identification that is: (1) nearly invisible to human and machine inspection; (2) difficult to remove; and (3) permanently embedded as an integral part of the design. Watermarking addresses IP protection by tracing unauthorized reuse and making untraceable unauthorized reuse as difficult as recreating given pieces of IP from scratch. We survey related work in cryptography and design methodology, then develop desiderata, metrics, and concrete protocols for constraint-based watermarking at various stages of the very large scale integration (VLSI) design process. In particular, we propose a new preprocessing approach that embeds watermarks as constraints into the input of a black-box design tool and a new postprocessing approach that embeds watermarks as constraints into the output of a black-box design tool. To demonstrate that our protocols can be transparently integrated into existing design flows, we use a testbed of commercial tools for VLSI physical design and embed watermarks into real-world industrial designs. We show that the implementation overhead is low-both in terms of central processing unit time and such standard physical design metrics as wirelength, layout area, number of vias, and routing congestion. We empirically show that the placement and routing applications considered in our methods achieve strong proofs of authorship and are resistant to tampering and do not adversely influence timing.

220 citations


Proceedings ArticleDOI
Warren D. Grobman1, Matthew A. Thompson1, Ruoping Wang1, C. Yuan1, Ruiqi Tian1, E. Demircan1 
22 Jun 2001
TL;DR: The need to do tiling that is model-driven and uses optimization techniques to achieve planarity for better manufacturing tolerance in the subwavelength dimensions era is emphasized.
Abstract: In this paper, we review phase shift lithography, rule vs. model based methods for OPC and model-based tiling, and discuss their implications for layout and verificat ion. We will discuss novel approaches, using polarizing films on reticles, which change the game for phase-shift coloring, and could lead to a new direction in c:PSM constraints on physical design. We emphasize the need to do tiling that is model-driven and uses optimization techniques to achieve planarity for better manufacturing tolerance in the subwavelength dimensions era. Electromagnetic solver results will be presented which estimate the effect of tiling on circuit timing.

190 citations


Patent
26 Mar 2001
TL;DR: In this paper, the authors proposed a method for estimating the external conditions of a partial circuit when used in an integrated circuit so that the partial circuit is designed in accordance with external conditions.
Abstract: There is no conventional method for precisely estimating under what external conditions each partial circuit, such as a library cell, is utilized in an actual integrated circuit at the time of designing the partial circuit. Therefore, by estimating the external conditions of a partial circuit when used in an integrated circuit so that the partial circuit is designed in accordance with the external conditions, the partial circuit having optimal performance for the external conditions can be designed. The step of external condition estimation can be formed so as to include the technology conversion step which technologically converts the layout for external condition extraction, that is prepared in advance, based on the technology information of an integrated circuit, which is the design objective; the layout extraction step of extracting layout extraction information which is external information influencing the operation of the partial circuit from the layout for external condition extraction that has been technologically converted; and the external condition calculation step of calculating external conditions of the partial circuit from the layout extraction information. In addition, by simply replacing the designed partial circuit with a partial circuit of a circuit for evaluation, the evaluation of the designed partial circuit can be easily carried out.

164 citations


Journal ArticleDOI
TL;DR: A synthesis environment for analog integrated circuits is presented that is able to drastically increase design and layout productivity for analog blocks and shows the productiveness and efficiency of the environment for the synthesis and process tuning of frequently used analog cells.
Abstract: A synthesis environment for analog integrated circuits is presented that is able to drastically increase design and layout productivity for analog blocks. The system covers the complete design flow from specification over topology selection and optimal circuit sizing down to automatic layout generation and performance characterization. It follows a hierarchical refinement strategy for more complex cells and is process independent. The sizing is based on an improved equation-based optimization approach, where the circuit behavior is characterized by declarative models that are then converted in a sequential design plan. Supporting tools have been developed to reduce the total effort to set up a new circuit topology in the system's database. The performance-driven layout generation tool guarantees layouts that satisfy all performance constraints. Redesign support is included in the design flow management to perform backtracking in case of design problems. The experimental results illustrate the productiveness and efficiency of the environment for the synthesis and process tuning of frequently used analog cells.

149 citations


Proceedings ArticleDOI
05 Feb 2001
TL;DR: The fourth-generation POWER processor as discussed by the authors contains 170M transistors and includes 2 microprocessor cores, shared L2, directory for an off-chip L3, and all logic needed to interconnect multiple chips to form an SMP.
Abstract: The fourth-generation POWER processor chip contains 170M transistors and includes 2 microprocessor cores, shared L2, directory for an off-chip L3, and all logic needed to interconnect multiple chips to form an SMP. It is implemented in a 0.18 /spl mu/m SOI technology, with 7 layers of Cu interconnect, and functions in systems at 1.1 GHz, and dissipates 115 W at 1.5 V.

124 citations


Journal ArticleDOI
06 May 2001
TL;DR: A hierarchical automated design flow for low-energy direct-mapped signal processing integrated circuits is presented and an example of architectural comparison of energy efficiency is presented.
Abstract: A hierarchical automated design flow for low-energy direct-mapped signal processing integrated circuits is presented. A modular framework based on a combined dataflow graph and floorplan description drives automatic layout generation with commercial CAD tools. Automatic characterization of layout improves system-level estimates. Simplified physical design methodologies for low supply voltages are discussed. The flow is demonstrated on a 300-k transistor test-chip, a time-division multiple-access baseband receiver, and a soft-output Viterbi decoder. An example of architectural comparison of energy efficiency is presented.

Patent
02 Mar 2001
TL;DR: An integrated circuit (IC) architecture with STANDARD BLOCKs is presented in this article, which is a general abstractions akin to black boxes, the global design aspects of which are transparent to a top-level design tool and the local design aspects, which are invisible to the top level design tool.
Abstract: An integrated circuit (IC) architecture with STANDARD BLOCKs. The IC architecture includes STANDARD BLOCKs and a layout that includes the STANDARD BLOCKs. Each of the STANDARD BLOCKs has a form that is physically constrained such that its dimensions feature one fixed or quantized dimension, and one variable dimension that ranges between predefined limits; a granularity larger than a standard cell granularity such that each STANDARD BLOCK includes a plurality of standard cells; and flexible physical design properties. Some or all of the STANDARD BLOCKS are arranged in one or more STANDARD BLOCK ARRAY configurations. The layout of the IC further includes power grid and clock grid structures providing, respectively, power and ground and clock distribution. The layout of the IC further includes standard cell sites for th etop-level cells, and pin sites associated with some of the interconnects . In this design style, the STANDARD BLOCKs are provided as general abstractions akin to black boxes the global design aspects of which are transparent to a top-level design tool and the local design aspects of which are invisible to the top-level design tool. The global design aspects of each STANDARD BLOCK include its fundamental architectural characteristics, including its physically constrained form, and its fundamental power, timing, clock and signal integrity properties. The IC architecture with the STANDARD BLOCKs can be applied to any large scale IC designs as well as any soft or hard intellectual property (IP) designs.

Proceedings ArticleDOI
01 Apr 2001
TL;DR: It is shown that chip level thermal effects can have a significant impact on large-scale circuit optimization techniques, including the clock-skew minimization scheme, and can influence other physical design problem formulations.
Abstract: This paper provides an overview of various thermal issues in high-performance VLSI with especial attention to their implications for performance and reliability. More specifically, it examines the impact of thermal effects on both interconnect design and electromigration reliability and discusses their impact on the allowable current density limits. Furthermore, it also discusses how thermal and reliability constrained current density limits may conflict with those obtained through purely performance based criterion. Additionally, it is shown that chip level thermal effects can have a significant impact on large-scale circuit optimization techniques, including the clock-skew minimization scheme, and can influence other physical design problem formulations. Finally, high-current interconnect design rules for ESD and I/O circuits are also examined.

Proceedings ArticleDOI
Sani R. Nassif1
30 Jan 2001
TL;DR: In this article, the authors examine the sources and trends of process variability, the new challenges associated with the increase in within-die variability analysis, and propose a modeling and simulation methodology to deal with this variability.
Abstract: Process-induced variations are an important consideration in the design of integrated circuits. Until recently, it was sufficient to model die-to-die shifts in device performance, leading to the well known worst-case modeling and design methodology. However, current and near-future integrated circuits are large enough that device and interconnect parameter variations within the chip are as important as those same variations from chip to chip. This presents a new set of challenges for process modeling and characterization and for the associated design tools and methodologies. This paper examines the sources and trends of process variability, the new challenges associated with the increase in within-die variability analysis, and proposes a modeling and simulation methodology to deal with this variability.

Patent
28 Mar 2001
TL;DR: A Web-based integrated circuit design system, method and computer program product tool allows design engineers to utilize a well-understood graphical interface (i.e., a web browser) to access a wealth of data and services as mentioned in this paper.
Abstract: A Web-based integrated circuit design system, method and computer program product tool allows design engineers to utilize a well-understood graphical interface (i.e., a Web browser) to access a wealth of data and services. The services and data include competing standard architectures and reference designs. The integrated circuit design tool allows users (e.g., design engineers) to efficiently design cores and systems-on-a-chip (SOCs). The integrated circuit design tool is a “virtual lab” which allows and aides design engineers at every stage of IC product design—architecture choice, implementation options, software development, and hardware design.

Patent
27 Sep 2001
TL;DR: In this paper, the authors present a system for the interactive design and analysis of analog and mixed-signal circuits, which can be used to analyze multiple circuit designs at the same time.
Abstract: A system is herein disclosed which allows for the interactive design and analysis of analog and mixed-signal circuits. Circuits may additionally be characterized and verified without leaving the environment provided by the system. The system may be used to analyze multiple circuit designs at the same time. In this manner a designer can create a test that sweeps over several circuit designs. Embodiments of the invention may be integrated with other circuit design tools and development systems.

Patent
15 Aug 2001
TL;DR: In this paper, a method and apparatus for PCB layout of a circuit simulated over a network is provided, where the components are placed on a PC board having landing areas designed to accommodate all the anticipated component sizes for the type of circuit being designed.
Abstract: A method and apparatus for PCB layout of a circuit simulated over a network is provided. Techniques are provided for designing a circuit that satisfies user-specified functional requirements received over a network. Based on the specified requirements, components and a topology for constructing the circuit are automatically determined. The components determined during this operation have operational values such that, when the components are arranged according to the topology to form the circuit, the circuit satisfies the user-specified functional requirements. The components are placed on a PC board having landing areas designed to accommodate all of the anticipated component sizes for the type of circuit being designed. The PC board may be cropped to the desired size. The PCB may be cropped automatically or manually by the user. The component and topology information may be used to generate a schematic diagram that is delivered in a web page to the user over the network. The user may thermally and electrically simulate the designed circuit. Many characteristics of the PC board may be adjusted to produce an accurate circuit.

Journal ArticleDOI
TL;DR: An overview of circuit, technology, and physical design methodology issues in embedded DRAM development and application is presented.
Abstract: Embedded DRAM provides advantages from a system point of view, along with many technical challenges. This article presents an overview of circuit, technology, and physical design methodology issues in embedded DRAM development and application.

Proceedings ArticleDOI
13 Mar 2001
TL;DR: A novel approach for the design of application specific multiprocessor systems-on chip based on a generic architecture model which is used as a template throughout the design process that allows one accelerate the design cycle.
Abstract: In this paper, we present a novel approach for the design of application specific multiprocessor systems-on chip. Our approach is based on a generic architecture model which is used as a template throughout the design process. The key characteristics of this model are its great modularity, flexibility and scalability which make it reusable for a large class of applications. In addition, it allows one accelerate the design cycle. This paper focuses on the definition of the architecture model and the systematic design flow that can be automated. The feasibility and effectiveness of this approach are illustrated by two significant demonstration examples.

Proceedings ArticleDOI
04 Nov 2001
TL;DR: Experimental results prove that a new algorithm based on efficient nonlinear programming techniques has achieved the objectives of minimizing the area of power/ground networks with higher speeds.
Abstract: This paper deals with area minimization of power distribution networks for VLSIs. A new algorithm based on efficient nonlinear programming techniques is presented to solve this problem. Experimental results prove that this algorithm has achieved the objectives of minimizing the area of power/ground networks with higher speeds.

Proceedings ArticleDOI
30 Jan 2001
TL;DR: The first methods for hierarchical layout density control for process uniformity are given, which trades off naturally between runtime, solution quality, and output data volume.
Abstract: To improve manufacturability and performance predictability, we seek to make a layout uniform with respect to prescribed density criteria, by inserting "fill" geometries into the layout. Previous approaches for flat layout density control are not scalable due to the necessity of solving very large linear programs, the large data volume of the solution, and the impact of hierarchy-breaking on verification. In this paper, we give the first methods for hierarchical layout density control for process uniformity. Our approach trades off naturally between runtime, solution quality, and output data volume. We also allow generation of compressed GDSII of fill geometries. Our experiments show that this hybrid hierarchical filling approach saves data volume and is scalable, while yielding solution quality that is competitive with existing Monte-Carlo and linear programming based approaches.

Proceedings ArticleDOI
01 Jan 2001
TL;DR: A method for embedding a watermark by modifying the number of vias or bends used to route the nets in a design is proposed, applicable to digital, analog and mixed-signal design, and has the ability to accommodate the noise tolerance and design intricacies of each.
Abstract: Intellectual property protection (IPP) has become a major concern in today's CAD and ASIC/SOC industries. This paper presents a watermarking technique for IPP at the physical design level. We propose a method for embedding a watermark by modifying the number of vias or bends used to route the nets in a design. This technique is applicable to digital, analog and mixed-signal design, and has the ability to accommodate the noise tolerance and design intricacies of each.

Proceedings ArticleDOI
Gregory A. Northrop1, Pong-Fei Lu1
22 Jun 2001
TL;DR: This methodology combines flexible custom circuit design with automated tuning and physical design tools to provide new opportunities to optimized design throughout the development cycle.
Abstract: In this paper we present techniques shown to significantly enhance the custom circuit design process typical of high-performance microprocessors. This methodology combines flexible custom circuit design with automated tuning and physical design tools to provide new opportunities to optimized design throughout the development cycle.

Proceedings ArticleDOI
Thomas Kutzschebauch1, Leon Stok1
04 Nov 2001
TL;DR: Novel algorithms that effectively combine physical layout and early logic synthesis are presented to improve overall design quality and partitioning and clustering algorithms are employed to achieve faster turn around times.
Abstract: In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitioning and clustering algorithms to achieve faster turn around times. With the increasing complexity of designs, the traditional separation of logic and physical design leads to sub-optimal results as the cost functions employed during logic synthesis do not accurately represent physical design information. While this problem has been addressed extensively, the existing solutions apply only simple synthesis transforms during physical layout and are generally unable to reverse decisions made during logic minimization and technology mapping, that have a major negative impact on circuit structure. In our novel approach, we propose congestion aware algorithms for layout driven decomposition and technology mapping, two of the steps that affect congestion the most during logic synthesis, to effectively decrease wire length and improve congestion. In addition, to improve design turn-around-time and handle large designs, we present an approach in which synthesis partitioning and placement clustering co-exist, reflecting the different characteristics of logical and physical domain.

Patent
12 Jan 2001
TL;DR: In this article, a test system includes a test data generator to provide test data (e.g., a test pattern) to a subject circuit, which is functionally to verify the subject circuit.
Abstract: A test system includes a test data generator to provide test data (e.g., a test pattern) to a subject circuit (e.g., a digital television video circuit). The test data is functionally to verify the subject circuit. The functional verification of the subject circuit is performed utilizing an output of the subject circuit generated responsive to the test data in accordance with an operational functionality of the subject circuit. The test data generator is also coupled to provide the test data to a built-in self-test (BIST) circuit so as to enable the built-in self-test circuit to receive the test data.

Patent
18 Jan 2001
TL;DR: In this paper, the system and methods for designing integrated circuits and for creating and using androgynous interfaces between electronic components of integrated circuits are disclosed, and one preferred method of designing an integrated circuit includes several steps.
Abstract: Systems and methods for designing integrated circuits and for creating and using androgynous interfaces between electronic components of integrated circuits are disclosed. One preferred method of designing an integrated circuit includes several steps. In one step, a foundation block for the integrated circuit is specified, including specifying the locations of multiple androgynous interfaces in the integrated circuit. In another step, one or more component blocks to comprise the integrated circuit are identified for use. In another step, the component blocks to form a layout of the integrated circuit are positioned in a manner that minimizes connection distances between functional blocks and between functional blocks and the androgynous interfaces. In another step, the androgynous interfaces are set to perform as targets (slaves) or initiators (masters) based on the layout.

Proceedings ArticleDOI
04 Nov 2001
TL;DR: It is shown that careful matching of design complexity and architecture resources of hierarchical FPGAs can have a positive impact on the overall device area, and a circuit placement algorithm based on Rent's parameter is proposed.
Abstract: In this paper, we utilize Rent's rule as an empirical measure for efficient clustering and placement of circuits on hierarchical FPGAs. We show that careful matching of design complexity and architecture resources of hierarchical FPGAs can have a positive impact on the overall device area. We propose a circuit placement algorithm based on Rent's parameter and show that our clustering and placement techniques can improve the overall device routing area by as much as 21% for the same array size, when compared to a state-of-art FPGA placement and routing tool.

Proceedings ArticleDOI
06 May 2001
TL;DR: The proposed methodology uses the analytical equations that describe the circuit's behavior as a function of the design parameters such as the transistor dimensions and/or the passive component values in order to fit the circuit performance into the desired specifications.
Abstract: This paper presents an equation-based design methodology for optimization of analog building blocks using genetic algorithms The proposed methodology uses the analytical equations that describe the circuit's behavior as a function of the design parameters such as the transistor dimensions and/or the passive component values These parameters are then subject to an optimization process, using genetic algorithms, in order to fit the circuit performance into the desired specifications This design methodology is suited for fast redesigns of analog blocks into new technologies

Patent
Timothe Litt1
28 Dec 2001
TL;DR: In this paper, a system is disclosed in which an on-chip logic analyzer (OCLA) is included in an integrated circuit, such as a microprocessor During debug modes, one or more sets of an onchip cache memory are disabled from use by other circuitry in the integrated circuit and reserved exclusively for use by OCLA Data stored in the reserved cache set can then be read out by the OCLA, and placed in a register that can be accessed by other logic internal or external to the integrated circuits
Abstract: A system is disclosed in which an on-chip logic analyzer (OCLA) is included in an integrated circuit, such as a microprocessor During debug modes, one or more sets of an on-chip cache memory are disabled from use by other circuitry in the integrated circuit, and reserved exclusively for use by the OCLA Data stored in the reserved cache set can then be read out by the OCLA, and placed in a register that can be accessed by other logic internal or external to the integrated circuit If the integrated circuit is operating under normal mode, the cache memory set can be used in conventional fashion by other circuitry with in the integrated circuit to enhance performance

Proceedings ArticleDOI
22 Jun 2001
TL;DR: The performance-driven two-level clustering solution can improve the circuit performance produced by the Quartus Design System from Altera by an average of 15% for APEX devices measured in terms of delay after final layout.
Abstract: In this paper, we study the problem of performance-driven multi-level circuit clustering with application to hierarchical FPGA designs. We first show that the performance-driven multi-level clustering problem is NP-hard (in contrast to the fact that single-level performance-driven clustering can be solved in polynomial time optimally). Then, we present an efficient heuristic for two-level clustering for delay minimization. It can also provide area-delay trade-off by controlling the amount of node duplication. The algorithm is applied to Altera's latest APEX FPGA architecture which has a two-level hierarchy. Experimental results with combinational circuits show that with our performance-driven two-level clustering solution we can improve the circuit performance produced by the Quartus Design System from Altera by an average of 15% for APEX devices measured in terms of delay after final layout. To our knowledge this is the first in-depth study for the performance-driven multi-level circuit clustering problem.