Showing papers on "Physical design published in 2002"

Design of integrated circuits for optical communications

Abstract: Design of Integrated Circuits for Optical Communications deals with the design of high-speed integrated circuits for optical communication systems. Written for both students and practicing engineers, the book systematically takes the reader from basic concepts to advanced topics, establishing both rigor and intuition. The text emphasizes analysis and design in modern VLSI technologies, particularly CMOS, and presents numerous broadband circuit techniques. Leading researcher Behzad Razavi is also the author of Design of Analog CMOS Integrated Circuits. Table of contents 1 Introduction to Optical Communications 2 Basic Concepts 3 Optical Devices 4 Transimpedance Amplifiers 5 Limiting Amplifiers and Output Buffers 6 Oscillator Fundamentals 7 LC Oscillators 8 Phase-Locked Loops 9 Clock and Data Recovery 10 Multiplexers and Laser Drivers

Characterization and verification for integrated circuit designs

Abstract: Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process includes lithography or etch. Predicted characteristics are verified to conform to the design, the characteristics including feature dimensions or electrical characteristics. A process is selected for use in fabricating the integrated circuit based on the relative predicted variations. Chip-level features of a design of an integrated circuit are verified for manufacture within focus limitations of a lithographic tool. Whether a design of a level of an integrated circuit can be lithographically imaged in accordance with the design is predicted, and if it cannot be, the design or processing parameters are adjusted so that it can be.

CMOS Mixed-Signal Circuit Design

Abstract: The power of mixed-signal circuit designs, and perhaps the reason they are replacing analog-only designs in the implementation of analog interfaces, comes from the marriage of analog circuits with digital signal processing This book builds on the fundamental material in the author's previous book, CMOS: Circuit Design, Layout, and Simulation, to provide a solid textbook and reference for mixed-signal circuit design The coverage is both practical and in-depth, integrating experimental, theoretical, and simulation examples to drive home the why and the how of doing mixed-signal circuit design Some of the highlights of this book include: (1) A practical/theoretical approach to mixed-signal circuit design with an emphasis on oversampling techniques; (2) An accessible and useful alternative to hard-to-digest technical papers without losing technical depth; (3) Coverage of delta-sigma data converters, custom analog and digital filter design, design with submicron CMOS processes, and practical at-the-bench deadbug prototyping techniques; (4) Hundreds of worked examples and questions covering all areas of mixed-signal circuit design

Block based design methodology with programmable components

Abstract: A method for designing a circuit block includes the steps of selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, at least one of said circuit blocks being programmable; collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method; accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk; upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks (FEA); and, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, in compliance with the criteria and modified constraints without changing the selected circuit block and the processing method.

Method and apparatus for facilitating process-compliant layout optimization

Abstract: One embodiment of the invention provides a system that simulates effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size. During operation, the system receives a representation of a target layout for the integrated circuit, wherein the representation defines a plurality of shapes that comprise the target layout. Next, the system simulates effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout. The system then identifies problem areas in the simulated printed image that do not meet a specification. Next, the system moves corresponding shapes in the target layout to produce a new target layout for the integrated circuit, so that a simulated printed image of the new target layout meets the specification.

Mask product made by selection of evaluation point locations based on proximity effects model amplitudes for correcting proximity effects in a fabricat layout

Abstract: Techniques provided for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Included are techniques that correct for proximity effects associated with an edge in a layout corresponding to the design layer.

Method of designing integrated circuit and apparatus for designing integrated circuit

Abstract: An integrated circuit design method and an integrated circuit design apparatus, for increasing an efficiency of parallel processing of LSI design layout data while retaining a hierarchical structure by use of a computer capable of processing the data in parallel, take a first construction of making an internal cell composed of divided cells obtained by dividing a design cell specified by design cell data among pieces of integrated circuit design layout data on the basis of a cell division judging criterion, and of non-divided design cells other than the divided cells, then creating a plurality of unit groups of which data quantities are substantially equal to each other by combining the internal cells, and executing hierarchical parallel processing of the data contained in the internal cell per unit group, and take a second construction of restoring a non-overlapped array data region left by excluding a data region having overlapped data from an array data region containing array data among pieces of integrated circuit design layout data, with a combination of a plurality of or a single piece of array cell or unit cell.

Coping with latency in SOC design

Abstract: Latency-insensitive design is the foundation of a correct-by-construction methodology for SOC design. This approach can handle latency's increasing impact on deep-submicron technologies and facilitate the reuse of intellectual-property cores for building complex systems on chips, reducing the number of costly iterations in the design process.

Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system

Abstract: A method for modeling integrated circuit designs in a hierarchical design automation system which utilizes a block abstraction including therein set of all database objects (cells, nets, wires, vias, and blockages) that are necessary to achieve accurate placement, routing, extraction, simulation, and verification of the block's ancestors in the hierarchy.

The circuit and physical design of the POWER4 microprocessor

Abstract: The IBM POWER4 processor is a 174-milliontransistor chip that runs at a clock frequency of greater than 1.3 GHz. It contains two microprocessor cores, high-speed buses, and an on-chip memory subsystem. The complexity and size of POWER4, together with its high operating frequency, presented a number of significant challenges for its multisite design team. This paper describes the circuit and physical design of POWER4 and gives results that were achieved. Emphasis is placed on aspects of the design methodology, clock distribution, circuits, power, integration, and timing that enabled the design team to meet the project goals and to complete the design on schedule.

Electronic design for integrated circuits based on process related variations

Abstract: An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model. An RC extraction tool is used in conjunction with the generating and adjusting of the electronic design. The process includes a fabrication process that will impart topographical variation to the integrated circuit and a lithography or etch process. Placement attributes for elements of the integrated circuit are determined.

Method and apparatus for improving digital circuit design

Abstract: A method and apparatus provide a digital circuit including dynamic logic that minimizes circuit-path delay, residue logic, and circuit area. The method and apparatus use a library of circuit cells to produce a digital circuit design using a mapping algorithm. The mapping algorithm firstly determines an arrangement of circuit cells to minimize the delay in the circuit design, secondly determines an arrangement of circuit cells to minimize the residue logic for the circuit design, thirdly determines an arrangement of circuit cells to minimize the circuit area for the circuit design, and then repeats the process for each node in the circuit until the best circuit design is produced in accordance with pre-determined criteria.

A comprehensive layout methodology and layout-specific circuit analyses for three-dimensional integrated circuits

Abstract: In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit are fabricated on different wafers, and then, the wafers are bonded with a glue layer of Cu or polymer based adhesive. Using our layout methodology, designers can layout such 3D circuits with necessary information on inter-wafer via/contact and orientation of each wafer embedded in the layout. We have implemented the layout methodology in 3DMagic. Availability of 3DMagic has led to interesting research with a wide range of layout-specific circuit analyses, from performance comparison of 2D and 3D circuits to layout-specific reliability analyses in 3D circuits. Using 3DMagic, researchers have designed and simulated an 8-bit encryption processor mapped into 2D and 3D FPGA layouts. Moreover, the layout methodology is an essential element of our ongoing research for the framework of a novel reliability computer aided design tool, ERNI-3D.

Placement method for integrated circuit design using topo-clustering

Abstract: The present invention, generally speaking, provides a placement method for the physical design of integrated circuits in which natural topological feature clusters (topo-clusters) are discovered and exploited during the placement process. Topo-clusters may be formed based on various criteria including, for example, functional similarity, proximity (in terms of number of nets), and genus. Genus refers to a representation of a netlist in terms of a number of planar netlists—netlists in which no crossing of nets occurs. Topo-clusters drive initial placement, with all of the gates of a topo-cluster being placed initially in a single bin of the placement layout or within a group of positionally-related bins. The portion of a topo-cluster placed within a given bin is called a quanto-cluster. An iterative placement refinement process then follows, using a technique referred to herein as Geometrically-Bounded FM (GBFM), and in particular Dual GBFM. In GBFM, FM is applied on a local basis to windows encompassing some number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region does not participate. The cost function takes account of actual physical metrics—delay, area, congestion, power, etc. “Dual” refers to the fact that each iteration has two phases. During a first phase, FM is performed within a region on a quanto-cluster basis. During a second phase, FM is performed within the region on a gate basis. GBFM occurs in the context of recursive quadrisection. Hence, after GBFM has been completed, a further quadrisection step is performed in which each bin is divided into four bins, with a quarter of the gates of the original bin being placed in the center of each of the resulting bins. GBFM then follows, and the cycle repeats until each bin contains a fairly small number of gates. Following the foregoing global placement process, the circuit is then ready for detailed placement in which cells are assigned to placement rows.

Layout-driven memory synthesis for embedded systems-on-chip

Abstract: Memory-processor integration offers new opportunities for reducing, the energy of a system. In the case of embedded systems, where memory access patterns can typically be profiled at design time, one solution consists of mapping the most frequently accessed addresses onto the on-chip SRAM to guarantee power and performance efficiency. In this work, we propose an algorithm for the automatic partitioning of on-chip SRAMs into multiple banks. Starting from the dynamic execution profile of an embedded application running on a given processor core, we synthesize a multi-banked SRAM architecture optimally fitted to the execution profile. The algorithm computes an optimal solution to the problem under realistic assumptions on the power cost metrics, and with constraints on the number of memory banks. The partitioning algorithm is integrated with the physical design phase into a complete flow that allows the back annotation of layout information to drive the partitioning process. Results, collected on a set of embedded applications for the ARM processor, have shown average energy savings around 34%.

Computation of design values for Class E amplifiers without using waveform equations

Abstract: This paper presents a novel design procedure for Class E amplifiers without using waveform equations. By the proposed design procedure, Class E amplifiers can be designed regardless of the Q factor of resonant circuit, existence of the switch on resistor, and so on. The proposed design procedure requires only circuit equations and design specifications. All design procedures reported until now require deriving waveform equations which requires a lot of work. The benefits of the proposed design procedure is that it is to deriving waveform equations is no longer necessary. When the circuit equations are obtained, the other procedures for computation of design values are carried out with aid of computer. Therefore, we can design Class E amplifier more easily than the conventional design procedure. The authors design Class E amplifiers by using the proposed design procedures and carry out the circuit experiments, and find that the experimental results agree with calculation results, and show the validity of the proposed design procedure.

Electronic circuit designing method and apparatus, and storage medium

Abstract: An electronic circuit designing method and apparatus designs an electronic circuit by CAD, by generating design constraints with respect to the electronic circuit based on at least one of general layout and wiring information related to devices and wirings included in the electronic circuit, user requirements defined by a user, and user resources defined by the user, and urging an input to the user by displaying the design constraints.

Circuit designing apparatus, circuit designing method and timing distribution apparatus

Abstract: The invention provides a circuit designing apparatus which includes a circuit information database for storing information regarding a circuit, an automatic designing processing section for reading out the information regarding the circuit from the circuit information database and designing the circuit for each predetermined unit to be processed, and a design information database for storing design information obtained by the automatic designing processing section and including peculiarizing information of circuit elements, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit. The circuit designing apparatus allows a desired circuit to be automatically produced, regenerated or optimized.

CYCLONE: automated design and layout of RF LC-oscillators

Abstract: This paper presents a specification-driven layout-aware CMOS RF LC-oscillator design tool called CYCLONE. Circuit sizing and layout generation are integrated in the overall oscillator optimization. The tool optimizes the device sizes and also determines the optimal geometrical parameters of the on-chip inductor and automatically performs electromagnetic simulations to exactly calculate its losses during sizing. For the other devices in the oscillator circuit, being gain cell and varactor diode, it uses a technology-independent template-based layout generation approach to obtain accurate predictions of the actual layout parasitics. The device sizing of the gain cell is based on an operating-point linearized BSIM3 model of the gain cell transistors. The varactor diode is sized based on the BSIM3 source/drain diode models of the pMOS transistor. All parasitics; are incorporated in a global optimization of the complete oscillator circuit. After optimization of the circuit, the layout can be exported to a standard GDSII format for processing. The capabilities of the tool are demonstrated by several design experiments.

Method and apparatus for securing electronic circuits

Abstract: A method and apparatus for protecting the stored information on an integrated circuit from being compromised through reverse engineering. To do so, the method and apparatus splits the functionality of an integrated circuit into two separate integrated circuits, which are then connected in an interlocking manner. A detection circuit monitors the interconnection of the two separate integrated circuits. Upon detection of a break in the interconnection of the two circuits, the detection circuit destroys the data stored in the two separate integrated circuits. The two integrated circuits are connected in a flip-chip fashion, thereby preventing access to the underlying conduction paths and charge storage sites which are normally used in reverse engineering an integrated circuit.

A delay metric for RC circuits based on the Weibull distribution

Abstract: Physical design optimizations such as placement, interconnect synthesis, floorplanning, and routing require fast and accurate analysis of RC networks. Because of its simple close form and fast evaluation, the Elmore delay metric has been widely adopted. The recently proposed delay metrics PRIMO and H-gamma match the first three circuit moments to the probability density function of a gamma statistical distribution. Although these methods demonstrate impressive accuracy compared to other delay metrics, their implementations tend to be challenging. As an alternative to matching to the gamma distribution, we propose to match the first two circuit moments to a Weibull distribution. The result is a new delay metric called Weibull based Delay (WED). The primary advantages of WED over PRIMO and H-gamma are its efficiency and ease of implementation. Experiments show that WED is robust and has satisfactory accuracies at both near- and far-end nodes.

Circuit optimization via sequential computer experiments: design of an output buffer

Abstract: In electrical engineering, circuit designs are now often optimized via circuit simulation computer models. Typically, many response variables characterize the circuit’s performance. Each response is a function of many input variables, including factors that can be set in the engineering design and noise factors representing manufacturing conditions. We describe a modelling approach which is appropriate for the simulator’s deterministic input–output relationships. Non-linearities and interactions are identified without explicit assumptions about the functional form. These models lead to predictors to guide the reduction of the ranges of the designable factors in a sequence of experiments. Ultimately, the predictors are used to optimize the engineering design. We also show how a visualization of the fitted relationships facilitates an understanding of the engineering trade-offs between responses. The example used to demonstrate these methods, the design of a buffer circuit, has multiple targets for the responses, representing different trade-offs between the key performance measures.

System and method for evaluation of electric characteristics of printed-circuit boards

Abstract: A printed-circuit board characteristic evaluation system is basically configured by an input device, a data processing device, a storage device and an output device. Herein, the input device inputs layout information representing an overall layout of a printed-circuit board installing at least one active component, from which layout information data regarding a power supply circuit is extracted and is stored in the storage device. The layout information data is converted to electric circuit information representing an equivalent circuit model with respect to a selected side of the printed-circuit board. Then, calculations are performed based on the layout information data to produce impedance characteristics with respect to the power supply circuit. A decision is made as to whether resonance is caused to occur in the power supply circuit on the basis of results of comparison of the impedance characteristics. The output device outputs the impedance characteristics as well as resonance information. If it is determined that resonance is caused to occur in the power supply circuit, the system changes the layout information, from which new layout information data is being extracted. In addition, a resonance suppression technique (e.g., installation of a decoupling capacitor) is applied to a certain point of the power supply circuit or a prescribed power terminal connecting position. Thus, the system is capable of performing evaluation as to whether printed-circuit boards are well designed to suppress variations of power voltages while inhibiting radiation of unwanted electromagnetic waves from occurring due to resonance of power supply circuits.

Signal integrity analysis system

Abstract: A method of signal integrity analysis includes providing a pre-defined circuit layout in SPICE format; selecting from a menu at least one of a technology, a driver, a driver package, a transmission line, a termination, a receiver package, a stimulus, a measurement, options, and sweep parameters for the predefined circuit layout; generating a SPICE netlist from the pre-defined circuit layout; simulating the predefined circuit layout from the SPICE netlist; and generating as output at least one of a listing, a waveform, and a signal measurement from the simulation of the pre-defined circuit layout.

Method of circuit verification in digital design

Abstract: The present invention relates to a method of circuit verification in digital design and in particular, relates to a method of register transfer level property checking to enable the same. Today's electrical circuit designs frequently contain up to several million transistors, and circuit designs need to be checked to ensure that circuits operate correctly. Formal methods for verification are becoming increasingly attractive since they confirm design behavior without exhausting simulating a design. A digital circuit design verification method, prior to a property checking process for each property of a non-reduced RTL model, determines a reduced RTL model which retains specific signal properties of a non-reduced RTL model which are to be checked. A linear signal width reduction causes an exponential reduction of the induced state space. Reducing state space sizes in general goes hand in hand with reduced verification runtimes, thus speeding up verification tasks.

An integrated approach to the facilities and material handling system design

Abstract: The facility layout problem involves the optimal location of manufacturing facilities into a workshop. The classical approach to the layout design is carried out in two separate steps: the first step is the construction of the block layout, i.e. the location of the departments into the workshop, and the second step is the design of the material handling system. The separate optimization of these two aspects of the problem leads to solutions that can be far from the total optimum. In this paper, an integrated approach to the facilities and material handling system design is proposed. Referring to a physical model, named the bay structure , and to a unidirectional AGV system, a genetic approach is proposed to individuate the locations of the departments, the positions of the pickup/delivery stations and the direction of the flow-path. The minimization of material handling cost is adopted as optimality criterion.

System and method for applying timing models in a static-timing analysis of a hierarchical integrated circuit design

Abstract: A system and method for automating a static-timing analysis of an integrated circuit design are provided. A representative system includes a network coupled to a plurality of data storage devices, the data storage devices containing a knowledge base that defines an integrated circuit design; a computer coupled to the network, the computer including logic for receiving information defining an integrated circuit representation from the plurality of data storage devices; and a memory element associated with the computer, the memory element configured to store logic, the logic configured to generate static-timing scripts that reflect a plurality of timing models. A representative method includes the following steps: acquiring circuit information, the circuit information comprising a plurality of functional blocks; identifying a timing model to apply to each of the plurality of functional blocks; defining the hierarchical relationships between each of the plurality of functional blocks; extracting the circuit information responsive to the identifying and defining steps to complete a simulation of each of the plurality of functional blocks; and forwarding the simulation to a static-timing engine.

Container spaces and functional features for top-down 3D layout design

Abstract: Although there have been many advances in computer-aided modelling techniques and representations of mechanical parts, there are areas where exact modelling is a handicap. One of these is 3D layout design. Here, simpler models are useful for initial design sketches to verify kinematic behaviour and organise product structure before the detailed component design phase begins. A commitment to exact, or close approximational geometry too early can imply a commitment to form before functionality has been finalised. This paper describes a system for top-down 3D layout design based on simple conceptual elements which can be used as a basis for visualisation, discussion, definition of product structure and kinematic functionality in the conceptual design phase before the embodiment or detailing begins. This tool forms a bridge between the abstract nature of the conceptual design phase and the geometric nature of the embodiment phase. The 3D layout module uses design spaces with simple geometry and kinematic connections to represent a product. The design spaces act as containers or envelopes within which the final component design is to be realised. The kinematic connections allow the behaviour of the product to be simulated to gain more information (such as overall component dimensions and areas of potential collisions) for the detailed design phase. In addition the paper describes the design process based on the proposed 3D layout design system and contrasts this with the traditional design process. An industrial case study is presented to illustrate the following advantages of the proposed approach: (i) the design process proceeds faster because unnecessary layout parameter and constraint modifications are avoided since kinematic functionality verification precedes the detail design, (ii) the design process can produce better designs since alternative solution principles can be explored early in the design process. Theoretical issues are discussed concerning kinematic constraint inheritance during design space decomposition and concerning computer support for non-rigid design spaces.

Algorithm and methodology for the polygonalization of sparse circuit schematics

Abstract: An method of creating a physical layout of an integrated circuit. A schematic file ( 600 ) is mapped directly to a physical layout using the location of elements and routing of interconnections as specified in the schematic file ( 600 ). The method takes advantage of constraints on the schematic design to provide the layout file ( 675 ) quickly, without complex routing programs. Design rules violations are anticipated and corrected in some cases. In other cases, the design rule violations are annotated, if the designer intentionally placed them in the design.

Pre-silicon verification path coverage

Abstract: A method for verifying a path coverage of a circuit design. The method generally comprises the steps of implementing a hardware description language to include a plurality of monitors for a plurality of nodes of the circuit design, monitoring the nodes of a programmable circuit implementing the circuit design in real-time to capture node data, and assessing the node data to determine the path coverage.