Showing papers on "Physical design published in 2004"

Integrating vertical and horizontal partitioning into automated physical database design

Abstract: In addition to indexes and materialized views, horizontal and vertical partitioning are important aspects of physical design in a relational database system that significantly impact performance. Horizontal partitioning also provides manageability; database administrators often require indexes and their underlying tables partitioned identically so as to make common operations such as backup/restore easier. While partitioning is important, incorporating partitioning makes the problem of automating physical design much harder since: (a) The choices of partitioning can strongly interact with choices of indexes and materialized views. (b) A large new space of physical design alternatives must be considered. (c) Manageability requirements impose a new constraint on the problem. In this paper, we present novel techniques for designing a scalable solution to this integrated physical design problem that takes both performance and manageability into account. We have implemented our techniques and evaluated it on Microsoft SQL Server. Our experiments highlight: (a) the importance of taking an integrated approach to automated physical design and (b) the scalability of our techniques.

A thermal-driven floorplanning algorithm for 3D ICs

Abstract: As the technology progresses, interconnect delays have become bottlenecks of chip performance. 3D integrated circuits are proposed as one way to address this problem. However, thermal problem is a critical challenge for 3D IC circuit design. We propose a thermal-driven 3D floorplanning algorithm. Our contributions include: (1) a new 3D floorplan representation, CBA and new interlayer local operations to more efficiently exploit the solution space; (2) an efficient thermal-driven 3D floorplanning algorithm with an integrated compact resistive network thermal model (CBA-T); (3) two fast thermal-driven 3D floorplanning algorithms using two different thermal models with different runtime and quality (CBA-T-Fast and CBA-T-Hybrid). Our experiments show that the proposed 3D floorplan algorithm with CBA representation can reduce the wirelength by 29% compared with a recent published result from (Hsiu et al., 2004). In addition, compared to a nonthermal-driven 3D floorplanning algorithm, the thermal-driven 3D floorplanning algorithm can reduce the maximum on-chip temperature by 56%.

DB2 design advisor: integrated automatic physical database design

Abstract: The DB2 Design Advisor in IBM® DB2® Universal DatabaseTM (DB2 UDB) Version 8.2 for Linux®, UNIX® and Windows® is a tool that, for a given workload, automatically recommends physical design features that are any subset of indexes, materialized query tables (also called materialized views), shared-nothing database partitionings, and multidimensional clustering of tables. Our work is the very first industrial-strength tool that covers the design of as many as four different features, a significant advance to existing tools, which support no more than just indexes and materialized views. Building such a tool is challenging, because of not only the large search space introduced by the interactions among features, but also the extensibility needed by the tool to support additional features in the future. We adopt a novel "hybrid" approach in the Design Advisor that allows us to take important interdependencies into account as well as to encapsulate design features as separate components to lower the reengineering cost. The Design Advisor also features a built-in module that automatically reduces the given workload, and therefore provides great scalability for the tool. Our experimental results demonstrate that our tool can quickly provide good physical design recommendations that satisfy users' requirements.

Circuit Design with VHDL

Abstract: This textbook teaches VHDL using system examples combined with programmable logic and supported by laboratory exercises. While other textbooks concentrate only on language features, Circuit Design with VHDL offers a fully integrated presentation of VHDL and design concepts by including a large number of complete design examples, illustrative circuit diagrams, a review of fundamental design concepts, fully explained solutions, and simulation results. The text presents the information concisely yet completely, discussing in detail all indispensable features of the VHDL synthesis. The book is organized in a clear progression, with the first part covering the circuit level, treating foundations of VHDL and fundamental coding, and the second part covering the system level (units that might be located in a library for code sharing, reuse, and partitioning), expanding upon the earlier chapters to discuss system coding. Part I, "Circuit Design," examines in detail the background and coding techniques of VHDL, including code structure, data types, operators and attributes, concurrent and sequential statements and code, objects (signals, variables, and constants), design of finite state machines, and examples of additional circuit designs. Part II, "System Design," builds on the material already presented, adding elements intended mainly for library allocation; it examines packages and components, functions and procedures, and additional examples of system design. Appendixes on programmable logic devices (PLDs/FPGAs) and synthesis tools follow Part II. The book's highly original approach of teaching through extensive system examples as well as its unique integration of VHDL and design make it suitable both for use by students in computer science and electrical engineering.

Directional and single-driver wires in FPGA interconnect

Abstract: Modern FPGA architectures from Altera and Xilinx have shifted away from allowing multiple drivers to connect to each interconnect wire. This work advocates the need for this shift to single-driver wiring by investigating the necessary architectural and circuit design changes. When single-driver wiring is used, area improves by 25%, delay improves by 9%, and area-delay improves by 32% compared to bidirectional wiring. Wiring capacitance is reduced by 37% due to reduced switch loading and physical wire length shrinkage. Furthermore, it is shown that larger circuits tend to realize larger savings. No significant CAD tool changes are needed.

Technology, performance, and computer-aided design of three-dimensional integrated circuits

Abstract: We present an overview of a new monolithic fabrication technology known as three-dimensional integration. 3D integration refers to any process by which multiple conventional device layers may be stacked and electrically interconnected. By combining state-of-the-art single-wafer integration with a high-density inter-wafer interconnect, our 3D integration process is capable of providing improved circuit performance in terms of metrics such as wire length, area, timing, and energy consumption. In this paper, we will discuss the overall 3D integration process flow, as well as specific technological challenges and the issues they present to circuit designers. We will also describe how these issues may be tackled during the placement, routing, and layout stages of physical design. Finally, we will present some performance results that may be obtained by integrating circuits in three dimensions.

An integrated design flow for a via-configurable gate array

Abstract: In This work we present a complete physical design flow for a via-configurable gate array (VCGA). The VCGA is an array of prefabricated logic blocks and fixed metal masks. The block consists of via-configurable functional cells and a via-decomposable flip-flop. An M1-M2 via mask is used to define the block's functionality. Interconnects are customized using via masks. We developed a physical design flow for VCGA, which integrates a set of effective techniques. Here, we highlight the packing, cell-binding, and detailed-routing problems. We use our design flow to compare the VCGA-based and standard-cell/FPGA-based designs. Experimental results show the efficiency of our flow.

Physical design methodologies for performance predictability and manufacturability

Abstract: The Physical Design Methodology of Integrated Systems is increasing its relevance in deep submicron technologies due to the appearance of new problems related to electrical behavior and performance predictability. This paper presents some techniques to improve reliability and manufacturability by the use of some layout strategies. One main approach is the search of regular solutions as the use of a layout composed by a matrix of cells. It is discussed the effects of layout strategies in the design of reconfigurable systems.

Physical CAD changes to incorporate design for lithography and manufacturability

Abstract: The next few process generations (65 nm and below) will have serious lithography and manufacturing constraints since the feature size is shrinking much more rapidly than the wavelengths used in manufacturing the chips. This paper starts with a quick tutorial on the Design for Manufacturability problems of these process generations, concentrating primarily on the limitations of optical lithography. The remainder of the talk covers the changes to physical design tools, such as placement and routing, that are needed to cope with these problems.

A robust cell-level crosstalk delay change analysis

Abstract: In This work we present a robust and efficient methodology for crosstalk-induced delay change analysis for ASIC design styles. The approach employs optimization methods to search for worst aggressor alignment, and it computes crosstalk induced delay change on each stage considering an impact on downstream logic. Computational efficiency is achieved using pre-characterized current models for drivers and compact macromodels for interconnect. The proposed methodology has been implemented in a commercial noise analysis tool. Experimental results obtained on industrial designs demonstrate high accuracy and reduced pessimism of the proposed methodology.

Evaluation of low-leakage design techniques for field programmable gate arrays

Abstract: In this paper we evaluate the trade-offs between various low-leakage design techniques for field programmable gate arrays (FGPAs) in deep sub-micron technologies. Since multiplexers are widely used in FPGAs for implementing look up tables (LUTs) and connection and routing switches, several low-leakage implementations of pass transistor based multiplexers and routing switches are proposed and their design trade-offs are presented based on transistor-level simulation, physical design, and impact on overall system performance. We find that gate biasing, the use of redundant SRAM cells, and integration of multi-Vt technology are ideal for FPGAs, and they can reduce leakage current by 2X-4X compared to an implementation without any leakage reduction technique. For some of the potential low-leakage design techniques being evaluated in our study, the impact on chip area is very minimal to an increase of 15%-30%.

Apparatus and method for integrated circuit power management

Abstract: Methods and/or associated devices and/or systems for providing power management in electronic circuits, including custom ICs, programmable logic devices (Fig.2), and application specific integrated circuits (ASICs) places portions of various power management solutions in the 1/O ring or in VO macros (Fig.2). The invention has numerous specific embodiments and applications to a wide variety of 1Cs and logic or other circuit design components including circuit modules, software descriptions of circuit modules and/or design or simulation or test systems for circuit development.

An integrated environment for technology closure of deep-submicron IC designs

Abstract: With larger chip images and increasingly aggressive technologies, key design processes must interoperate, PDS, a physical-synthesis system, accomplishes technology closure through interacting processes of logic optimization, placement, timing, clock insertion, and routing, all using a common infrastructure with robust variable-accuracy analysis abstractions.

An automated tool deployment for ESD (electrostatic-discharge) correct-by-construction strategy in 90 nm process

Abstract: Continuous device scaling adhering to Moore's law imposes a greater challenge to the product design envelop. The complexity of ESD protection design can be enormous due to high degree of integration, including high signal count and mix-signal considerations. It is likely to take several design iterations before the specified ESD requirements can be guaranteed (Dabral and Maloney, 1998; Amerasekera and Duvvury, 1995). In view of a shorter design cycle coupled with overwhelming technological challenges in the leading edge 90nm process, an automated tool (RVCAT-ESD) has been deployed for the verification of ESD design rules during the product development stage. The tool can effectively verify both local and global ESD protection rules on the design database. The tool is also capable of providing a panoramic view of the ESD violation nodes in the design layout using the "overlay" feature. This helps to efficiently pin-point ESD design weaknesses in the design layout, such as current congestion, insufficient metal width and etc. This allows ESD design rules compliance in the early design stage, thus enhancing the approach of "correct-by-construction" on ESD design.

Multi-layer floorplanning for reliable system-on-package

Abstract: Physical design automation for the new emerging mixed-signal system-on-package (SOP) technology requires a new kind of floorplanner - it must place both active components such as digital IC, analog ICs, memory modules, MEMS, and optoelectronic modules, and embedded passive components such as capacitors, resistors and inductors in a multi-layer packaging substrate while considering various signal integrity issues. We propose a new interconnect-centric multi-layer floorplanner named MF-SOP, which is based on a multiple objective stochastic simulated annealing method. The contribution of this work is to first formulate this new kind of floorplanning problem and then to develop an effective algorithm that handles various design constraints unique to SOP. The related experiments show that the area reduction of MF-SOP compared to its 2D counterpart is on the order of O(k) and wirelength reduction is 39% average for k-layer SOP, while satisfying design constraints.

Dynamic voltage scaling for portable devices

Abstract: A method and apparatus for voltage regulation uses, in one aspect, worst-case supply voltages specific to the process split of the integrated device at issue. In another aspect, a two-phase voltage regulation system and method identifies the characterization data pertinent to a family of integrated circuit devices in a first phase, and identifies an associated process split of a candidate integrated circuit device in a second phase. The characterization data from the first phase is then used to provide supply voltages that correspond to target frequencies of operation for the candidate device. In another aspect, a hybrid voltage regulator circuit includes an open loop circuit which automatically identifies the process split of the integrated circuit device and allows a regulator to modify supply voltage based on characterization data specific to that process split, and a closed loop circuit which fine-tunes the supply voltage. In one embodiment, the closed-loop circuit includes a critical path replica for providing estimated frequencies of operation necessary for a critical path in the integrated circuit device. A ring oscillator circuit may be used in one embodiment in the critical path and/or in the open loop circuit.

Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors

Abstract: In this paper, various circuit and system level design challenges for nanometer-scale devices and single-electron transistors are discussed, with an emphasis to the functional robustness and fault tolerance point of view. A set of general guidelines is identified for the design of very high-density digital systems using inherently unreliable and error-prone devices. The fundamental principles of a highly regular, redundant, and scalable design approach based on fixed-weight neural networks and multiple-valued logic are presented. It is demonstrated that the proposed design technique offers significantly improved immunity to permanent and transient faults occurring at the transistor level, and that it results in graceful degradation of circuit performance in response to device failures.

Quantum-dot cellular automata (QCA) circuit partitioning: problem modeling and solutions

Abstract: This paper presents the Quantum-Dot Cellular Automata (QCA) physical design problem, in the context of the VLSI physical design problem. The problem is divided into three subproblems: partitioning, placement, and routing of QCA circuits. This paper presents an ILP formulation and heuristic solution to the partitioning problem, and compares the two sets of results. Additionally, we compare a human-generated circuit to the ILP and Heuristic solutions. The results demonstrate that the heuristic is a practical method of reducing partitioning run time while providing a result that is close to the optimal for a given circuit.

Physical design system and method

Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Electronic circuit designing method apparatus for designing an electronic circuit, and storage medium for storing an electronic circuit designing method

Abstract: An electronic circuit designing method and apparatus designs an electronic circuit by CAD, by generating design constraints with respect to the electronic circuit based on at least one of general layout and wiring information related to devices and wirings included in the electronic circuit, user requirements defined by a user, and user resources defined by the user, and urging an input to the user by displaying the design constraints.

2.5D system integration: a design driven system implementation schema

Abstract: This paper investigates a 3D die-stacking based VLSI integration strategy, so-called 2.5D integration, which can potentially overcome many problems stumbling the development of monolithic System-on-Chip (SoC). In this paper, we review available fabrication technologies and testing solutions for the new integration strategy. We also propose a design driven system implementation schema for this new integration strategy. A layout synthesis framework is under development by us to analyze typical "what if" questions and resolve major physical attributes for a 2.5D system according to the design specification and constraints.

Method and system for translating software binaries and assembly code onto hardware

Abstract: A computer-aided hardware design system enables design of an actual hardware implementation for a digital circuit using a software implementation of an algorithm in assembly language or machine binary code by converting an algorithmic representation for a hardware design initially created in software assembly or machine binary code of a general-purpose processor, to a hardware design implementation (FPGA or ASIC) by translating software binaries or assembly code, targeted for general-purpose processors, into RTL VHDL or Verilog code to be synthesized using commercial logic synthesis and physical design tools onto FPGAs and ASICs. The system performs data flow, parallelism analysis and optimizations at the assembly and machine code level and alias analysis to analyze memory accesses and automatically identify the parallelism in the operations automatically identifying loops and other control constructs, and recognizing procedure and function calls. The system automatically generates test benches for verifying correctness of the designs.

Dissection of edges with projection points in a fabrication layout for correcting proximity effects

Abstract: Techniques for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Techniques include selecting from among all edges of all polygons in a proposed layout a subset of edges for which proximity corrections are desirable. The subset of edges includes less than all the edges. Evaluation points are established only for the subset of edges. Corrections are determined for at least portions of the subset of edges based on an analysis performed at the evaluation points. Other techniques include establishing a projection point on a first edge corresponding to the design layout based on whether a vertex of a second edge is within a halo distance. An evaluation point is determined for the first edge based on the projection point and characteristics of the first edge. It is then determined how to correct at least a portion of the edge for proximity effects based on an analysis at the evaluation point.

Post-layout leakage power minimization based on distributed sleep transistor insertion

Abstract: This paper introduces a new approach to sub-threshold leakage power reduction in CMOS circuits. Our technique is based on automatic insertion of sleep transistors for cutting sub-threshold current when CMOS gates are in stand-by mode. Area and speed overhead caused by sleep transistor insertion are tightly controlled thanks to: (i) a post-layout incremental modification step that inserts sleep transistors in an existing row-based layout; (ii) an innovative algorithm that selects the subset of cells that can be gated for maximal leakage power reduction, while meeting user-provided constraints on area and delay increase. The presented technique is highly effective and fully compatible with industrial back-end flows, as demonstrated by post-layout analysis on several benchmarks placed and routed with state-of-the art commercial tools for physical design.

Design of routing-constrained low power scan chains

Abstract: Scan-based architectures, though widely used in modern designs, are expensive in power consumption. Recently, we proposed a technique based on clustering and reordering of scan cells that allows to design low power scan chains. The main feature of this technique is that power consumption during scan testing is minimized while constraints on scan routing are satisfied. In this paper, we propose a new version of this technique. The clustering process has been modified to allow a better distribution of scan cells in each cluster and hence lead to more important power reductions. Results are provided at the end of the paper to highlight this point and show that scan design constraints (length of scan connections, congestion problems) are still satisfied.

Practical issues in high speed PCB design

Abstract: Current high-speed PCB (printed circuit board) designs need extra care due to the frequency of operation and reduced rise time signals. We present the main issues and parameters that a PCB designer has to consider and analyze before a board layout is created. First order approximation equations for various parameters are presented, based on the geometry of the PCB traces. Some useful design practices are also mentioned. As the speed of operation increases, the variables that are neglected in the lower frequency/higher rise time situation become more significant. Such parameters increase the complexity of the design. Three-dimensional analysis becomes a must to calculate and model interconnects accurately. This is where field solvers and the role of the signal integrity engineer come into play.

Semiconductor integrated circuit apparatus, measurement result management system, and management server

Abstract: A semiconductor integrated circuit apparatus, and more particularly a technology for measuring and managing a physical amount of factors that exert an influence upon an operation of a semiconductor integrated circuit is provided; more particularly, a semiconductor integrated circuit that is an object of measurement, and a measurement circuit which measures a physical factor that exerts an influence upon the actual operation of the semiconductor integrated circuit, such as jitter or noise jitter, and noise of this semiconductor integrated circuit are provided on an identical chip; also, a measurement result of the measurement circuit of the present invention is analyzed, and is fed back to a circuit for adjusting the semiconductor integrated circuit that is the object of measurement.

Layout printability optimization using a silicon simulation methodology

Abstract: The manufacturing complexity at the 90 nm and 65 nm technology nodes severely impacts the design. The traditional use of design rule based verification is no longer a guarantee of high yield once the chip has been manufactured. This paper describes many of the trends behind this phenomenon. A new approach to layout that moves from an abstraction approach to a modeling approach is proposed. In this new methodology, layouts are processed using resolution enhancement techniques and the results are simulated using lithographical models for a specific manufacturing process. The simulation results are used to identify critical regions in the layouts. The layouts are then optimized based on this analysis to improve their printability, manufacturability and yield.

Design of sub-10-picoseconds on-chip time measurement circuit

Abstract: The rapid pace of change in IC technology, specifically in speed of operation, demands sophisticated design solutions for IC testing methodologies. Moreover, the current technology of system-on-chip (SOC) makes great demands for testing internal speed accurately as the limitation on accessing internal nodes using I/O pins becomes more difficult. This paper presents two high-resolution time measurement schemes for digital BIST applications, namely: two-delay interpolation method (TDIM) and time amplifier. The two schemes are combined to produce a completely new design for BIST time measurement which offers two main advantages: a low range of timing measurement which has never been achieved before, and a small size of layout occupying 0.2 mm/sup 2/ or equivalent to 3020 transistors. These two features are undoubtedly compatible with present high-speed SOC design architectures.