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Showing papers on "Physical design published in 2006"


Journal ArticleDOI
TL;DR: In this paper, the design challenges that current and future processors must face, with stringent power limits, high-frequency targets, and the continuing system integration trends, are reviewed, and a first-generation Cell processor is described.
Abstract: This paper reviews the design challenges that current and future processors must face, with stringent power limits, high-frequency targets, and the continuing system integration trends. This paper then describes the architecture, circuit design, and physical implementation of a first-generation Cell processor and the design techniques used to overcome the above challenges. A Cell processor consists of a 64-bit Power Architecture processor coupled with multiple synergistic processors, a flexible IO interface, and a memory interface controller that supports multiple operating systems including Linux. This multi-core SoC, implemented in 90-nm SOI technology, achieved a high clock rate by maximizing custom circuit design while maintaining reasonable complexity through design modularity and reuse.

258 citations


Proceedings ArticleDOI
06 Mar 2006
TL;DR: This work develops the first systematic droplet routing method that can be integrated with biochip synthesis, which minimizes the number of cells used fordroplet routing, while satisfying constraints imposed by throughput considerations and fluidic properties.
Abstract: Recent advances in microfluidics are expected to lead to sensor systems for high-throughput biochemical analysis. CAD tools are needed to handle increased design complexity for such systems. Analogous to classical VLSI synthesis, a top-down design automation approach can shorten the design cycle and reduce human effort. We focus here on the droplet routing problem, which is a key issue in biochip physical design automation. We develop the first systematic droplet routing method that can be integrated with biochip synthesis. The proposed approach minimizes the number of cells used for droplet routing, while satisfying constraints imposed by throughput considerations and fluidic properties. A real-life biochemical application is used to evaluate the proposed method.

228 citations


Proceedings ArticleDOI
05 Nov 2006
TL;DR: This work presents a floorplan aware design method that considers the wiring complexity of the NoC during the topology synthesis process, and incorporates mechanisms to prevent deadlocks during routing, which is critical for proper operation of NoCs.
Abstract: With increasing communication demands of processor and memory cores in systems on chips (SoCs), scalable networks on chips (NoCs) are needed to interconnect the cores. For the use of NoCs to be feasible in today's industrial designs, a custom-tailored, application-specific NoC that satisfies the design objectives and constraints of the targeted application domain is required. In this work, we present a design methodology that automates the synthesis of such application-specific NoC architectures. We present a floorplan aware design method that considers the wiring complexity of the NoC during the topology synthesis process. This leads to detecting timing violations on the NoC links early in the design cycle and to have accurate power estimations of the interconnect. We incorporate mechanisms to prevent deadlocks during routing, which is critical for proper operation of NoCs. We integrate the NoC synthesis method with an existing design flow, automating NoC synthesis, generation, simulation and physical design processes. We also present ways to ensure design convergence across the levels. Experiments on several SoC benchmarks are presented, which show that the synthesized topologies provide a large reduction in network power consumption (2.78 times on average) and improvement in performance (1.59 times on average) over the best mesh and mesh-based custom topologies. An actual layout of a multimedia SoC with the NoC designed using our methodology is presented, which shows that the designed NoC supports the required frequency of operation (close to 900 MHz) without any timing violations. We could design the NoC from input specifications to layout in 4 hours, a process that usually takes several weeks

204 citations


Patent
29 Jun 2006
TL;DR: In this article, a filler cell placement algorithm was proposed to optimize the placement of the filler cells in an integrated circuit physical design process, and a method of optimizing the locations, number, and distribution of the customizable filler cells was provided.
Abstract: A system and method for optimizing customizable filler cells in an integrated circuit physical design process. In particular, a filler cell placement algorithm of the present disclosure is utilized in the method to optimize the customizable filler cells in a circuit layout. The filler cell placement algorithm performs the operation of selecting a starting point within a given circuit layout, selecting a direction in which the position of logic cells is adjusted, adjusting the position of logic cells and, thereby, combining filler cells in order to increase the accumulated area thereof; suspending the adjustment operation when a customizable filler cell is formed; and resuming the adjustment operation from the point of the newly formed customizable filler cell. Additionally, a method of optimizing the locations, number, and distribution of the customizable filler cells in an integrated circuit design by use of the filler cell placement algorithm is provided.

198 citations


Patent
31 Oct 2006
TL;DR: In this paper, a method of designing an integrated circuit is provided in which the design layout is optimized using a process model until the design constraints are satisfied by the image contours simulated by the process model.
Abstract: A method of designing an integrated circuit is provided in which the design layout is optimized using a process model until the design constraints are satisfied by the image contours simulated by the process model. The process model used in the design phase need not be as accurate as the lithographic model used in preparing the lithographic mask layout during data prep. The resulting image contours are then included with the modified, optimized design layout to the data prep process, in which the mask layout is optimized using the lithographic process model, for example, including RET and OPC. The mask layout optimization matches the images simulated by the lithographic process model with the image contours generated during the design phase, which ensures that the design and manufacturability constraints specified by the designer are satisfied by the optimized mask layout.

184 citations


Proceedings ArticleDOI
18 Sep 2006
TL;DR: The first generation of Niagara SPARC processors implements a power-efficient multi-threading architecture to achieve high throughput with minimum hardware complexity.
Abstract: This first generation of "Niagara" SPARC processors implements a power-efficient Chip Multi-Threading (CMT) architecture which maximizes overall throughput performance for commercial workloads. The target performance is achieved by exploiting high bandwidth rather than high frequency, thereby reducing hardware complexity and power. The UltraSPARC T1 processor combines eight four-threaded 64-b cores, a floating-point unit, a high-bandwidth interconnect crossbar, a shared 3-MB L2 Cache, four DDR2 DRAM interfaces, and a system interface unit. Power and thermal monitoring techniques further enhance CMT performance benefits, increasing overall chip reliability. The 378-mm2 die is fabricated in Texas Instrument's 90-nm CMOS technology with nine layers of copper interconnect. The chip contains 279 million transistors and consumes a maximum of 63 W at 1.2 GHz and 1.2 V. Key functional units employ special circuit techniques to provide the high bandwidth required by a CMT architecture while optimizing power and silicon area. These include a highly integrated integer register file, a high-bandwidth interconnect crossbar, the shared L2 cache, and the IO subsystem. Key aspects of the physical design methodology are also discussed

144 citations


Proceedings ArticleDOI
20 Mar 2006
TL;DR: In this paper, the authors describe the use of full-chip verification engines in current Design For Manufacturing (DFM) practices and extend the analysis to identify a set of key technologies and applications for the 45, 32 and 22 nm nodes.
Abstract: The past decade has experienced a remarkable synergy between Resolution Enhancement Technologies (RET) in Optical Lithography and Optical Proximity Correction (OPC). This heterogeneous array of patterning solutions ranges from simple rule-based to more sophisticated model-based corrections, including sub-resolution assist features, partially transmitting masks and various dual mask approaches. A survey of the evolutionary development from the early introduction of the first OPC engines in 1996 to the debut of Immersion Lithography in 2006 reveals that the convergence of RET and OPC has also enabled a progressive selection and fine-tuning of Geometric Design Rules (GDR) at each technology node, based on systematic adoption of lithographic verification. This paper describes the use of "full-chip" lithography verification engines in current Design For Manufacturing (DFM) practices and extends the analysis to identify a set of key technologies and applications for the 45, 32 and 22 nm nodes. As OPC-derived tools enter the stage of maturity, from a software standpoint, their use-model is being greatly broadened from the back-end mask tape-out flow, upstream, directly integrated into physical design verification. Lithography awareness into the physical design environment, mediated by new DFM verification tools and flows, is driving various forms of manufacturable physical layout implementation: from Restricted Design Rules and Flexible Design Rules to Regular Circuit Fabrics. As new lithography solutions, such as immersion lithography and EUV, will have to be deployed within a complex technology framework, the paper also examines the trend towards "layout design regularization" and its implications for patterning and next generation lithographies.

119 citations


Proceedings ArticleDOI
09 Apr 2006
TL;DR: This talk gives an introduction to the electromigration problem and its relationship to current density, then presents various physical design constraints that affect electromigration, and introduces components of an electromigration-aware physical design flow.
Abstract: Electromigration is increasingly relevant to the physical design of electronic circuits. It is caused by excessive current density stress in the interconnect. The ongoing reduction of circuit feature sizes has aggravated the problem over the last couple of years. It is therefore an important reliability issue to consider electromigration-related design parameters during physical design. In this talk, we give an introduction to the electromigration problem and its relationship to current density. We then present various physical design constraints that affect electromigration. Finally, we introduce components of an electromigration-aware physical design flow.

101 citations


Proceedings ArticleDOI
06 Mar 2006
TL;DR: This paper presents a novel heuristic technique consisting of system-level physical design, and interconnection network generation that generates custom low power NoC architectures for application specific SoC.
Abstract: Network-on-Chip (NoC) has been proposed to replace traditional bus based architectures to address the global communication challenges in nanoscale technologies. In future SoC architectures, minimizing power consumption will continue to be an important design goal. In this paper, we present a novel heuristic technique consisting of system-level physical design, and interconnection network generation that generates custom low power NoC architectures for application specific SoC. We demonstrate the quality of the solutions produced by our technique by experimentation with many benchmarks. Our technique has a low computational complexity, and consumes only 1.25 times the power consumption, and 0.85 times the number of router resources compared to an optimal MILP based technique [ 1] whose computational complexity is not bounded.

85 citations


Patent
23 May 2006
TL;DR: Improved techniques for stacking integrated circuit dies within an integrated circuit package are disclosed in this article, which allow greater stacking density of IC dies within a package and also permit conventional bonding techniques for electrical connection of the various IC dies to each other or to a substrate.
Abstract: Improved techniques for stacking integrated circuit dies within an integrated circuit package are disclosed. These improved techniques allow greater stacking density of integrated circuit dies within an integrated circuit package. Additionally, the improved stacking techniques permit conventional bonding techniques for electrical connection of the various integrated circuit dies to each other or to a substrate. These improved approaches are particularly useful for stacking same size (and often same function) integrated circuit dies within integrated circuit packages. One example of such an integrated circuit package is a non-volatile memory integrated circuit package that contains multiple, like-sized memory storage integrated circuit dies arranged in a stack.

81 citations


Proceedings ArticleDOI
01 Oct 2006
TL;DR: The ability of the flow to calculate feature failure rates and the application of the failure rates for yield learning is demonstrated through volume data analysis on a production ASIC.
Abstract: This paper presents a flow for using logic diagnosis to turn production material into vehicles for yield learning. High throughput logic diagnosis is combined with the newly emerging field of design for manufacturing to enable layout aware diagnosis. The ability of the flow to calculate feature failure rates and the application of the failure rates for yield learning is demonstrated through volume data analysis on a production ASIC.

Patent
01 Jun 2006
TL;DR: In this article, the first component of an integrated circuit has a dynamic characteristic that varies among like integrated circuits, for example, among integrated circuits fabricated using the same lithography mask.
Abstract: An integrated circuit has a first component that has a dynamic characteristic that varies among like integrated circuits, for example, among integrated circuits fabricated using the same lithography mask. Operating the first component produces an output that is dependent on the dynamic characteristic of the first component. A digital value associated with the integrated circuit is generated using the output of the first component, and then the generated digital value is used in operation of the integrated circuit.

Proceedings ArticleDOI
01 Dec 2006
TL;DR: In this paper, the integrity of bonded Cu interconnects has been investigated as a function of pattern geometry and density, as well as bonding process parameters, and it was found that a pattern density around or more than 13 % coupled with the application of a small downforce (~1000 N) prior to temperature ramping and followed by large down-force during bonding gives optimal yield and alignment accuracy, and provides excellent electrical connectivity and thermal reliability.
Abstract: Three-dimensional integration (3DI) is a very promising fabrication methodology for extending the CMOS technology roadmap. As such, it is critical to evaluate the capability of this technique to provide reliable interconnection between stacked circuit layers. Since one of potential approaches for 3DI is through use of Cu bonded interconnects, the viability of this process is evaluated in this paper. More specifically, the integrity of bonded Cu interconnects has been investigated as a function of pattern geometry and density, as well as bonding process parameters. It is found that a pattern density around or more than 13 % coupled with the application of a small down-force (~1000 N) prior to temperature ramping and followed by large down-force (~10000 N) during bonding gives optimal yield and alignment accuracy, and provides excellent electrical connectivity and thermal reliability. This result is a key milestone in establishing the manufacturability of Cu-based interconnections for 3D integration technology

Proceedings ArticleDOI
05 Nov 2006
TL;DR: In this article, a variability-aware method that clusters gates at design time into a handful of carefully chosen independent body bias groups, which are then individually tuned post-silicon for each die.
Abstract: Adaptive body biasing (ABB) is a powerful technique that allows post-silicon tuning of individual manufactured dies such that each die optimally meets the delay and power constraints. Assigning individual bias control to each gate leads to severe overhead, rendering the method impractical. However, assigning a single bias control to all gates in the circuit prevents the method from compensating for intra-die variation and greatly reduces its effectiveness. In this paper, we propose a new variability-aware method that clusters gates at design time into a handful of carefully chosen independent body bias groups, which are then individually tuned post-silicon for each die. We show that this allows us to obtain near-optimal performance and power characteristics with minimal overhead. For each gate, we generate the probability distribution of its post-silicon ideal body bias voltage using an efficient sampling method. We then use these distributions and their correlations to drive a statistically-aware clustering technique. We study the physical design constraints and show how the area and wirelength overhead can be significantly limited using the proposed method. Compared to a fixed design time based dual threshold voltage assignment method, we improve leakage power by 38-71% while simultaneously reducing the standard deviation of delay by 2-9X.

BookDOI
23 Mar 2006
TL;DR: This work discusses design for Manufacturability in the Nanometer Era, FPGA Synthesis and Physical Design, and Mixed-Signal Noise Coupling in System-on-Chip Design: Modeling, Analysis and Validation.
Abstract: Design Flows. Logic Synthesis. Power Analysis and Optimization from Circuit to Register Transfer Levels. Equivalence checking. Digital Layout - Placement. Static Timing Analysis. Structured Digital Design. Routing. Exploring Challenges of Libraries for Electronic Design. Design Closure. Tools for Chip-Package Codesign. Design Databases. FPGA Synthesis and Physical Design. Simulation of Analog and Radio Frequency Circuits and Systems. Simulation and Modeling for Analog and Mixed-Signal Integrated Circuits. Layout Tools for Analog ICs and Mixed-Signal SoCs. Design Rule Checking. Resolution Enhancement Technology and Mask Data Preparation. Design for Manufacturability in the Nanometer Era. Power Supply Network Design and Analysis. Noise Considerations in Digital ICs. Layout Extraction. Mixed-Signal Noise Coupling in System-on-Chip Design: Modeling, Analysis and Validation. Process Simulation. Device Modeling: From Physics to Electrical Parameter Extraction. High-Accuracy Parasitic Extraction.

Patent
26 Apr 2006
TL;DR: In this paper, a method of routing a random logic macro (RLM) that is used multiple times in a hierarchical VLSI design without having to route each individual instantiation independently is presented.
Abstract: A method of routing a random logic macro (RLM) that is used multiple times in a hierarchical VLSI design without having to route each individual instantiation independently. Once an RLM has been routed and timed it can be copied and reused in a physical design as is, and does not require any wiring changes. This method is an advantage over existing art because it conserves area, improves wireability, and reduces the time required for routing and timing each RLM instance. Furthermore, each RLM possesses the same timing and power characteristics, which improves overall circuit performance.

Journal ArticleDOI
TL;DR: In this paper, a general and effective procedure based on a mathematical programming approach for composite structures optimal design, under weight, stiffness and strength criteria, is presented, which is able to find a local optimum in few iterations, even with a large number of design variables.

Patent
04 Aug 2006
TL;DR: In this paper, the authors present a method of designing and producing an integrated circuit, where each performance interval is independently optimized for performance versus power by assigning to each interval a different corresponding supply voltage.
Abstract: Disclosed are embodiments of a method of designing and producing an integrated circuit. During the pre-release chip design process, the method subdivides the overall process window for an integrated circuit design into smaller successive intervals corresponding to achievable performance. Each performance interval is independently optimized for performance versus power by assigning to each interval a different corresponding supply voltage. Timing for the design is then closed for each interval at each assigned voltage. After chip manufacturing, the method measures the performance of the integrated circuits that are manufactured according to the design. Using these performance measurements, the circuits are sorted into bins corresponding to each performance interval and appropriately labeled (e.g., with the performance goal and previously assigned supply voltage corresponding to the performance interval).

Proceedings Article
06 Mar 2006
TL;DR: The concepts of design for manufacturability and design for yield DFM/DFY are bringing together domains that co-existed mostly separated until now until now $circuit design, physical design and manufacturing process.
Abstract: The concepts of Design for Manufacturability and Design for Yield DFM/DFY are bringing together domains that co-existed mostly separated until now -- circuit design, physical design and manufacturing process. New requirements like SoC, mixed analog/digital design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to design and verify integrated circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the designed and manufactured circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. For technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. Redesigns and, therefore, respins of the whole development and manufacturing chain lead to high costs of multiple manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the design phase of digital, analog, and mixed-signal circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels -- both for digital as well as for analog is a big challenge. Yield analysis and optimization is currently applied to individual circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (On Chip Variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to design individual blocks with high robustness (>6σ). For abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. For the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices.

Proceedings ArticleDOI
24 Jan 2006
TL;DR: MEVA-3D, an automated physical design and architecture performance estimation flow for 3D architectural evaluation which includes 3D floorplanning, routing, interconnect pipelining and automated thermal via insertion, and associated die size, performance, and thermal modeling capabilities, is developed.
Abstract: Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact on overall system performance is still poorly understood due to the lack of tools and systematic flows to evaluate 3D microarchitectural designs. The contribution of this paper is the development of MEVA-3D, an automated physical design and architecture performance estimation flow for 3D architectural evaluation which includes 3D floorplanning, routing, interconnect pipelining and automated thermal via insertion, and associated die size, performance, and thermal modeling capabilities. We apply this flow to a simple, out-of-order superscalar microprocessor to evaluate the performance and thermal behavior in 2D and 3D designs, and demonstrate the value of MEVA-3D in providing quantitative evaluation results to guide 3D architecture designs. In particular, we show that it is feasible to manage thermal challenges with a combination of thermal vias and double-sided heat sinks, and report modest system performance gains in 3D designs for these simple test examples.

Proceedings ArticleDOI
24 Jan 2006
TL;DR: An efficient and accurate thermal-aware floor-planning high-level synthesis system that makes use of integrated high- level and physical-level thermal optimization techniques to reduce the design's power consumption and peak temperature is proposed.
Abstract: Thermal effects are becoming increasingly important during integrated circuit design. Thermal characteristics influence reliability, power consumption, cooling costs, and performance. It is necessary to consider thermal effects during all levels of the design process, from the architectural level to the physical level. However, design-time temperature prediction requires access to block placement, wire models, power profile, and a chip-package thermal model. Thermal-aware design and synthesis necessarily couple architectural-level design decisions (e.g., scheduling) with physical design (e.g., floorplanning) and modeling (e.g., wire and thermal modeling). This article proposes an efficient and accurate thermal-aware floor-planning high-level synthesis system that makes use of integrated high-level and physical-level thermal optimization techniques. Voltage islands are automatically generated via novel slack distribution and voltage partitioning algorithms in order to reduce the design's power consumption and peak temperature. A new thermal-aware floorplanning technique is proposed to balance chip thermal profile, thereby further reducing peak temperature. The proposed system was used to synthesize a number of benchmarks, yielding numerous designs that trade off peak temperature, integrated circuit area, and power consumption. The proposed techniques reduces peak temperature by 12.5/spl deg/C on average. When used to minimize peak temperature with a fixed area, peak temperature reductions are common. Under a constraint on peak temperature, integrated circuit area is reduced by 9.9% on average.

Proceedings ArticleDOI
24 Jul 2006
TL;DR: Physical design experiments were performed on a low-power and a high-performance design in an existing 3DIC technology, and it is shown that thermal-vias offer no performance benefit for the low- power system and only marginal benefit forThe high- performance system.
Abstract: Three-dimensional integrated circuits (3DICs) have the potential to reduce interconnect lengths and improve digital system performance. However, heat removal is more difficult in 3DICs, and the higher temperatures increase delay and leakage power, potentially negating the performance improvement. Thermal vias can help to remove heat, but they create routing congestion, which also leads to longer interconnects. It is therefore very difficult to tell whether or not a particular system may benefit from 3D integration. In order to help understand this trade-off, physical design experiments were performed on a low-power and a high-performance design in an existing 3DIC technology. Each design was partitioned and routed with varying numbers of tiers and thermal-via densities. A thermal-analysis methodology is developed to predict the final performance. Results show that the lowest energy per operation and delay are achieved with 4 or 5 tiers. These results show a reduction in energy and delay of up to 27% and 20% compared to a traditional 2DIC approach. In addition, it is shown that thermal-vias offer no performance benefit for the low-power system and only marginal benefit for the high-performance system.

Journal ArticleDOI
TL;DR: A new approach to analysis and design of feedback systems, based on the general feedback theorem (GFT), is discussed.
Abstract: Design-oriented analysis is a paradigm based on the recognition that design is the reverse of analysis, because the answer to the analysis is the start big point for design. Conventional loop or node analysis leads to a result in the form of a "high entropy expression," which is a ratio of sums of products of the circuit elements. There are many methods of D-OA, some of them little more than shortcuts or tricks. In this paper, the spotlight is on a new approach to analysis and design of feedback systems, based on the general feedback theorem (GFT) is discussed.

Patent
06 Jan 2006
TL;DR: A reprogrammable integrated circuit as discussed by the authors is a set of logic dies including circuit components, connected to the circuit components to define signal routing paths between the components to allow a user to develop an integrated circuit.
Abstract: A reprogrammable integrated circuit, including one or more logic dies including circuit components; and one or more reprogrammable interconnect dies including reprogrammable interconnect components electrically connected to the circuit components to define signal routing paths between the circuit components to allow a user to develop an integrated circuit.

Journal ArticleDOI
TL;DR: Experimental results show that this new layout synthesis tool is capable of producing high quality layouts comparable to those manually done by layout experts but with much less design time.
Abstract: In this paper, a layout synthesis tool for the design of analog integrated circuits (ICs) is presented. This tool offers great flexibility that allows analog circuit designers to bring their special design knowledge and experiences into the synthesis process to create high-quality analog circuit layouts. Different from conventional layout systems that are limited to the optimization of single devices, our layout generation tool attempts to optimize more complex modules. This tool includes a complete tool suite that covers the following three major analog physical designs stages. 1) Module Generation: designers can develop and maintain their own technology- and application-independent module generators for subcircuits using an in-house developed description language. 2) Placement: a two-stage placement technique, tailored for the analog placement design, is proposed. In particular, this placement algorithm features a novel genetic placement stage followed by a fast simulated reannealing scheme. 3) Routing: the minimum-Steiner-tree-based global routing is developed, and it is actually integrated into the placement procedure to improve reliability and routability of the placement solutions. Following the global routing, a compaction-based constructive detailed routing finally completes the interconnection of the entire layout. Several testing circuits have been applied to demonstrate the design efficiency and the effectiveness of this tool. Experimental results show that this new layout tool is capable of producing high quality layouts comparable to those manually done by layout experts but with much less design time

Journal ArticleDOI
TL;DR: This paper presents the first FPGA-floorplanning algorithm targeted for FPGAs with heterogeneous resources, and can generate floorplans for Xilinx's XC3S5000 architecture (largest of the Spartan3 family) in a few minutes.
Abstract: Modern field-programmable gate arrays (FPGAs) have multimillions of gates and future generations of FPGAs will be even more complex. This means that floorplanning tools will soon be extremely important for the physical design of FPGAs. Due to the heterogeneous logic and routing resources of an FPGA, FPGA floorplanning is very different from the traditional floorplanning for application-specific integrated circuits. This paper presents the first FPGA-floorplanning algorithm targeted for FPGAs with heterogeneous resources (e.g., Xilinx's Spartan3 chips consisting of columns of configurable logic blocks, RAM blocks, and multiplier blocks). This algorithm can generate floorplans for Xilinx's XC3S5000 architecture (largest of the Spartan3 family) in a few minutes

Proceedings ArticleDOI
09 Apr 2006
TL;DR: This work identifies particularly difficult industrial instances and reproduce the failures of existing tools by modifying public-domain netlists, and proposes algorithms that facilitate floorplacement of these difficult instances.
Abstract: Physical Design of modern systems on chip is extremely challenging. Such digital integrated circuits often contain tens of millions of logic gates, intellectual property blocks, embedded memories and custom RTL blocks. At current and future technology nodes, their power and performance are impacted, more than ever, by the placement of their modules. However, our experiments show that traditional techniques for placement and floorplanning, and existing academic tools cannot reliably solve the placement task.To study this problem, we identify particularly difficult industrial instances and reproduce the failures of existing tools by modifying public-domain netlists. Furthermore, we propose algorithms that facilitate floorplacement of these difficult instances. Empirically, our techniques consistently produced legal placements, and on instances where comparison is possible, reduced wirelength by 3.5% over Capo 9.4 and 14.5% over PATOMA 1.0 --- the pre-existing tools that most frequently produced legal placements in our experiments.

Patent
25 Oct 2006
TL;DR: In this article, a test module is configured to operate between automated testing equipment and an integrated circuit to test time sensitive parameters of the integrated circuit, such as set-up time and hold time of individual data channels.
Abstract: Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test time sensitive parameters of the integrated circuit. The testing interface includes components for generating addresses, commands, and test data to be conveyed to the integrated circuit as well as a clock adjustment component. By adjusting the clock synchronization controlling the test signals to be conveyed to the integrated circuit, set-up time and hold time can be tested. The systems are configured to test set-up time and hold time of individual data channels, for example, an individual address line of the integrated circuit.

Proceedings ArticleDOI
05 Nov 2006
TL;DR: A unified post-litho device characterization model and circuit simulation for timing and power and the parameter extraction is included in the model which was omitted by previous works.
Abstract: For 65nm and below devices, even after optical proximity correction (OPC), the gate may still be non-rectangular. There are several limited works on the device and circuit characterizations for the post-OPC non-ideal-shape wafer images, with significant impacts on timing and power. Most of them, however, are based on the equivalent gate length models, which are different for timing and leakage, and thus hard to use for coherent circuit simulations. In this paper, we propose a unified post-litho device characterization model and circuit simulation for timing and power. To our best knowledge, this is the most accurate methodology for post-litho analysis, including timing, leakage and transient simulation. Based on this method, the parameter extraction is also included in the model which was omitted by previous works. A post-litho model card is proposed for circuit simulation to combine these two techniques. Our experimental results validate the new model.

Journal ArticleDOI
TL;DR: The experimental results show that by applying the proposed clustering algorithm, the previously reported best partitioning solutions from state-of-the-art partitioners are further improved.
Abstract: Circuit partitioning is a fundamental problem in very large-scale integration (VLSI) physical design automation. In this brief, we present a new connectivity-based clustering algorithm for VLSI circuit partitioning. The proposed clustering method focuses on capturing natural clusters in a circuit, i.e., the groups of cells that are highly interconnected in a circuit. Therefore, the proposed clustering method can reduce the size of large-scale partitioning problems without losing partitioning solution qualities. The performance of the proposed clustering algorithm is evaluated on a standard set of partitioning benchmarks-ISPD98 benchmark suite. The experimental results show that by applying the proposed clustering algorithm, the previously reported best partitioning solutions from state-of-the-art partitioners are further improved.