Showing papers on "Physical design published in 2008"

Three-Dimensional Integrated Circuit Design

Abstract: With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. This is due primarily to the inevitable increase in the distance among circuit elements and interconnect design solutions have become the greatest determining factor in overall performance. Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to enhance dramatically chip performance and functionality, while reducing the distance among devices on a chip. They promise solutions to the current "interconnect bottleneck" challenges faced by IC designers. They also may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits. A handy, comprehensive reference or a practical design guide, this book provides a sound foundation for the design of three-dimensional integrated circuits. * Demonstrates how to overcome "Interconnect Bottleneck" with 3D Integrated Circuit Design...leading edge design techniques offer solutions to problems (performance/power consumption/price) faced by all circuit designers. * The FIRST book on 3D Integrated Circuit Design...provides up-to-date information that is otherwise difficult to find; * Focuses on design issues key to the product development cyle...good design plays a major role in exploiting the implementation flexibilities offered in the third dimension; * Provides broad coverage of 3D IC Design, including Interconnect Prediction Models, Thermal Management Techniques, and Timing Optimization...offers practical view of designing 3D circuits.

Handbook of Algorithms for Physical Design Automation

Abstract: The physical design flow of any project depends upon the size of the design, the technology, the number of designers, the clock frequency, and the time to do the design. As technology advances and design-styles change, physical design flows are constantly reinvented as traditional phases are removed and new ones are added to accommodate changes in technology. Includes a personal perspective from Ralph Otten as he looks back on the major technical milestones in the history of physical design automation. Explore State-of-the-Art Techniques and TrendsHandbook of Algorithms for Physical Design Automation provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitioning, the book discusses significant advances in floorplanning representations and describes recent formulations of the floorplanning problem. The text also addresses issues of placement, net layout and optimization, routing multiple signal nets, manufacturability, physical synthesis, special nets, and designing for specialized technologies. Highly-Focused Information for Next Generation Design Problems Although several books on this topic are currently available, most are either too broad or out of date. Alternatively, proceedings and journal articles are valuable resources for researchers in this area, but the material is widely dispersed in the literature. This handbook pulls together a broad variety of perspectives on the most challenging problems in the field, and focuses on emerging problems and research results.

Three dimensional integrated circuits and methods of fabrication

Abstract: The invention relates to multi-planar logic components in a three-dimensional (3D) integrated circuit (IC) apparatus configuration. A multi-planar integrated circuit connected by through silicon vias is configured to connect microprocessor, FPGA and memory components. The integrated circuit components may be on tiles of layers of the 3D IC.

High-Performance Routing at the Nanometer Scale

Abstract: In this paper, we describe significant improvements to core routing technologies and outperform the best results from the International Symposium on Physical Design 2007 Global Routing Contest and the International Conference on Computer-Aided Design 2007 in terms of route completion and total wirelength.

Linear Circuit Design Handbook

Abstract: This book enables design engineers to be more effective in designing discrete and integrated circuits by helping them understand the role of analog devices in their circuit design. Analog elements are at the heart of many important functions in both discrete and integrated circuits, but from a design perspective the analog components are often the most difficult to understand. Examples include operational amplifiers, D/A and A/D converters and active filters. Effective circuit design requires a strong understanding of the operation of these analog devices and how they affect circuit design. TABLE OF CONTENTSCHAPTER 1: THE OP AMP CHAPTER 2: OTHER LINEAR CIRCUITS CHAPTER 3: SENSORS CHAPTER 4 RF/IF CIRCUITS CHAPTER 5: FUNDAMENTALS OF SAMPLED DATA SYSTEMS CHAPTER 6: CONVERTERS CHAPTER 7: DATA CONVERTER SUPPORT CIRCUITS CHAPTER 8 ANALOG FILTERS CHAPTER 9: POWER MANAGEMENT CHAPTER 10: PASSIVE COMPONENTS CHAPTER 11: OVERVOLTAGE EFFECTS ON ANALOG INTEGRATED CIRCUITS CHAPTER 12: PRINTED CIRCUIT BOARD (PCB) DESIGN ISSUES Key Features* comprehensive coverage of analog circuit components for the practicing engineer * market-validated design information for all major types of linear circuits* includes practical advice on how to read op amp data sheets and how to choose off-the-shelf op amps* full chapter covering printed circuit board design issues,

Integrated Circuit Cell Library for Multiple Patterning

Abstract: A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are linear-shaped and commonly oriented. The layout is split into a number of sub-layouts for the level of the cell. Each of the number of layout features in the layout is allocated to any one of the number of sub-layouts. Also, the layout is split such that each sub-layout is independently fabricatable. The sub-layouts for the level of the cell are stored on a computer readable medium.

An evolutionary algorithm-based approach to robust analog circuit design using constrained multi-objective optimization

Abstract: The increasing complexity of circuit design needs to be managed with appropriate optimization algorithms and accurate statistical description of design models in order to reach the design specifics, guaranteeing ''zero defects''. In the Design for Yield open problems are the design of effective optimization algorithms and statistical analysis for yield design, which require time consuming techniques. New methods have to balance accuracy, robustness and computational effort. Typical analog integrated circuit optimization problems are computationally hard and require the handling of multiple, conflicting, and non-commensurate objectives having strong nonlinear interdependence. This paper tackles the problem by evolutionary algorithms to produce tradeoff solutions on the Pareto Front. In this research work Integrated Circuit (IC) design has been formulated as a constrained multi-objective optimization problem defined in a mixed integer/discrete/continuous domain. The following real-life circuits, RF Low Noise Amplifier, LeapFrog Filter, and Ultra Wideband LNA, were selected as test bed. The proposed algorithm, A-NSGAII, was shown to produce acceptable and robust solutions in the tested applications, where state-of-art algorithms and circuit designers failed. The results show significant improvement in all the chosen IC design problems.

Circuit Design for Voltage Scaling and SER Immunity on a Quad-Core Itanium® Processor

Abstract: The 700mm2 65nm Itaniumreg processor doubles the number of cores over its predecessor, from 2 to 4. It also adds a system interface that is roughly as large as two cores, including six QuickPath interconnects and four FBDIMM channels. This 3x increase in logic circuits per socket presents two major circuit challenges that are addressed in this paper.

Automated optimization of an integrated circuit layout using cost functions associated with circuit performance characteristics

Abstract: An integrated circuit (IC) design system and method provide an optimization of a layout of an integrated circuit wherein an assessment is taken into account of the circuit performance characteristics and the layout of the IC design The system and method assess associated circuit performance characteristics, each as a cost function of a local pattern of shapes in an initial circuit layout, aggregate cost functions of the associated circuit performance characteristics to derive an integral performance number associated to the initial global circuit layout, perturb the integral performance number by varying the global circuit layout, and select perturbations that optimize the performance number, so as to optimize the global circuit layout Assessment is taken into account of the circuit performance characteristics based on the layout and the interdependence of the circuit performance characteristics for the IC design The physical process related effects such as well proximity effect and stress/strain engineering and/or performance parameters such as the P-N transistor size ratio are taken into account to achieve optimization

Design Procedure for Class E Switching Circuits Allowing Implicit Circuit Equations

Abstract: This paper presents novel design procedures for class E switching circuits allowing implicit circuit equations. Because of the allowance, circuit simulators can be used in the proposed design procedures. Moreover, the proposed design procedures also allow any conditions considered until now. The proposed design algorithms are implemented by using PSpice and OPTIMUS. This paper shows the design examples of two kinds of class E switching circuits. In particular, the design example of the class E oscillator shows the benefit of the proposed design procedure eminently, i.e., it is unnecessary to make an equivalent model of the semiconductor devices for the design. These design examples show the validity and effectiveness of the proposed design procedures.

Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias

Abstract: Adaptive body biasing is a powerful technique that allows post-silicon tuning of individual manufactured dies such that each die optimally meets the delay and power constraints. Assigning individual bias control to each gate leads to severe overhead, rendering the method impractical. However, assigning a single bias control to all gates in the circuit prevents the method from compensating for intra-die variation and greatly reduces its effectiveness. In this paper, we propose a new variability-aware method that clusters gates at design time into a handful of carefully chosen independent body-bias groups, which are then individually tuned post-silicon for each die. We show that this allows us to obtain near-optimal performance and power characteristics with minimal overhead. For each gate, we generate the probability distribution of its post-silicon ideal body bias voltage using an efficient sampling method. We then use these distributions and their correlations to drive a statistically aware clustering technique. We study the physical design constraints and show how the area and wirelength overhead can be significantly limited using the proposed method. Compared with a fixed design-time based dual threshold voltage assignment method, we improve leakage power by 38%-68% while simultaneously reducing the standard deviation of delay by two to nine times.

Low-Temperature Cofired Ceramic LC Filters for RF Applications

Abstract: The latest wireless products demand ever-greater functionality, higher performance, and lower cost in smaller and lighter formats. This demand has been satisfied to date by major advances in integrated circuits and high-density packaging technologies, even though the RF sections have been continuing to demand high-performance and miniaturized passive components such as matching and filtering circuitries. Continuing reductions in the size of discrete surface-mounted components are having diminishing returns because of the incompatibility of printed circuit board (PCB) technology as well as the high cost of assembly for those tiny discrete components. Therefore, new technological approaches are required to address the integration of passives. One of the important means today for integrating passives, particularly for RF functions, is low temperature cofired ceramics (LTCCs). Besides the use of this technology for highly integrated RF front-end modules [1]‐[4], there has also been a great deal of interest in realizing compact LTCC-embedded or isolated components, ranging from traditional baluns [5], couplers [6], and filters [7]‐[10] to more sophisticated diplexers [11] and balanced filters [12]‐[13], for different wireless communication technologies such as mobile phones, Bluetooth, and/or wireless LAN (WLAN) equipped terminals. This article specifically focuses on the design and implementation details for lumped or semi-lumped LTCC bandpass filters. A variety of LTCC chip-type filters with different characteristics are widely available commercially. They are often specified by the center frequency, fractional bandwidth, insertion loss, and stopband attenuation. Some examples are given in Table 1. These filters are usually second-order or third-order and have their responses optimized for specific applications by taking advantage of flexible filtering characteristics of LTCC LC filters. In general, their design process starts with a schematic circuit usually obtained by computer-aided design techniques from which a physical layout realization is generated through electromagnetic (EM) simulation tools. Nevertheless, the conventional analytical design methods can always be used as a starting point in the design process. The general design procedure for an LTCC filter can be summarized as • derive a schematic circuit including parasitic elements • optimize the circuit to meet required specifications • generate a physical layout based on the circuit • tune the layout to meet required specifications • fabricate prototypes to verify the performance. Each of these steps has its own design aspects and should be addressed carefully. Generally, layout tuning is the most time-consuming step as it involves full-wave EM simulations. Therefore, having a good layout design to minimize the number of simulations is of primary concern. As miniaturized LTCC filters are usually second-order or third-order, their layouts should not be too complicated. Indeed, there are some well-known standard layout strategies that are commonly used in practice. In the following section, we will discuss some important issues for the whole design process.

Constrained physical design tuning

Abstract: Existing solutions to the automated physical design problem in database systems attempt to minimize execution costs of input workloads for a given a storage constraint. In this paper, we argue that this model is not flexible enough to address several real-world situations. To overcome this limitation, we introduce a constraint language that is simple yet powerful enough to express many important scenarios. We build upon an existing transformation-based framework to effectively incorporate constraints in the search space. We then show experimentally that we are able to handle a rich class of constraints and that our proposed technique scales gracefully.

Nano-CMOS Design for Manufacturability: Robust Circuit and Physical Design for Sub-65nm Technology Nodes

Abstract: This book is the sequel to Nano-CMOS Circuit and Physical Design, taking design to technology nodes beyond 65nm geometries. It examines the challenges that design engineers face in the nano-scaled era, such as exacerbated effects and the proven design for manufacturability (DFM) methodology in the midst of increasing variability and design process interactions. It also tackles complex issues in the design process and introduces several emerging concepts, including stress proximity effects, contour-based extraction, and design process interactions.

Configuration-parametric query optimization for physical design tuning

Abstract: Automated physical design tuning for database systems has recently become an active area of research and development. Existing tuning tools explore the space of feasible solutions by repeatedly optimizing queries in the input workload for several candidate configurations. This general approach, while scalable, often results in tuning sessions waiting for results from the query optimizer over 90% of the time. In this paper we introduce a novel approach, called Configuration-Parametric Query Optimization, that drastically improves the performance of current tuning tools. By issuing a single optimization call per query, we are able to generate a compact representation of the optimization space that can then produce very efficiently execution plans for the input query under arbitrary configurations. Our experiments show that our technique speeds-up query optimization by 30x to over 450x with virtually no loss in quality, and effectively eliminates the optimization bottleneck in existing tuning tools. Our techniques open the door for new, more sophisticated optimization strategies by eliminating the main bottleneck of current tuning tools.

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test

Abstract: As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays increase the likelihood of cells with marginal stability and pose strict constraints on transistor parameters distributions. Standard functional tests often fail to detect unstable SRAM cells. Undetected unstable cells deteriorate quality and reliability of the product as such cells may fail to retain the data and cause a system failure. Special design and test measures have to be taken to identify cells with marginal stability. However, it is not sufficient to identify the unstable cells. To ensure reliable system operation, unstable cells have to be repaired. CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies.

Partial Timing Modeling for Gate Level Simulation

Abstract: Various apparatuses, methods and systems for creating an integrated circuit and performing a gate level simulation of a circuit are disclosed herein. For example, some embodiments of the present invention provide a system for performing a gate level simulation of a circuit including a computer system, a design verification tool and an output device. The design verification tool, executable on the computer system, includes a simulator and a partial timing model generator. The partial timing model generator is operable to generate a representation of the circuit for simulation by cutting a first portion of a circuit out of a full gate level netlist for the circuit and leaving a second portion of the circuit represented by the full gate level netlist, and to overlay a simplified representation of the first portion of the circuit over the representation of the circuit. The first portion of the circuit is cut out at timing paths. The simulator is operable to perform a gate level simulation of the circuit based on the representation of the circuit. The output device is connected to the computer system and is operable to provide an indication of a result of the gate level simulation of the circuit.

Thermally-Aware Design

Abstract: With greater integration, the power dissipation in integrated circuits has begun to outpace the ability of today's heat sinks to limit the on-chip temperature. As a result, thermal issues have come to the forefront, and thermally aware design techniques are likely to play a major role in the future. While improved heat sink technologies are available, economic considerations restrict them from being widely deployed until and unless they become more cost-effective. Low power design is helpful in controlling on-chip temperatures, but is already widely utilized, and new thermal-specific approaches are necessary. In short, the onus on thermal management is beginning to move from the package designer toward the chip designer. This survey provides an overview of analysis and optimization techniques for thermally aware design. After beginning with a motivation for the problem and trends seen in the semiconductor industry, the survey presents a description of techniques for on-chip thermal analysis. Next, the effects of elevated temperatures on on-chip performance metrics are analyzed. Finally, a set of thermal optimization techniques, for controlling on-chip temperatures and limiting the level to which they degrade circuit performance, are described.

Robustness in automatic physical database design

Abstract: Automatic physical database design tools rely on "what-if" interfaces to the query optimizer to estimate the execution time of the training query workload under different candidate physical designs. The tools use these what-if interfaces to recommend physical designs that minimize the estimated execution time of the input training workload. In this paper, we argue that minimizing estimated execution time alone can lead to designs with inherent problems. In particular, if the optimizer makes an error in estimating the execution time of some workload queries, then the recommended physical design may actually harm the workload instead of benefiting it. In this sense, the physical design is risky. Moreover, if the production queries are slightly different from the training queries, the recommended physical design may not benefit them at all. In this sense, the physical design is not general. We define Risk and Generality as two new metrics to evaluate the quality of a proposed physical database design, and we show one way of extending the objective function being optimized by a generic physical design advisor to take these measures into account. We have implemented a physical design advisor in PostgreSQL, and we use it to experimentally demonstrate the usefulness of our approach. We show that our two new metrics result in physical designs that are more robust, which means that the user can implement them with a higher degree of confidence. This is particularly important as we move towards truly zero-administration database systems in which there is not the possibility for a DBA to vet the recommendations of the physical design tool before applying them.

Interactions of double patterning technology with wafer processing, OPC and design flows

Abstract: Double patterning technology (DPT) is one of the main options for printing logic devices with half-pitch less than 45nm; and flash and DRAM memory devices with half-pitch less than 40nm. DPT methods decompose the original design intent into two individual masking layers which are each patterned using single exposures and existing 193nm lithography tools. The results of the individual patterning layers combine to re-create the design intent pattern on the wafer. In this paper we study interactions of DPT with lithography, masks synthesis and physical design flows. Double exposure and etch patterning steps create complexity for both process and design flows. DPT decomposition is a critical software step which will be performed in physical design and also in mask synthesis. Decomposition includes cutting (splitting) of original design intent polygons into multiple polygons where required; and coloring of the resulting polygons. We evaluate the ability to meet key physical design goals such as: reduce circuit area; minimize rework; ensure DPT compliance; guarantee patterning robustness on individual layer targets; ensure symmetric wafer results; and create uniform wafer density for the individual patterning layers.

Shortening the design cycle

Abstract: Electromagnetics (EM) has today become a critical part of the microwave design cycle. This article briefly traces the entry of EM into microwave design and describes how today's design cycle arose. Then, we discuss how recent developments (in particular, perfectly calibrated ports in EM analysis) open entire new areas of applied microwave design.

Method and apparatus for automatic orientation optimization

Abstract: Methods and apparatuses are disclosed for automatic orientation optimization in the course of generating a placed, routed, and optimized circuit design. Also disclosed are a circuit design and circuit created with the technology. Also disclosed are a circuit design and circuit created with the technology.

Method and system for optimizing integrated circuit layout

Abstract: We disclose a method for optimizing integrated circuit layout which comprises analyzing constraint relationship among objects in an initial layout; constructing local modifications to the constraint relationship; forming new constraint relationships by combining initial constraint relationships with their local modifications; and producing a new layout by implementing the new constraint relationships. Local modification to constraints provides a framework for bringing detailed local information into the design process in a highly automated manner, which can be applied to a wide range of situations. We disclose preferred embodiments on improving lithography printability, reducing defect susceptibility, and improving circuit performance such as reducing layout variability and leakage.

A new approach for circuit design optimization using Genetic Algorithm

Abstract: A circuit designed by human often results in very complex hardware architectures, requiring a large amount of manpower and computational resources. A wider objective is used to find novel solutions to design such complex architectures so that system functionality and performance may not be compromised. Design automation using reconfigurable hardware and evolutionary algorithms (EA), such as genetic algorithm (GA), is one of the methods to tackle this issue. This concept applies the notion of Evolvable Hardware (EHW) to the problem domain such as novel design solutions and circuit optimization. EHW is a new field about the use of EA to synthesize a circuit. EA manipulates a population of individuals where each individual describes how to construct a candidate for a good circuit. Each circuit is assigned a fitness, which indicates how well a candidate satisfies the design specification. EA uses stochastic operators repeatedly to evolve new circuit configurations from existing ones, and a resultant circuit configuration will exhibit a desirable behavior. In this paper, optimum circuit design by using GA with fitness function composed of circuit complexity, power and time delay is proposed, and its effectiveness is shown by simulations.

Clustering circuit paths in electronic circuit design

Abstract: Techniques are disclosed for clustering circuit paths in an electronic design automation process for use in improving the timing characteristics of the overall circuit design. Circuit paths included in the cluster may be subjected to placing and routing as a group to relocate instances of circuit components included in the clustered circuit paths to thereby improve the overall circuit design timing.

Flexible noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs

Abstract: Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design may be partitioned into a plurality of circuit stages. A timing graph including timing arcs is constructed to represent the timing delays in circuit stages of the integrated circuit design. A model of each circuit stage may be formed including a model of a victim driver, an aggressor driver, a victim receiver, and a victim net and an aggressor net coupled together. For each timing arc in the timing graph, full timing delays may be computed for the timing arcs in each circuit stage.

Apparatus and method for integrated circuit design for circuit edit

Abstract: A method and apparatus for optimizing an integrated circuit design for post-fabrication circuit editing and diagnostics. The method and apparatus is specifically directed to adding designed-for-edit modifications and designed-for-diagnostics structures to an integrated circuit design for post-fabrication circuit editing with a charged-particle beam tool. An integrated circuit design may be modified to create efficient and reliable access to specified nodes and structures, such as spare gates, by the charged-particle beam tool during subsequent testing and debugging of the fabricated device. Additionally, structures such as spare gates, spare transistors, spare metal wires, and debug circuitry may be added to an integrated circuit design to provide for easier editing of portions of the design that may fail.

Gridded-router based wiring on a non-gridded library

Abstract: A computerized method for automatically generating a grid-based derivative of a non-gridded cell library of an integrated circuit design comprises the step of determining at least one valid position of at least one wiring element of a circuit of the first cell library, wherein the at least one valid position fulfills all technological design rules and wherein the at least one valid position fits into the second grid format. The method can also be used for automatically transforming a first cell library of an integrated circuit design having a first grid format into a second cell library having a second grid format or for automatically analyzing a grid-based cell library of an integrated circuit design in view of the circuit quality regarding technical design rules.