Showing papers on "Physical design published in 2011"

User-centered System Design

Abstract: Will reading habit influence your life? Many say yes. Reading user centered system design is a good habit; you can develop this habit to be such interesting way. Yeah, reading habit will not only make you have any favourite activity. It will be one of guidance of your life. When reading has become a habit, you will not make it as disturbing activities or as boring activity. You can gain many benefits and importances of reading.

VLSI Physical Design: From Graph Partitioning to Timing Closure

Abstract: Design and optimization of integrated circuits are essential to the creation of new semiconductor chips, and physical optimizations are becoming more prominent as a result of semiconductor scaling. Modern chip design has become so complex that it is largely performed by specialized software, which is frequently updated to address advances in semiconductor technologies and increased problem complexities. A user of such software needs a high-level understanding of the underlying mathematical models and algorithms. On the other hand, a developer of such software must have a keen understanding of computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact. VLSI Physical Design: From Graph Partitioning to Timing Closure introduces and compares algorithms that are used during the physical design phase of integrated-circuit design, wherein a geometric chip layout is produced starting from an abstract circuit design. The emphasis is on essential and fundamental techniques, ranging from hypergraph partitioning and circuit placement to timing closure.

CELONCEL: effective design technique for 3-D monolithic integration targeting high performance integrated circuits

Abstract: 3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequential order, the size of the vertical contacts is similar to traditional contacts unlike in the case of parallel 3-D integration with through silicon vias (TSVs). Given the advantage of such small contacts, 3DMI enables manufacturing multiple active layers very close to each other. In this work we propose two different strategies of stacking standard cells in 3-D without breaking the regularity of the conventional design flow: a) Vertical stacking of diffusion areas (Intra-Cell stacking) that supports complete reuse of 2-D physical design tools and b) vertical stacking of cells over others (Cell-on-Cell stacking). A placement tool (CELONCEL-placer) targeting the Cell-on-Cell placement problem is proposed to allow high quality 3-D layout generation. Our experiments demonstrate the effectiveness of CELONCEL technique, fetching us an area gain of 37.5%, 15.51% reduction in wirelength, and 13.49% improvement in overall delay, compared with a 2-D case when benchmarked across an interconnect dominated low-density-parity-check (LDPC) decoder at 45nm technology node.

Co-Design of an Active Suspension Using Simultaneous Dynamic Optimization

Abstract: Design of physical systems and associated control systems are coupled tasks; design methods that manage this interaction explicitly can produce system-optimal designs, whereas conventional sequential processes may not. Here we explore a new technique for combined physical system and control design (co-design) based on a simultaneous dynamic optimization approach known as direct transcription, which transforms infinite-dimensional control design problems into finite dimensional nonlinear programming problems. While direct transcription problem dimension is often large, sparse problem structures and fine-grained parallelism (among other advantageous properties) can be exploited to yield computationally efficient implementations. Extension of direct transcription to co-design gives rise to a new problem structures and new challenges. Here we illustrate direct transcription for co-design using a new automotive active suspension design example developed specifically for testing co-design methods. This example builds on prior active suspension problems by incorporating a more realistic physical design component that includes independent design variables and a broad set of physical design constraints, while maintaining linearity of the associated differential equations.© 2011 ASME

Post-Placement Power Optimization With Multi-Bit Flip-Flops

Abstract: Optimization for power is always one of the most important design objectives in modern nanometer integrated circuit design Recent studies have shown the effectiveness of applying multi-bit flip-flops to save the power consumption of the clock network This paper presents: 1) a novel design methodology of applying multi-bit flip-flops at the post-placement stage, which can be seamlessly integrated in modern design flow; 2) a new problem formulation for post-placement optimization with multi-bit flip-flops; 3) flip-flop clustering and placement algorithms to simultaneously minimize flip-flop power consumption and interconnecting wirelength; and 4) a progressive window-based optimization technique to reduce placement deviation and improve runtime efficiency of our algorithms Experimental results show that our algorithms are very effective in reducing not only flip-flop power consumption but also clock tree and signal net wirelength Consequently, the power consumption of the clock network is minimized

Proteus: An ASIC Flow for GHz Asynchronous Designs

Abstract: Editors' note:The high-performance benefits of asynchronous design have hitherto been obtained only using full-custom design. This article presents an industrial-strength asynchronous ASIC CAD flow that enables the automatic synthesis and physical design of high-level specifications into GHz silicon, greatly reducing design time and enabling far wider use of asynchronous technology.

Computer-Aided Analog Circuit Design for Reliability in Nanometer CMOS

Abstract: Integrated analog circuit design in nanometer CMOS technologies brings forth new and significant reliability challenges. Ever-increasing process variability effects and transistor wear-out phenomena such as BTI, hot carrier degradation and dielectric breakdown force designers to use large design margins and to increase the uncertainty on the circuit lifetime. To help designers to tackle these problems at design time (i.e., Design For Reliability, or DFR), accurate transistor aging models, efficient circuit reliability analysis methods and novel design techniques are needed. The paper overviews the current state of the art in DFR for analog circuits. The most important unreliability effects in nanometer CMOS technologies are reviewed and transistor aging models, intended for accurate circuit simulation, are described. Also, efficient methods for circuit reliability simulation and analysis are discussed. These methods can help designers to analyze their circuits and to identify weak spots. Finally, cost-effective design techniques for more resilient and self-healing analog circuits are studied.

Designing Cmos Circuits For Low Power

Abstract: Designing CMOS Circuits for Low Power provides the fundamentals of low power design for logic, circuit, and physical design level as well as the "design story" of two innovative low power systems developed in the context of European Low Power Initiative for Electronic System Design. The main objective is to present in-depth analytical and design capabilities for low power design CMOS circuits.

Comparative Evaluation of Layout Density in 3T, 4T, and MT FinFET Standard Cells

Abstract: In this paper, issues related to the physical design and layout density of FinFET standard cells are discussed. Analysis significantly extends previous analyses, which considered the simplistic case of a single FinFET device or extremely simple circuits. Results show that analysis of a single device cannot predict the layout density of FinFET cells, due to the additional spacing constraints imposed by the standard cell structure. Results on the layout density of FinFET standard cell circuits are derived by building and analyzing various cell libraries in 32-nm technology, based on three-terminal (3T) and four-terminal (4T) devices, as well as on the recently proposed cells with mixed 3T-4T devices (MT). The results obtained for spacer- and lithography-defined FinFETs are observed from the technology scaling perspective by also considering 45- and 65-nm libraries. The effect of the fin and cell height on the layout density is studied. Results show that 3T and MT FinFET standard cells can have the same layout density as bulk cells (or better) for low (moderate) fin heights. Instead, 4T standard cells have an unacceptably worse layout density. Hence, MT standard cells turn out to be the only viable option to apply back biasing in FinFET standard cell circuits.

Constraint-Based Layout-Driven Sizing of Analog Circuits

Abstract: A flow is presented for the automatic synthesis of an analog circuit layout based on a schematic and a list of circuit design parameter values. The flow is driven by design, placement, and routing constraints-no layout template is necessary. Every possible layout for each device in the circuit is investigated; the layouts with the best geometric features and smallest quantization error (due to manufacturing grid alignment) are kept. For circuit placement, a complete enumeration of possible circuit placements, limited only by usual constraints of symmetry, proximity, and common centroid, is performed. Out of this enumeration a final circuit placement is selected and routed. The new flow is integrated with a deterministic nonlinear optimization algorithm to perform layout-driven circuit sizing; layouts are synthesized during both gradient approximation and next step determination. Layout-driven circuit sizing was applied to two example circuits. Sizing of the first circuit example took 8× the amount of CPU time needed for traditional circuit sizing, but remained feasible at 2.1 h of wall clock time on a contemporary workstation.

A study of methodological issues in design and development of rule-based systems: proposal of a new approach

Abstract: Rule-based systems (RBSs) constitute a powerful technology for declarative encoding and automated processing of large bodies of knowledge. A typical RBS consists of a knowledge base containing facts and production rules, and an inference engine managing the reasoning process. Despite their simple conceptual scheme, design and development of a RBS often turn out to be unexpectedly complex task. This paper presents an overview of issues concerning design and development of such systems. Differences between RBSs and classical software are exemplified, and design and implementation issues are analyzed. A novel, consistent, three-phase methodology incorporating conceptual, logical, and physical design is outlined. Moreover, tools supporting the complete design and development process are presented. © 2011 John Wiley & Sons, Inc. WIREs Data Mining Knowl Discov 2011 1 117-137 DOI: 10.1002/widm.11

System and method for automated real-time design checking

Abstract: Systems and methods for real-time design checking of an integrated circuit design, include the operations of receiving at a design tool, design elements of an integrated circuit design entered by an integrated circuit designer; the design tool performing real-time design checks on the design elements as they are entered by the integrated circuit designer to determine whether a design element violates a design rule; when the design tool detects a violation of a design rule based on the design checks alerting the integrated circuit designer; and the design tool presenting a correction to correct the violation of the design rule. The real-time design checks can include, comparing each design element to one or more known non-compliant design elements stored in a database to determine whether a non-compliant design element was entered or is being entered by the integrated circuit designer.

Phase-Locked Loop Circuit Design

Abstract: Aiming at the defects of the existing analog phase-locked loop,the idea of fabricating analog phase-locked loop with imported VCXO is introduced in this article.The article also puts forward the design and selection of elements of the circuit.Test with experiment shows that feasibility of such scheme and the possibility of circuit improvement.

Design Framework for Soft-Error-Resilient Sequential Cells

Abstract: This paper presents a design framework for soft-error-resilient sequential cells, by introducing a new sequential cell called LEAP-DICE and evaluating it against existing circuit techniques in the “soft error resilience-power-delay-area” design space in an 180 nm CMOS test chip. LEAP-DICE, which employs both circuit and layout techniques, achieved the best soft error performance with a 2,000X improvement over the reference D flip-flop with moderate design costs. This study also discovered new soft error effects related to operating conditions.

Scalable meta-data objects

Abstract: A method is disclosed for defining an integrated circuit. The method includes generating a digital data file that includes both electrical connection information and physical topology information for a number of circuit components. The method also includes operating a computer to execute a layout generation program. The layout generation program reads the electrical connection and physical topology information for each of the number of circuit components from the digital data file and automatically creates one or more layout structures necessary to form each of the number of circuit components in a semiconductor device fabrication process, such that the one or more layout structures comply with the physical topology information read from the digital data file. The computer is also operated to store the one or more layout structures necessary to form each of the number of circuit components in a digital format on a computer readable medium.

Simultaneous Layout Migration and Decomposition for Double Patterning Technology

Abstract: Double patterning technology (DPT) and layout migration (LM) are two closely related problems on design for manufacturability in the nanometer era DPT decomposes a layout into two masks and applies double exposure patterning to increase pitch size and, thus, printability In this paper, we present the first algorithm in the literature for the simultaneous layout migration and decomposition (SMD) problem Our algorithm first constructs a potential conflict graph and DPT-aware constraint graphs, and then applies integer linear programming (ILP) corresponding to the graphs to obtain a decomposed and migrated layout We further present an effective graph-based reduction technique to prune the ILP solution space, which maintains the same DPT conflicts We also present a new DPT-aware objective for the SMD problem to minimize the difference between the original and migrated layouts while considering the DPT effects In addition, we present an approach to generate DPT-aware standard cells by considering the DPT effects on the cell boundaries; this technique improves the layout printability and facilitates electronic design automation tools to consider DPT Experimental results show that our algorithms can effectively generate conflict-free migrated layouts with 11% smaller layout areas and 21% smaller layout changes, compared with the traditional method of layout decomposition followed by LM In particular, our reduction technique reduces the ILP variables by 457%, the ILP constraints by 585%, and the DPT edges by 799% over the basic ILP formulation, leading to a substantial speedup For example, it can reduce the runtimes for the test cases from more than one day to only seconds

Process Variations and Probabilistic Integrated Circuit Design

Abstract: Uncertainty in key parameters within a chip and between different chips in the deep sub micron area plays a more and more important role. As a result, manufacturing process spreads need to be considered during the design process. Quantitative methodology is needed to ensure faultless functionality, despite existing process variations within given bounds, during product development. This book presents the technological, physical, and mathematical fundamentals for a design paradigm shift, from a deterministic process to a probability-orientated design process for microelectronic circuits. Readers will learn to evaluate the different sources of variations in the design flow in order to establish different design variants, while applying appropriate methods and tools to evaluate and optimize their design.

Thermal-electrical co-optimisation of floorplanning of three-dimensional integrated circuits under manufacturing and physical design constraints

Abstract: Although the stacking of multiple strata to produce three-dimensional (3D) integrated circuits (ICs) improves interconnect length and hence reduces power and latency, it also results in the exacerbation of the thermal management challenge owing to the increased power density. There is a need for design tools to understand and optimise the trade-off between electrical and thermal design at the device and block levels. This study presents results from thermal-electrical co-optimisation for block-level floorplanning in a multi-die 3D IC under various manufacturing and physical design constraints. A method for temperature computation based on linearity of the governing energy equation is presented. This method is combined with previously reported electrical delay models for 3D ICs to simultaneously optimise both the maximum temperature and the interconnect length. It is shown that co-optimisation of thermal and electrical objectives results in a floorplan that is attractive from both perspectives. Physical design constraints because of cost-effective 3D manufacturing such as using fully or partly identical dies using reciprocal design symmetry (RDS), differentiated technology in each die and thinned die/wafer are discussed and their impact on the thermal-electrical co-optimisation is investigated. In some cases, the cheapest manufacturing choice, such as using identical die, for each layer may not result in optimal thermal and electrical design. Results presented in this work highlight the need for thermal and electrical co-design in multi-strata microelectronics, and for reconciling manufacturing and design considerations in order to develop practical design tools for 3D ICs.

High-dimensional statistical modeling and analysis of custom integrated circuits (invited paper)

Abstract: Custom circuit designers have long favored manual equation-based approaches in early design stages, because it gives excellent insight and control over the design. However, this flow is threatened: as modern process nodes advance, process variation affects circuit performance more strongly, hurting the accuracy of existing equations. Because designers are typically not statistical modeling experts, it is difficult to adapt the equations to incorporate statistical variations. This paper presents a fast, deterministic technique to help designers revise equations to account for statistical variation. Specifically, the technique extracts compact equations of performance as a function of process variables, even for cases when there are thousands of possible variables and the equations are highly nonlinear. In fact, it provides a whole set of equations that trade off simplicity versus accuracy compared to SPICE. The technique is validated on a broad range of custom integrated circuit modeling problems.

Design, Modeling, and Control of a Camless Valve Actuation System With Internal Feedback

Abstract: This paper presents the modeling and control design of a new fully flexible engine valve actuation system, which is an enabler for camless engines. Unlike existing electromechanical or servo-actuated electrohydraulic valve actuation systems, precise valve motion control is achieved using a very stiff hydromechanical internal-feedback mechanism. The entire feedback mechanism is built into the physical design of the system. The external control only activates or deactivates the feedback mechanism in real time using simple two-state valves. This helps reduce the system cost, and thus enables mass production. The trajectory of the closed-loop system is purely dependent on the design parameters of the internal-feedback system. A mathematical model of the system has been developed and validated with experimental results from a prototype system. The “area-schedule” is identified as the most critical design feature, which affects the trajectory of the closed-loop system and, therefore, needs to be designed systematically to optimize the performance of the system as well as improve its robustness. By treating this feature as the feedback-control variable, the design problem is transformed into a nonlinear optimal control problem and solved numerically using dynamic programming. The effectiveness of the proposed design procedure is verified with case studies.

Methods, systems, and articles for multi-scenario physically-aware design methodology for layout-dependent effects

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing multi-scenario physically-aware design of electronic circuit design(s). In some embodiments, the method captures layout dependent effect(s) when a critical component instance, which corresponds to multiple candidate configurations, is being created in a physical design to enable a designer to create partial layout(s) from layout alternative(s) and to extract parameter(s) from the partial layout(s) in different layout contexts. The method may extract parasitics between components and analyzes impact(s) of layout dependent effect(s) on an electronic design by performing simulation(s) with layout dependent effect(s) in the schematic domain and may perform some partial routing based on some routing style(s) in each of the different layout contexts to generate just enough interconnects that may affect the electronic design.

Design of embedded memory and logic based on pattern constructs

Abstract: Design rules become ineffective for interfacing layout design and manufacturing when complex lithography sources are used for sub-20nm patterning. Experiments demonstrate feasibility of a construct-based design that facilitates control of process capabilities and captures layout dependent variations. Results for early 14nm patterning experiments are shown for logic and memory circuits.

Multiprocessor system-on-chip : hardware design and tool integration

Abstract: Part 1: Application Mapping and Communication Infrastructure: Virtualization in NOCs--Enhanced MPSOC Robustness and Performance Verification.-HW Support to Exploit Parallelism in Homogeneous and Heterogeneous Multicore System-on-Chip.-PALLAS: Mapping Applications onto Manycore.-Part 2: Reconfigurable Hardware in Multiprocessor Systems: Adaptive Multiprocessor System on Chip Architecture.-Designing FPGA Systems with Many Processors.-Part 3: Physical Design of Multiprocessor Systems: Design tools and methods for chip physical design.-Challenges in Physical Design for Multi- and Manycore Hardware Architectures.

Integrated development environment for rapid device development

Abstract: An integrated development environment for rapid device development is described. In an embodiment the integrated development environment provides a number of different views to a user which each relate to a different aspect of device design, such as hardware configuration, software development and physical design. The device, which may be a prototype device, is formed from a number of objects which are selected from a database and the database stores multiple data types for each object, such as a 3D model, software libraries and code-stubs for the object and hardware parameters. A user can design the device by selecting different views in any order and can switch between views as they choose. Changes which are made in one view, such as the selection of a new object, are fed into the other views.

Method and apparatus for pattern adjusted timing via pattern matching

Abstract: An approach is provided for pattern adjusted timing via pattern matching. Embodiments include receiving data corresponding to a problematic layout pattern associated with at least one performance characteristic and data corresponding to an integrated circuit layout design, scanning the integrated circuit layout design for the problematic layout pattern, identifying at least one portion of the integrated circuit layout design substantially matching the problematic layout pattern, and modifying a netlist associated with the integrated circuit layout design, the modification being based on the at least one performance characteristic.

A Python-based layout-aware analog design methodology for nanometric technologies

Abstract: This paper presents a methodology for procedural layout-aware design for nanometric technologies. A Python-based layout generation tool generates different layout styles for the same basic analog building blocks. Moreover, layout dependent parasitic parameters such as stress effects are easily computed and compared for different layout styles. The procedural layout description is written using a Python API that ensures layout portability over different technologies. A main focus is on how the layout generation tool addresses both geometric and parasitic-aware electrical synthesis. This is made possible through an internal loop that links circularly both the sizing phase and the layout generation phase. The proposed design methodology assists the analog designer in exploring electrical and physical trade-offs. At the end, we present synthesis and characterization results that prove the effectiveness and speed of the proposed methodology.

Automatic optimal integrated circuit generator from algorithms and specification

Abstract: Systems and methods are disclosed to automatically design a custom integrated circuit includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically devising a processor architecture and generating a processor chip specification uniquely customized to the computer readable code which satisfies the constraints; and synthesizing the chip specification into a layout of the custom integrated circuit.

Systems and methods for circuit design, synthesis, simulation, and modeling

Abstract: Systems and methods for specifying, modelings simulating, and implementing a circuit design using a circuit design database comprising re-usable program elements to represent circuit design elements. The re-usable program elements may be used to build an overall circuit design description in the database. In example embodiments, the circuit design may be structured as a computer program and library to deterministically specify the circuit design elements to be used. Circuit synthesis functionality and circuit simulation functionality may be embedded as part of the re-usable program elements. Libraries may be compiled with the computer program instructions specifying the circuits to generate an executable that can be used for synthesis and simulation The combined executable code may be executed on an instruction set processor directly or through an interpreter.

From RTL to GDSII: An ASIC design course development using Synopsys® University Program

Abstract: The development of an ASIC design course using the Synopsys® University Program lectures, labs and tools is presented in this paper. The ASIC design course lasts for 20 weeks and the students learn the design flow using tools including Design Compiler™, IC Compiler™ and PrimeTime™. The syllabus is developed based on the Synopsys® University Program Curriculum. Besides the curriculum, the students are assigned projects to synthesize some small circuits to gain more in-depth knowledge about the ASIC design flow. A keystone project is assigned to facilitate the application of the entire IC physical design flow on an industrial size processor design.