Showing papers on "Physical design published in 2017"

Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques

Abstract: The threat of hardware reverse engineering is a growing concern for a large number of applications. A main defense strategy against reverse engineering is hardware obfuscation. In this paper, we investigate physical obfuscation techniques, which perform alterations of circuit elements that are difficult or impossible for an adversary to observe. The examples of such stealthy manipulations are changes in the doping concentrations or dielectric manipulations. An attacker will, thus, extract a netlist, which does not correspond to the logic function of the device-under-attack. This approach of camouflaging has garnered recent attention in the literature. In this paper, we expound on this promising direction to conduct a systematic end-to-end study of the VLSI design process to find multiple ways to obfuscate a circuit for hardware security. This paper makes three major contributions. First, we provide a categorization of the available physical obfuscation techniques as it pertains to various design stages. There is a large and multidimensional design space for introducing obfuscated elements and mechanisms, and the proposed taxonomy is helpful for a systematic treatment. Second, we provide a review of the methods that have been proposed or in use. Third, we present recent and new device and logic-level techniques for design obfuscation. For each technique considered, we discuss feasibility of the approach and assess likelihood of its detection. Then we turn our focus to open research questions, and conclude with suggestions for future research directions.

Shrunk-2-D: A Physical Design Methodology to Build Commercial-Quality Monolithic 3-D ICs

Abstract: Monolithic 3-D (M3D) integrated circuits (ICs) are an emerging technology that offer much higher integration densities than previous 3-D IC approaches. In this paper, we present a complete netlist-to-layout design flow to design an M3D block, as well as to integrate 2-D and 3-D blocks into an M3D SoC. This design flow is based on commercial tools built for 2-D ICs, and enhanced with our 3-D specific methodologies. We use the OpenSPARC T2 SoC as a case study, implement it in a 28-nm fully depleted silicon on insulator foundry process, and demonstrate that we can achieve up to 12% and 8% power savings for a single block and SoC, respectively, when compared with their 2-D counterparts implemented using commercial tools.

Close-to-optimal placement and routing for continuous-flow microfluidic biochips

Abstract: Continuous-flow microfluidics rapidly evolved in the last decades as a solution to automate laboratory procedures in molecular biology and biochemistry. Therefore, the physical design of the corresponding chips, i.e., the placement and routing of the involved components and channels, received significant attention. Recently, several physical design solutions for this task have been presented. However, they often rely on general heuristics which traverse the search space in a rather arbitrary fashion and, additionally, consider placement and routing independently from each other. Consequently, the obtained results are often far from being optimal. In this work, a methodology is proposed which aims for determining close-to-optimal physical designs for continuous-flow microfluidic biochips. To this end, we consider all — or, at least, as much as possible — of the valid solutions. As this obviously yields a significant complexity, solving engines are utilized to efficiently traverse the search space and pruning schemes are proposed to reduce the search space without discarding too many promising solutions. Evaluations show that the proposed methodology is capable of determining optimal results for small experiments to be realized. For larger experiments, close-to-optimal results can efficiently be derived. Moreover, compared to the current state-of-the-art, improvements of up to 1–2 orders of magnitude can be observed.

End-to-end scalable FPGA accelerator for deep residual networks

Abstract: This work presents an efficient hardware accelerator design of deep residual learning algorithms, which have shown superior image recognition accuracy (>90% top-5 accuracy on ImageNet database). Two key objectives of the acceleration strategy are to (1) maximize resource utilization and minimize data movements, and (2) employ scalable and reusable computing primitives to optimize physical design under hardware constraints. Furthermore, we present techniques for efficient integration and communication of these primitives in deep residual convolutional neural networks (CNNs) that exhibit complex, non-uniform layer connections. The proposed hardware accelerator efficiently implements state-of-the-art ResNet-50/152 algorithms on Arria-10 FPGA, demonstrating 285.1/315.5 GOPS of throughput and 27.2/71.7 ms of latency, respectively.

Toward Optimal Legalization for Mixed-Cell-Height Circuit Designs

Abstract: Modern circuits often contain standard cells of different row heights to meet various design requirements. Higher cells give larger drive strengths at the costs of larger areas and power. Multi-row-height standard cells incur challenging issues to layout designs, especially the mixed-cell-height legalization problem due to the heterogeneous cell structures. Honoring the good cell positions from global placement, we present in this paper a fast and near-optimal algorithm to solve the legalization problem. Fixing the cell ordering from global placement and relaxing the right boundary constraints, we first convert the problem into a linear complementarity problem (LCP). With the converted LCP, we split its matrices to meet the convergence requirement of a modulus-based matrix splitting iteration method (MMSIM), and then apply the MMSIM to solve the LCP. This MMSIM method guarantees the optimality if no cells are placed beyond the right boundary of a chip. Finally, a Tetris-like allocation approach is used to align cells to placement sites on rows and fix the placement of out-of-right-boundary cells, if any. Experimental results show that our proposed algorithm can achieve the best cell displacement and wirelength among all published methods in reasonable runtimes. The MMSIM optimality is theoretically proven and empirically validated. In particular, our formulation provides new generic solutions and research directions for various optimization problems that require solving large-scale quadratic programs efficiently.

ToPoliNano: A CAD Tool for Nano Magnetic Logic

Abstract: In the post-CMOS scenario, field coupled nanotechnologies represent an innovative and interesting new direction for electronic nanocomputing. Among these technologies, nanomagnet logic (NML) makes it possible to finally embed logic and memory in the same device. To fully analyze the potential of NML circuits, design tools that mimic the CMOS design-flow should be used for circuit design. We present, in this paper, the latest and improved version of Torino Politecnico Nanotechnology (ToPoliNano), our design and simulation framework for field coupled nanotechnologies. ToPoliNano emulates the top-down design process of CMOS technology. Circuits are described with a VHSIC hardware description language netlist and layout is then automatically generated considering in-plane NML (iNML) technology. The resulting circuits can be simulated and performance can be analyzed. In this paper, we describe several enhancements to the tool itself, like a circuit editor for custom design of field coupled nanodevices, improved algorithms for netlist optimization and new algorithms for the place and route of iNML circuits. We have validated and analyzed the tool by using extensive metrics, both by using standard circuits and ISCAS’85 benchmarks. This contribution highlights the improvements of ToPoliNano, which is now a innovative and complete tool for the development of iNML technology.

Security-Aware 2.5D Integrated Circuit Design Flow Against Hardware IP Piracy

Abstract: To combat security threats to integrated circuit (IC) fabrication outsourcing, 2.5D integration can obfuscate the outsourced design by lifting a portion of the wires into an interposer layer. A security-aware physical design flow for 2.5D IC technology can then help defend against attacks by increasing the layout and functionality obfuscation.

An Integrated Circuit Design for a Dynamics-Based Reconfigurable Logic Block

Abstract: In this brief, a nonlinear integrated circuit to harvest different types of digital computation from complex dynamics is designed and fabricated. This circuit can be dynamically reconfigured to implement different two-input, one-output digital functions. The main advantage of the circuit is the ability to implement different digital functions in each clock cycle without halting for reconfiguration.

Design flows and collateral for the ASAP7 7nm FinFET predictive process design kit

Abstract: Educators and researchers exploring integrated circuit design methods need models and design flows for advanced integrated circuit processes. As commercial processes have become highly proprietary, predictive technology models fill the gap. This work describes a design flow for ASAP7, the first 7 nm FinFET PDK, including schematic and layout entry, library characterization, synthesis, placement and routing, parasitic extraction, and HSPICE simulation.

ASAP7 predictive design kit development and cell design technology co-optimization: Invited paper

Abstract: This work discusses the ASAP7 predictive process design kit (PDK) and associated standard cell library. The necessity for multi-patterning (MP) techniques at advanced nodes results in the standard cell and SRAM architecture becoming entangled with design rules, mandating design-technology co-optimization (DTCO). This paper discusses the DTCO process involving standard cell physical design. An assumption of extreme ultraviolet (EUV) lithography availability in the PDK allows bi-directional M1 geometries that are difficult with MP. Routing and power distribution schemes for self-aligned quadruple patterning (SAQP) friendly, high density standard cell based blocks are shown. Restrictive design rules are required and supported by the automated place and route (APR) setup. Supporting sub-20 nm dimensions with academic tool licenses is described. The APR (QRC techfile) extraction shows high correlation with the Calibre extraction deck. Finally, use of the PDK for academic coursework and research is discussed.

Nanoelectronic Mixed-Signal System Design [Book Reviews]

Abstract: The book covers the entire spectrum of modern integrated circuit (IC) technologies from the design and simulation point of view, starting at the schematic level and progressing through to actual physical design. There are many senior- and graduate level textbooks centered on traditional digital very-large-scale integration (VLSI) design. The topic is robust, mature, and has been taught for decades. In parallel, there is a much smaller population of texts focused on analog IC design with an emphasis on designing specific modules, such as amplifiers, analog-to-digital and digital-to-analog converters, receivers, transmitters, filters, and other esoteric topics. Absent from the latter category of textbooks are the discussions of system-centered analog design geared toward integration into an SoC. The intersection of these two design disciplines is commonly known as mixed-signal or analog/mixed-signal (AMS) design, a topic that has received very little attention. There are only a handful of books on the subject, usually at very advanced levels; most are collections of loosely connected chapters or papers. This dearth of information is at odds with the fact that all IC design these days is AMS by virtue of the design methodologies developed and the systems themselves: pure digital systems, even though still tremendously useful for computation, do not reflect daily usage of commodity electronics dictated by our connected society. This book covers the entire spectrum of modern IC technologies from the design and simulation point of view, starting at the schematic level and progressing through to actual physical design, including postlayout simulation and design optimization, always with a systems emphasis. The audience for this massive and authoritative treatise includes those interested in AMS IC design, particularly at the nano level, and the book also addresses the needs of everyone in that scope: college seniors, master’s and Ph.D. students as well as practicing engineers, designers, and computer-aided design developers. It can be used both as a text and reference book at the same time, since it covers an immense amount of state-of-the-art material.

Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System

Abstract: A realistic assessment of optical networks-on-chip (ONoCs) can be performed only in the context of a comprehensive floorplanning strategy for the system as a whole, especially when the 3-D stacking of electronic and optical layers is implemented. This paper fosters layout-aware ONoC design by developing a physical mapping methodology for wavelength-routed ONoC topologies subject to the floorplanning, placement, and routing constraints that arise in a 3-D-stacked environment. As a result, this paper is able to compare the power efficiency and signal-to-noise ratio of ring-based versus filter-based wavelength-routed topologies as determined by their physical design flexibility.

Quantum circuit physical design flow for 2D nearest-neighbor architectures

Abstract: The physical design process takes a netlist generated by the logic synthesis process and places and routes the netlist on a physical platform. In some physical platforms, physical qubits must be placed on a 2D grid. Each node of the grid represents a qubit. In these platforms, performing quantum gates on non-adjacent qubits is very error prone or hard to control. Therefore, quantum gates are limited to be performed on adjacent qubits. A communication channel of swap gates needs to be constructed if the qubits in the logical circuit are not adjacent. The algorithms used for mapping of qubits on the grid have important roles in reducing the number of swap gates and thus decreasing of the circuit latency. Focusing on this issue, in this paper, a flow for physical design of quantum circuits on a 2D grid is proposed. It contains three algorithms for finding the order of qubit placement, physical qubit placement, and routing. Simulation results show that the proposed flow not only decreases the average number of swap gates by about 16% compared with the best in the literature but also improves the average runtime by about 94% compared with it. Copyright © 2017 John Wiley & Sons, Ltd.

Efficient and reliable fault analysis methodology for nanomagnetic circuits

Abstract: Summary The increasing issues in scaled Complementary Metal Oxide Semiconductor (CMOS) circuit fabrication favor the flourishing of emerging technologies. Because of their limited sizes, both CMOS and emerging technologies are particularly sensitive to defects that arise during the fabrication process. Their impact is not easy to analyze in order to take the necessary countermeasures, especially in the case of circuits of realistic complexity based on emerging technologies. In this work, we propose a new methodology supported by an efficient and reliable tool for the identification of the impact of faults in complex circuits implemented using the emerging technology we are focusing on in this case: nanomagnetic logic. The methodology is based on three main steps: (i) we performed exhaustive physical-level simulations of basic blocks based on a detailed finite-element tool in order to have a full characterization, to know their properties in presence of defects, and to have a solid reference point for the following steps; (ii) we developed a model (fanomag) for the basic block behavior suitable for simulations in presence of defects of complex circuits, that is, lighter than a physical level one, but accurate enough to capture the most important features to be inherited at circuit level; (iii) starting from a physical design of complex circuits that we perform using a specific design tool we developed, that is, ToPoliNano, we simulated using fanomag, now embedded in our ToPoliNano tool, the behavior of circuits in presence of multiple sets of fabrication defects using a Monte Carlo approach now included in ToPoliNano as a new feature. In this paper, a specific type of defect is considered as a case study. The framework and methodology are conceived to be easily extended to handle other types of defects and problems due to working conditions that a designer and/or a technologist might want to focus on. The major outcome is then a powerful methodology and tool capable to analyze with a good accuracy nanomagnetic logic complex circuits and architectures both in ideal conditions and in presence of defects with remarkable performance in terms of simulation times. Copyright © 2016 John Wiley & Sons, Ltd.

Machine learning for mask/wafer hotspot detection and mask synthesis

Abstract: Machine learning is a powerful computer science technique that can derive knowledge from big data and make predictions/decisions. Since nanometer integrated circuits (IC) and manufacturing have extremely high complexity and gigantic data, there is great opportunity to apply and adapt various machine learning techniques in IC physical design and verification. This paper will first give an introduction to machine learning, and then discuss several applications, including mask/wafer hotspot detection, and machine learning-based optical proximity correction (OPC) and sub-resolution assist feature (SRAF) insertion. We will further discuss some challenges and research directions.

An Electromechanical Model and Simulation for Test Process of the Wafer Probe

Abstract: With the fast development of IC (integrated circuit) packaging industry, IC test is becoming more and more important, especially the probe test of the wafer packaging. Based on experimental data and theoretical analysis, an electromechanical model is first proposed to describe the characteristics of the testing process of wafer probe to understand the behavior of micro-probe testing process, and to simulate the whole physical process. The model consists of a dynamic mechanical model, a dc electro-mechanical coupling model and an ac impedance model, which is used to analyze the overall physical properties of the probe test process and has a good agreement with the experimental data. Based on the electromechanical model, a simulation platform is established first, which will provide a simulation tool for the design of the microprobe and setting of multiparameters.

Rsyn: An Extensible Physical Synthesis Framework

Abstract: Due to the advanced stage of development on EDA science, it has been increasingly difficult to implement realistic software infrastructures in academia so that new problems and solutions are tested in a meaningful and consistent way. In this paper we present Rsyn, a free and open-source C++ framework for physical synthesis research and development comprising an elegant netlist data model, analysis tools (e.g. timing analysis, congestion), optimization methods (e.g. placement, sizing, buffering) and a graphical user interface. It is designed to be very modular and incrementally extensible. New components can be easily integrated making Rsyn increasingly valuable as a framework to leverage research in physical design. Standard and third party components can be mixed together via code or script language to create a comprehensive design flow, which can be used to better assess the quality of results of the research being conducted. The netlist data model uses the new features of C++11 providing a simple but efficient way to traverse and modify the netlist. Attributes can be seamlessly added to objects and a notification system alerts components about changes in the netlist. The flexibility of the netlist inspired the name Rsyn, which comes from the word resynthesis. Rsyn is created to allow researchers to focus on what is really important to their research spending less time on the infrastructure development. Allowing the sharing and reusability of common components is also one of the main contributions of the Rsyn framework. In this paper, the key concepts of Rsyn are presented. Examples of use are drawn, the important standard components (e.g. physical layer, timing) are detailed and some case studies based on recent Electronic Design Automation (EDA) contests are analyzed. Rsyn is available at http://rsyn.design.

A Novel Heuristic Passive and Active Matching Circuit Design Method for Wireless Power Transfer to Moving Objects

Abstract: In this paper, a novel matching circuit design method utilizing a genetic algorithm (GA) and the measured S-parameters of randomly moved coil configurations is discussed. Through the detailed comparison of different matching circuit topologies, the superiority of active matching circuits is clearly demonstrated, and potentially there is 21.4% improvement in the wireless power transfer efficiency by using a four-cell active matching circuit, which can create 16 different impedance values. Also, the matching circuit design simulation can be further simplified by choosing a much smaller subset of representative impedance values for the utilized time-changing coil configuration through the employment of $k$ -means clustering and use only these values for the derivation of the optimal matching circuit. This heuristic approach could drastically reduce the time for the matching circuit design simulation, especially for matching circuit topologies with a larger number of cells.

Diagonal Component Expansion for Flow-Layer Placement of Flow-Based Microfluidic Biochips

Abstract: Continuous flow-based microfluidic devices have seen a huge increase in interest because of their ability to automate and miniaturize biochemistry and biological processes, as well as their promise of creating a programmable platform for chemical and biological experimentation. The major hurdle in the adoption of these types of devices is in the design, which is largely done by hand using tools such as AutoCAD or SolidWorks, which require immense domain knowledge and are hard to scale. This paper investigates the problem of automated physical design for continuous flow-based microfluidic very large scale integration (mVLSI) biochips, starting from a netlist specification of the flow layer. After an initial planar graph embedding, vertices in the netlist are expanded into two-dimensional components, followed by fluid channel routing. A new heuristic, DIagonal Component Expansion (DICE) is introduced for the component expansion step. Compared to a baseline expansion method, DICE improves area utilization by a factor of 8.90x and reduces average fluid routing channel length by 47.4%.

Physical Design Challenges and Innovations to Meet Power, Speed, and Area Scaling Trend

Abstract: In the advanced process technologies of 7nm and beyond, the semiconductor industry faces several new challenges: (1) aggressive chip area scaling with economically feasible process technology development, (2) sufficient performance enhancement of advanced small-scale technology with significantly increased wire and via resistances, (3) power density sustainability with ever shrinking chip area, and (4) advanced chip packaging integration solutions for complex SOC systems. In this presentation, novel physical design solutions of robust IP and design methodologies will be explored to solve these challenges. These innovations are made possible by the co-optimization of process technology, IP design and design flow automation. Density scaling is the most important indicator in the continuation of Moore's law. Before 10nm, chip area reduction is mainly achieved by fundamentally shrinking transistor and metal dimensions. Starting from 7nm, maintaining sufficient and economical scaling is hard to achieve through dimension decrease alone. We present two cost-effective enablers, FIN depopulation and EUV, along with their associated innovative standard cell structures and physical design flows, to realize additional area reduction beyond process dimension scaling. Achieving high performance is always a key index for CPU designs. However, the resistance of interconnects has grown significantly as the dimensions of wires and vias are scaled aggressively. We present novel physical design solutions of the via pillar approach using metal layer promotion and multiple-width configurable wires. This fully automated via pillar design flow mitigates the high resistance impact and becomes indispensable in high performance designs for advanced process technologies. Maintaining power densities while aggressively shrinking chip areas is also a critical requirement, especially for mobile and IoT applications. Lowering supply voltages is one of the most effective means to reducing power consumption, especially for FinFET devices with much lower threshold voltages than planar devices. However, process and timing variation is high even for FinFET devices operating at very low voltages. We present robust ultra-low voltage IP design solutions and the current status and issues of non-Gaussian and asymmetric variation modeling for ultra-low voltage timing signoffs. Finally, advanced chip packaging is presented as a viable solution for integration and system level scaling for complex SOC systems. Specific packaging solutions can meet different requirements of system die and package size, form factor, bandwidth, power and homogeneous or heterogeneous integration. For a silicon-proven system, quantitative advantages of advanced packaging over traditional packaging in silicon thickness, thermal dissipation and voltage drop are presented. Chip packaging integration flow and requirements will also be discussed.

Trading Accuracy for Energy in Stochastic Circuit Design

Abstract: As we approach the limits of traditional Moore’s-Law scaling, alternative computing techniques that consume energy more efficiently become attractive. Stochastic computing (SC), as a re-emerging computing technique, is a low-cost and error-tolerant alternative to conventional binary circuits in several important applications such as image processing and communications. SC allows a natural accuracy-energy tradeoff that has been exploited in the past. This article presents an accuracy-energy tradeoff technique for SC circuits that reduces their energy consumption with virtually no accuracy loss. To this end, we employ voltage or frequency scaling, which normally reduce energy consumption at the cost of timing errors. Then we show that due to their inherent error tolerance, SC circuits operate satisfactorily without significant accuracy loss even with aggressive scaling. This significantly improves their energy efficiency. In contrast, conventional binary circuits quickly fail as the supply voltage decreases. To find the most energy-efficient operating point of an SC circuit, we propose an error estimation method that allows us to quickly explore the circuit’s design space. The error estimation method is based on Markov chain and least-squares regression. Furthermore, we investigate opportunities to optimize SC circuits under such aggressive scaling. We find that logical and physical design techniques can be combined to significantly expand the already-powerful accuracy-energy tradeoff possibilities of SC. In particular, we demonstrate that careful adjustment of path delays can lead to significant error reduction under voltage and frequency scaling. We perform buffer insertion and route detouring to achieve more balanced path delays. These techniques differ from conventional path-balancing techniques whose goal is to minimize power consumption by resizing the non-critical paths. The goal of our path-balancing approach is to increase error cancellation chances in voltage-/frequency-scaled SC circuits. Our circuit optimization comprehends the tradeoff between power overheads due to inserted buffers and wires versus the energy reduction from supply voltage downscaling enabled by more balanced path delays. Simulation results show that our optimized SC circuits can tolerate aggressive voltage scaling with no significant signal-to-noise ratio (SNR) degradation. In one example, a 40% supply voltage reduction (1V to 0.6V) on the SC circuit leads to 66% energy saving (20.7pJ to 6.9pJ) and makes it more efficient than its conventional binary counterpart. In the same example, a 100% frequency boosting (400ps to 200ps) of the optimized circuits leads to no significant SNR degradation. We also show that process variation and temperature variation have limited impact on optimized SC circuits. The error change is less than 5% when temperature changes by 100°C or process condition changes from worst case to best case.

An Introduction to CAD for VLSI

Abstract: The last decade has seen an explosion in integrated circuit technology. Improved manufacturing processes have led to ever smaller device sizes. Chips with over a hundred thousand transistors have become common and performance has improved dramatically. Alongside this explosion in manufacturing technology has been a much-less-heralded explosion of design tool capability that has enabled designers to build those large, complex devices. The tools have allowed designers to build chips in less time, reducing the cost and risk. Without the design tools, we would not now be seeing the full benefits of the advanced manufacturing technology. The Scope of This Book This book describes the implementation of several tools that are commonly used to design integrated circuits. The tools are the most common ones used for computer aided design and represent the mainstay of design tools in use in the industry today. This book describes proven techniques. It is not a survey of the newest and most exotic design tools, but rather an introduction to the most common, most heavily-used tools. It does not describe how to use computer aided design tools, but rather how to write them. It is a view behind the screen, describing data structures, algorithms and code organization. This book covers a broad range of design tools for Computer Aided Design (CAD) and Computer Aided Engineering (CAE). The focus of the discussion is on tools for transistor-level physical design and analysis.

Impact and Design Guideline of Monolithic 3-D IC at the 7-nm Technology Node

Abstract: Monolithic 3-D (M3D) IC is one of the potential technologies to break through the challenges of continued circuit power and performance scaling. In this paper, for the first time, we demonstrate the power benefits of M3D and present design guideline in a 7-nm FinFET technology node. The predictive 7-nm process design kit (PDK) and the standard cell library using both high-performance (HP) and low-standby-power (LSTP) device technologies are developed based on NanGate 45-nm PDK using accurate dimensional, material, and electrical parameters from publications and a commercial-grade tool flow. We implement full-chip M3D designs utilizing industry-standard physical design tools, and gauge the impact of M3D technology on performance, power, and area metrics. We also provide the design guidelines as well as a new partitioning methodology to improve M3D design quality. This paper shows that M3D designs outperform 2-D counterparts by 16% and 16.5% on average in terms of isoperformance total power reduction with 7-nm HP and LSTP cell library, respectively. This demonstrates the power benefits of M3D technology in both HP and low-power future generation devices.

A physically based scalable SPICE model for silicon carbide power MOSFETs

Abstract: This paper proposes a novel physical and scalable SPICE model for Silicon Carbide (SiC) power MOSFETs The model is based on process and layout parameters, enabling design optimization through a direct link between SPICE, physical design, and process technology One model applies to the entire technology instead of conventional discrete models for each device size and process variation The SPICE agnostic model ports across multiple industry standard simulation platforms The model has been validated with On Semiconductor's advanced 1200V SiC MOSFET technology

A learning bridge from architectural synthesis to physical design for exploring power efficient high-performance adders

Abstract: In spite of maturity to the modern electronic design automation (EDA) tools, optimized designs at architectural stage may become sub-optimal after going through physical design flow. Adder design has been such a long studied fundamental problem in VLSI industry yet designers cannot achieve optimal solutions by running EDA tools on the set of available prefix adder architectures. In this paper, we enhance a state-of-the-art prefix adder synthesis algorithm to obtain a much wider solution space in architectural domain. On top of that, a machine learning based design space exploration methodology is applied to predict the Pareto frontier of the adders in physical domain, which is infeasible by exhaustively running EDA tools for innumerable architectural solutions. Experimental results demonstrate that our framework can achieve near-optimal delay vs. power/area Pareto frontier over a wide design space, bridging the gap between architectural and physical designs.

The comparative analysis of modelling of simscape physical plant system design and armature-controlled system design of DC motor

Abstract: In many fields of science, technology and production uses fast processes, high-speed devices, higher modes and interaction among different objects and materials. In this regard, there is the problem of developing fast actuators that could support and implement high speed movement of the various actuators. DC motors are widely used in industry, transportation, robotic control system and other applications that require a broad and smooth speed control (rolling mills, powerful machine tools, electric traction in transport, etc.). Nowadays stability and accuracy are required for the automatic control system. This paper presents a DC motor speed controlling system under load conditions and with Torque-variation is designed using PID controller. A MATLAB/SIMULINK platform is used to observe the system response of the DC motor with no-load and full-load conditions. On the other hand, the physical design requires that a mechanical system and its control system should be designed as an integrated system. So, this paper discusses how MATLAB and SIMULINK can be operated to ensure the PID control of a mechatronic system design and Armature-Controlled system.

Synchoricity and NOCs could make Billion Gate Custom Hardware Centric SOCs Affordable

Abstract: In this paper, we present a novel synchoros VLSI design scheme that discretizes space uniformly. Synchoros derives from the Greek word choros for space. We propose raising the physical design abstraction to register transfer level by using coarse grain reconfigurable building blocks called SiLago blocks. SiLago blocks are hardened, synchoros and are used to create arbitrarily complex VLSI design instances by abutting them and not requiring any further logic and physical syntheses. SiLago blocks are interconnected by two levels of NOCs, regional and global. By configuring the SiLago blocks and the two levels of NOCs, it is possible to create implementation alternatives whose cost metrics can be evaluated with agility and post layout accuracy. This framework, called the SiLago framework includes a synthesis based design flow that allows end to end automation of multi-million gate functionality modeled as SDF in Simulink to be transformed into timing and DRC clean physical design in minutes, while exploring 100s of solutions. We benchmark the synthesis efficiency, and silicon and computational efficiencies against the conventional standard cell based tooling to show two orders improvement in accuracy and three orders improvement in synthesis while eliminating the need to verify at lower abstractions like RTL. The proposed solution is being extended to deal with system-level non-compile time functionalities. We also present arguments on how synchoricity could also contribute to eliminating the engineering cost of designing masks to lower the manufacturing cost.