Showing papers on "Physical design published in 2018"

Machine Learning Applications in Physical Design: Recent Results and Directions

Abstract: In the late-CMOS era, semiconductor and electronics companies face severe product schedule and other competitive pressures. In this context, electronic design automation (EDA) must deliver "design-based equivalent scaling" to help continue essential industry trajectories. A powerful lever for this will be the use of machine learning techniques, both inside and "around" design tools and flows. This paper reviews opportunities for machine learning with a focus on IC physical implementation. Example applications include (1) removing unnecessary design and modeling margins through correlation mechanisms, (2) achieving faster design convergence through predictors of downstream flow outcomes that comprehend both tools and design instances, and (3) corollaries such as optimizing the usage of design resources licenses and available schedule. The paper concludes with open challenges for machine learning in IC physical design.

UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing

Abstract: Field programmable gate array (FPGA) packing and placement without routability consideration could lead to unroutable results for high-utilization designs. Conventional FPGA packing and placement approaches are shown to have severe difficulties to yield good routability. In this paper, we propose an FPGA packing and placement engine called UTPlaceF that simultaneously optimizes wirelength and routability. A novel physical and congestion aware packing algorithm and a hierarchical detailed placement technique are proposed. UTPlaceF outperforms state-of-the-art FPGA placers simultaneously in runtime and solution quality on International Symposium on Physical Design (ISPD) 2016 benchmark suite. Compared with the top three winners of ISPD’16 FPGA placement contest, UTPlaceF can deliver 6.2%, 11.6%, and 29.1% better routed wirelength with shorter runtime.

Compact-2D: A Physical Design Methodology to Build Commercial-Quality Face-to-Face-Bonded 3D ICs

Abstract: The recent advancement of wafer bonding technology offers fine-grained and silicon-space overhead-free 3D interconnections in face-to-face (F2F) bonded 3D ICs. In this paper, we propose a full-chip RTL-to-GDSII physical design solution to build high-density and commercial-quality two-tier F2F-bonded 3D ICs. The state-of-the-art flow named Shrunk-2D (S2D) requires shrinking of standard cells and interconnects by a factor of 50% to fit into the target 3D footprint of a two-tier design. This, unfortunately, necessitates commercial place/route engines that handle one node smaller geometries, which can be challenging and costly. Our flow named Compact-2D (C2D) does not require any geometry shrinking. Instead, C2D implements a 2D IC with scaled interconnect RC parasitics, and contracts the layout to the F2F design footprint. In addition, C2D offers post-tier-partitioning optimization that is shown to be effective in fixing timing violations caused by inter-tier 3D routing, which is completely missing in S2D. Lastly, we present a methodology to recycle the routing result of post-tier-partitioning optimization for final GDSII generation. Our experimental results show that at iso-performance, C2D offers up to 26.8% power reduction and 15.6% silicon area savings over commercial 2D ICs without any routing resource overhead.

The Cat and Mouse in Split Manufacturing

Abstract: Split manufacturing of integrated circuits eliminates vulnerabilities introduced by an untrusted foundry by manufacturing only a part of the target design at an untrusted high-end foundry and the remaining part at a trusted low-end foundry. Most researchers have focused on attack and defenses for hierarchical designs and/or use a relatively high-end trusted foundry, leading to high cost. We propose an attack and defense for split manufacturing for flattened designs. Our attack uses a network-flow model and outperforms previous attacks. We also develop two defense techniques using placement perturbation—one using physical design information and the other using logical information—while considering overhead. The effectiveness of our techniques is demonstrated on benchmark circuits.

Computational Bounds For Photonic Design

Abstract: Physical design problems, such as photonic inverse design, are typically solved using local optimization methods. These methods often produce what appear to be good or very good designs when compared to classical design methods, but it is not known how far from optimal such designs really are. We address this issue by developing methods for computing a bound on the true optimal value of a physical design problem; physical designs with objective smaller than our bound are impossible to achieve. Our bound is based on Lagrange duality and exploits the special mathematical structure of these physical design problems. For a multi-mode 2D Helmholtz resonator, numerical examples show that the bounds we compute are often close to the objective values obtained using local optimization methods, which reveals that the designs are not only good, but in fact nearly optimal. Our computational bounding method also produces, as a by-product, a reasonable starting point for local optimization methods.

MIP model and elitist strategy hybrid GA–SA algorithm for layout design

Abstract: It is most important for any manufacturing industry to have an efficient layout for their production environment to participate in global competition. One of the prime objectives of such an organisation is to decide an optimal arrangement of their facilities (machines or departments) in a two-dimensional planar region satisfying desired objectives, which is termed facility layout problem. To overcome the drawbacks of traditional layout design methodology, it is attempted to solve three important layout design problems such as inter-cell layout design, determination of optimum location for input/output stations and flow path layout design of material handling system simultaneously in an integrated manner. The quality of the final layout is evaluated by minimizing the total material handling cost, where the perimeter distance metric is used for the distance measurement. Sequence-pair, an elegant representation technique is used for layout encoding. The translation from sequence-pair to layout is efficiently done by longest common subsequence computation methodology. Due to the non-polynomial hard nature of the problem considered, an elitist strategy based hybrid genetic algorithm that uses simulated annealing as local search mechanism (ESHGA) is developed and tested with test problem instances available in the literature. The results indicate that proposed integrated methodology with developed mixed integer programming based mathematical model along with ESHGA could generate realistic layouts compared to reported result.

DFARPA: Differential fault attack resistant physical design automation

Abstract: Differential Fault Analysis (DFA), aided by sophisticated mathematical analysis techniques for ciphers and precise fault injection methodologies, has become a potent threat to cryptographic implementations. In this paper, we propose, to the best of the our knowledge, the first “DFA-aware” physical design automation methodology, that effectively mitigates the threat posed by DFA. We first develop a novel floorplan heuristic, which resists the simultaneous corruption of cipher states necessary for successful fault attack, by exploiting the fact that most fault injections are localized in practice. Our technique results in the computational complexity of the fault attack to shoot up to exhaustive search levels, making them practically infeasible. In the second part of the work, we develop a routing mechanism, which tackles more precise and costly fault injection techniques, like laser and electromagnetic guns. We propose a routing technique by integrating a specially designed ring oscillator based sensor circuit around the potential fault attack targets without incurring any performance overhead. We demonstrate the effectiveness of our technique by applying it on state of the art ciphers.

A fast thermal-aware fixed-outline floorplanning methodology based on analytical models

Abstract: High temperature or temperature non-uniformity have become a serious threat to performance and reliability of high-performance integrated circuits (ICs). Thermal effect becomes a non-ignorable issue to circuit design or physical design. To estimate temperature accurately, the locations of modules have to be determined, which makes an efficient and effective thermal-aware floorplanning play a more important role. To resolve this problem, this paper proposes a differential nonlinear model which can approximate temperature and minimize wirelength at the same time during floorplanning. We also apply some techniques such a thermal-aware clustering or shrinking hot modules in the multi-level framework to further reduce temperature without inducing longer wirelength. The experimental results demonstrate that temperature and wirelength are greatly improved in our method compared to other works. More importantly, our runtime is quite fast and the fixed-outline constraint is also satisfied.

End-to-End Industrial Study of Retiming

Abstract: Sequential circuits are combinational circuits that are separated by registers. Retiming is considered as the most promising technique for optimizing sequential circuits, that involves moving the edge-triggered registers across the combinational logic without changing the functionality. Despite significant efforts spent on sequential optimization since 1980's, there are few works? discussed its performance in an end-to-end design flow. The retiming algorithms were mostly evaluated at the logic level. However, it turns out that the retiming results at logic level could be significantly different than evaluating the physical level. This paper provides the findings of how retiming algorithms perform in an end-to-end industrial design flow, with seven industry designs taken from a recent 14nm microprocessor. Experiments are conducted with several complete industrial design flows. The evaluations are made at the end of the physical design flow. The experimental results show that the performance (design quality) of the retiming algorithms vary on the designs. Based these experimental results, we discover a feature that describes the retiming potentials of sequential designs. This model successfully forecast whether the given industrial designs could be significantly improved by retiming in an end-to-end design flow, regarding timing, area, and power.

Simultaneous partitioning and signals grouping for time-division multiplexing in 2.5D FPGA-based systems

Abstract: The 2.5D FPGA is a promising technology to accommodate a large design in one FPGA chip, but the limited number of inter-die connections in a 2.5D FPGA may cause routing failures. To resolve the failures, input/output time-division multiplexing is adopted by grouping cross-die signals to go through one routing channel with a timing penalty after netlist partitioning. However, grouping signals after partitioning might lead to a suboptimal solution. Consequently, it is desirable to consider simultaneous partitioning and signal grouping although the optimization objectives of partitioning and grouping are different, and the time complexity of such simultaneous optimization is usually high. In this paper, we propose a simultaneous partitioning and grouping algorithm that can not only integrate the two objectives smoothly, but also reduce the time complexity to linear time per partitioning iteration. Experimental results show that our proposed algorithm outperforms the state-of-the-arts flow in both cross-die signal timing criticality and system-clock periods.

Flexibility: FPGAs and CAD in Deep Learning Acceleration

Abstract: Deep learning inference has become the key workload to accelerate in our AI-powered world. FPGAs are an ideal platform for the acceleration of deep learning inference by combining low-latency performance, power-efficiency, and flexibility. This paper examines the flexibility aspect, and its impact on FPGA design methodology, physical design tools and CAD. We describe the degrees of flexibility required for creating efficient deep learning accelerators. We quantify the varying effects of precision, vectorization, and buffering on both performance and accuracy, and show how the FPGA can yield superior performance through architecture customization tuned for a specific neural network. We describe the need for abstraction and propose solutions in modern FPGA design flows to enable the rapid creation of these customized accelerator architectures for deep learning inference acceleration. Finally, we examine the implications on physical design tools and CAD.

The Pressing Need for Electromigration-Aware Physical Design

Abstract: Electromigration (EM) is becoming a progressively intractable design challenge due to increased interconnect current densities. It has changed from something designers "should" think about to something they "must" think about, i.e., it is now a definite requirement. The on-going IC-down-scaling is producing physical designs with ever-smaller feature sizes, which can easily lead to current densities that exceed their maximum allowable values. This invited talk introduces the fundamentals of EM, its interactions with thermal and stress migration, and presents appropriate modelling and simulation methodologies. Following a summary of EM-inhibiting effects in physical design, we propose ways of facilitating EM-compliant layout design in future technology nodes.

DATC RDF: an academic flow from logic synthesis to detailed routing

Abstract: In this paper, we present DATC Robust Design Flow (RDF) from logic synthesis to detailed routing. We further include detailed placement and detailed routing tools based on recent EDA research contests. We also demonstrate RDF in a scalable cloud infrastructure. Design methodology and cross-stage optimization research can be conducted via RDF.

Design automation methodology and tools for superconductive electronics

Abstract: Josephson junction-based superconducting logic families have been proposed to implement analog and digital signals, which can achieve low energy dissipation and ultra-fast switching speed. There are two representative technologies: DC-biased RSFQ (rapid single flux quantum) technology and its variants that achieve a verified speed of 370 Ghz, and AC-biased AQFP (adiabatic quantum-flux-parametron) that achieves an energy dissipation near quantum limits. Despite extraordinary characteristics of the superconducting logic families, many technical challenges remain, including the choice of circuit fabrics and architectures that utilize the SFQ technology and the development of effective design automation methodologies and tools. This paper presents our work on developing design flows and tools for DC- and AC-biased SFQ circuits, leveraging unique characteristics and design requirements of the SFQ logic families. More precisely, physical design algorithms, including placement, clock tree routing, and signal routing algorithms targeting RSFQ circuits are presented first. Next, a majority/minority gate-based automatic synthesis framework targeting AQFP logic circuits is described. Finally, experimental results to demonstrate the efficacy of the proposed framework and tools are presented.

Power, Performance and Area Optimization of I/O Design

Abstract: The VLSI (Very Large Scale Integration) industry has been growing constantly obeying Moores law to an extent where multiple processors can be implemented on a single chip. Yet, the development is unable to keep up with the demands and challenges faced by the growth of device capacity in terms of VLSI design without sacrificing the quality. There is a need to produce an efficient placement solution that can address high quality placement. This paper investigates physical design methodologies for synthesizing and optimization of design in terms of power, performance and area by completing the ASIC (application-specific integrated circuit) design flow using advance industry level tools.

Electromigration- and Parasitic-Aware ILP-Based Analog Router

Abstract: Interconnect and via failures due to the electromigration (EM) effect have become increasingly challenging in the advanced technology as a result of shrinking feature size. The parasitic effect, which has to be normally represented as analog and radio frequency (RF) circuit constraints for effective suppression in practice, has also made the modern physical design more intractable. In this paper, we present a new integer-linear-programming-based EM-aware and sensitivity-aware analog/RF router, which can effectively address the EM constraints as well as interconnect parasitics and matching constraints along the routing paths. Interconnect parasitics can be evaluated in the sensitivity analysis so that an appropriate width can be adopted for each subnet in order to gain better circuit performance. Any mismatch can be also minimized between ideally matching nets whenever the primitive methods fail to find exactly matched routes for these sensitive nets. By using our proposed routing methodology, the EM constraints are taken into account to guarantee a final EM-compliant routing solution. The experimental results show that our proposed method is able to produce better circuit performance compared to the previous works while EM can be seriously addressed for analog/RF circuits.

A Novel Implementation of Ternary Decoder Using CMOS DPL Binary Gates

Abstract: This paper proposes a novel implementation of Ternary Decoder using CMOS DPL (Double Pass Logic) Binary logic gates, in digital CMOS technology. The physical design of the circuits is simulated and tested with Micro-Cap 10 SPICE simulator. The Proposed Ternary Decoder circuit can be used in VLSI design. The Proposed decoder circuit will be the basic circuit to create other Ternary Logic Circuits like Ternary Logic Gates, Ternary Memory, Adder, Multiplier, Multiplexer, and others. The simulation results demonstrate the merits of the approach in terms of reduced number of transistors by 25% compared to the existing ternary decoder.

Increasing EM Robustness of Placement and Routing Solutions based on Layout-Driven Discretization

Abstract: Nowadays, electromigration (EM) is mainly addressed in the verification step. This is no longer possible due to the ever increasing number of EM failures in the future. An EM-aware physical synthesis could reduce the number of critical locations but the layout complexities prevent this from already being used. To solve this problem, we propose a novel method to discretize placement and routing solutions to enable a fast EM analysis. In addition, we suggest adjustments in the placement and routing step to enhance the EM robustness based on early analysis results. In contrast to the standard approach of running a numerical simulation outside the physical design step and after the synthesis, we perform most of the analysis steps within our placement and routing tools to consider the results; thus enabling early and specialized EM-robust solutions. Particularly, our methodology exploits layout structures to enable an efficient discretization inside the geometrical representations of synthesis tools. We demonstrate how to reduce the discretization effort significantly while achieving sufficient accuracy to improve EM robustness.

IBM z14: enabling physical design in 14-nm technology for high-performance, high-reliability microprocessors

Abstract: The IBM z14 design was built with the 14-nm high-performance silicon-on-insulator (SOI) technology of GLOBALFOUNDRIES. This was the first technology node after IBM transitioned from its integrated fabrication facility to operating in a fabless environment, driving significant changes to design processes and methodology. In addition to this partnership, the 14-nm technology introduced significant changes relative to previous technology nodes, including the introduction of fin-shaped field-effect transistors, the use of double patterning for the lowest back-end-of-line layers, and the introduction of middle-of-line layers to exploit contact layers for local interconnects. This combination of technical and business challenges required numerous large-scale innovations for our design, design team, and design methodologies. In this paper, we provide a survey of these innovations, including the fin-based standard cell image, deeply scaled SOI self-heating/electromigration verification, routing strategies to handle double-patterning with interlayer via awareness, fill automation to enable simultaneous design of multiple layers of hierarchy, and high-performance array design with the voltage and noise limitations of the 14-nm technology node.

The need and opportunities of electromigration-aware integrated circuit design

Abstract: Electromigration (EM) is becoming a progressively severe reliability challenge due to increased interconnect current densities. A shift from traditional (post-layout) EM verification to robust (pro-active) EM-aware design - where the circuit layout is designed with individual EM-robust solutions - is urgently needed. This tutorial will give an overview of EM and its effects on the reliability of present and future integrated circuits (ICs). We introduce the physical EM process and present its specific characteristics that can be affected during physical design. Examples of EM countermeasures which are applied in today's commercial design flows are presented. We show how to improve the EM-robustness of metallization patterns and we also consider mission profiles to obtain application-oriented current-density limits. The increasing interaction of EM with thermal migration is investigated as well. We conclude with a discussion of application examples to shift from the current post-layout EM verification towards an EM-aware physical design process. Its methodologies, such as EM-aware routing, increase the EM-robustness of the layout with the overall goal of reducing the negative impact of EM on the circuit's reliability.

Macro-aware row-style power delivery network design for better routability

Abstract: Reliability of a P/G network is one of the most important concerns in a chip design, which makes powerplanning the most critical step in the physical design. Traditional P/G network design mainly focuses on reducing usage of routing resource to satisfy voltage drop and electromigration constraints according to a regular mesh. As the number of macros in a modern design increases, this style may waste more routing resource and make routing congestion more severe in local regions. In order to save routing resource and increase routability, this paper proposes a delicate powerplanning method. First, we propose a row-style power mesh to facilitate connection of pre-placed macros and increase routability of signal nets in the later stage. Besides, an effective power stripe width which can reduce wastage of routing resource and provide stronger supply voltage is found. Moreover, we propose the first work to use the linear programming algorithm to minimize P/G routing area and consider routability at the same time. The experimental results show that routability of a design with many macros can be significantly improved by our row-style power networks.

Usage and impact of multi-bit flip-flops low power methodology on physical implementation

Abstract: Multi-Bit flip-flops (MBFF) usage is an innovative technique introduced in Integrated Circuit (IC) design as one of the low power methodologies that reduce the area and the power consumption during the design phase and physical synthesis. Recently this approach is introduced in the physical implementation to help for more power reduction. In this paper, we will present the MBFF merging challenges in the physical design process, then we will recommend the optimal stage to perform the flip-flops merging, within the Pre-CTS (Clock-tree Synthesis) step. The success criteria is to achieve the highest MBFF percentage without degrading the circuit performance. The experiments on a high-speed design, made with 7nm technology node, shows that the best stage for the MBFF merging is after the final detailed placement and timing optimization. The percentage of multi-bit flip-flop cells compared to all flip-flop cells achieved is 75.8% with a no performance degradation.

Interconnect Design and Technology Optimization for Conventional and Emerging Nanoscale Devices: A Physical Design Perspective

Abstract: Interconnect parasitics severely limit the performance and power dissipation in modern circuits at the advanced process technology nodes. Hence, device-level advances must be complemented with appropriate interconnect technology and design innovations for effective enablement at the circuit and system levels. This paper highlights the impact of device technologies on the optimal interconnect design and circuit-level metrics. The FinFET and Tunnel-FETs are studied by building fully placed-and-routed physical designs. The impact of device and interconnect technology co-optimization on circuit performance, power, and variability is shown for a range of emerging devices.

Cross-layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach

Abstract: In spite of maturity to the modern electronic design automation (EDA) tools, optimized designs at architectural stage may become sub-optimal after going through physical design flow. Adder design has been such a long studied fundamental problem in VLSI industry yet designers cannot achieve optimal solutions by running EDA tools on the set of available prefix adder architectures. In this paper, we enhance a state-of-the-art prefix adder synthesis algorithm to obtain a much wider solution space in architectural domain. On top of that, a machine learning-based design space exploration methodology is applied to predict the Pareto frontier of the adders in physical domain, which is infeasible by exhaustively running EDA tools for innumerable architectural solutions. Considering the high cost of obtaining the true values for learning, an active learning algorithm is utilized to select the representative data during learning process, which uses less labeled data while achieving better quality of Pareto frontier. Experimental results demonstrate that our framework can achieve Pareto frontier of high quality over a wide design space, bridging the gap between architectural and physical designs.

A Logic Test Chip for Optimal Test and Diagnosis

Abstract: The benefits of the continued progress in integrated circuit manufacturing have been numerous, most notably in the explosion of computing power in devices ranging from cell phones to cars. Key to this success has been strategies to identify, manage, and mitigate yield loss. One such strategy is the use of test structures to identify sources of yield loss early in the development of a new manufacturing process. However, the aggressive scaling of feature dimensions, the integration of new materials, and the increase in structural complexity in modern technologies has challenged the capabilities of conventional test structures. To help address these challenges, a new logic test chip, called the Carnegie Mellon Logic Characterization Vehicle (CM-LCV), has been developed. The CM-LCV utilizes a two- dimensional array of functional unit blocks (FUBs) that each implement an innovative functionality. Properties including fault coverage, logical and physical design features, and fault distinguishability are shown to be composable within the FUB array; that is, they exist regardless of the size and composition of the FUB array. A synthesis ow that leverages this composability to adapt the FUB array to a wide range of test chip design requirements is presented. The connection between the innovative FUB functionality and orthogonal Latin squares is identified and used to analyze the universe of possible FUB functions. Two additional variants to the FUB array are also developed: heterogenous FUB arrays utilize multiple FUB functions to improve the synthesis ow performance, while pipelined FUB arrays incorporate sequential circuit elements (e.g., ip- ops and latches) that are absent from the original combinational FUB array. In addition to the design of the CM-LCV, methods for testing it are presented. Techniques to create minimal sets of test patterns that exhaustively exercise each FUB within the FUB array are developed. Additional constraints are described for the heterogenous and pipelined FUB arrays that allow these techniques to be applied for both variant FUB arrays. Furthermore, a simple built-in self test (BIST) scheme is described and applied to a reference design, resulting in a 88.0% reduction in the number of test cycles required without loss in fault coverage. A hierarchical FUB array diagnosis methodology (HFAD) is also presented for the CM- LCV that leverages its unique properties to improve performance for multiple defects. Experiments demonstrate that this HFAD methodology is capable of perfect accuracy in 93.1% of simulations with two injected faults, an improvement on the state-of-the-art commercial diagnosis. Additionally, silicon fail data was collected from a CM-LCV manufactured using a 14nm process by an industry partner. A comparison of the diagnosis results for the 1,375 fail logs examined shows that the HFAD methodology discovers additional defects during multiple defect diagnosis that the commercial tool misses for 40 of the diagnosed fail logs. Examination of these cases shows that the additional defects found by the HFAD methodology can result in improved diagnosis confidence and more precise descriptions of the defect behavior(s). The contributions of this dissertation can thus be summarized as the description of the design, test, and diagnosis of a new logic test chip for use in yield learning during process development. This CM-LCV can be adapted to meet a wide range of test chip requirements, can be efficiently and rigorously tested, and exhibits properties that can be used to improve diagnosis outcomes. All of these claims are validated through both simulated experiments and silicon data.

Design Rule Violation Hotspot Prediction Based on Neural Network Ensembles

Abstract: Design rule check is a critical step in the physical design of integrated circuits to ensure manufacturability. However, it can be done only after a time-consuming detailed routing procedure, which adds drastically to the time of design iterations. With advanced technology nodes, the outcomes of global routing and detailed routing become less correlated, which adds to the difficulty of predicting design rule violations from earlier stages. In this paper, a framework based on neural network ensembles is proposed to predict design rule violation hotspots using information from placement and global routing. A soft voting structure and a PCA-based subset selection scheme are developed on top of a baseline neural network from a recent work. Experimental results show that the proposed architecture achieves significant improvement in model performance compared to the baseline case. For half of test cases, the performance is even better than random forest, a commonly-used ensemble learning model.

Geometric Programming-Based Automation of Floorplanning in ASIC Physical Design

Abstract: The ASIC physical design process is a complex optimization problem with various objectives such as minimum chip minimum wire length, area, minimum of vias The main aims of optimization are to improve the performance and reliability etc, of the ASIC design process The objectives mentioned can be achieved through the effective implementation of floorplanning before other steps are implemented In this study, a pseudo code is developed for floorplanning using geometric programming to achieve global optima This study uses simulations performed using MATLAB GGP toolbox

Research and Design of Class D Amplifier at 1 MHz

Abstract: This paper is mainly for the study of current mode Class-D(CMCD) power amplifier at 1MHz operating frequency. The article mainly focuses on the influence of the driving circuit of the power MOSFET on the Class-D amplifier at high frequency, the parameter calculation in the power amplifier circuit and the parameters of the output transformer. The calculations are discussed in three aspects. In addition, the article discusses the Class-D materials used in the circuit. The article realizes the development of a current-type Class-D amplifier based on the efficiency value of nearly 80% at the operating frequency of 1MHz, and it builds a specific circuit for physical design and verification.