Showing papers on "Physical design published in 2022"

Perimeter Degree Technique for the Reduction of Routing Congestion during Placement in Physical Design of VLSI Circuits

Abstract: When used in conjunction with the current floorplan and the optimization technique in circuit design engineering, this research allows for the evaluation of design parameters that can be used to reduce congestion during integrated circuit fabrication. Testing the multiple alternative consequences of IC design will be extremely beneficial in this situation, as will be demonstrated further below. If the importance of placement and routing congestion concerns is underappreciated, the IC implementation may experience significant nonlinear problems throughout the process as a result of the underappreciation of placement and routing congestion concerns. The use of standard optimization techniques in integrated circuit design is not the most effective strategy when it comes to precisely estimating nonlinear aspects in the design of integrated circuits. To this end, advanced tools such as Xilinx VIVADO and the ICC2 have been developed, in addition to the ICC1 and VIRTUOSO, to explore for computations and recover the actual parameters that are required to design optimal placement and routing for well-organized and ordered physical design. Furthermore, this work employs the perimeter degree technique (PDT) to measure routing congestion in both horizontal and vertical directions for a silicon chip region and then applies the technique to lower the density of superfluous routing (DSR) (PDT). Recently, a metaheuristic approach to computation has increased in favor, particularly in the last two decades. It is a classic graph theory problem, and it is also a common topic in the field of optimization. However, it does not provide correct information about where and how nodes should be put, despite its popularity. Consequently, in conjunction with the optimized floorplan data, the optimized model created by the Improved Harmonic Search Optimization algorithm undergoes testing and investigation in order to estimate the amount of congestion that occurs during the routing process in VLSI circuit design and to minimize the amount of congestion that occurs.

Survey of Machine Learning for Electronic Design Automation

Abstract: An increase in demand for semiconductor ICs, recent advancements in machine learning, and the slowing down of Moore's law have all contributed to the increased interest in using Machine Learning (ML) to enhance Electronic Design Automation (EDA) and Computer-Aided Design (CAD) tools and processes. This paper provides a comprehensive survey of available EDA and CAD tools, methods, processes, and techniques for Integrated Circuits (ICs) that use machine learning algorithms. The ML-based EDA/CAD tools are classified based on the IC design steps. They are utilized in Synthesis, Physical Design (Floorplanning, Placement, Clock Tree Synthesis, Routing), IR drop analysis, Static Timing Analysis (STA), Design for Test (DFT), Power Delivery Network analysis, and Sign-off. The current landscape of ML-based VLSI-CAD tools, current trends, and future perspectives of ML in VLSI-CAD are also discussed.

Application of Phase-Based Circuit Theory to RSFQ Logic Design

Abstract: In contrast to transistor-based semiconductor circuits, there is currently no widely accepted formalized circuit theory or design methodology for superconductor rapid single flux quantum (RSFQ) logic circuits. Experienced designers intuitively consider flux loops, nodal phase, and branch currents when making design choices, but the lack of a formalized design process makes it difficult for inexperienced RSFQ circuit designers to construct a functioning logic cell without a reference. This results in new circuit designers, mostly recycling templates from published circuit designs without fully understanding why the circuits function as they do. Inexperienced RSFQ circuit designers often follow an iterative process where cell parameter values are adjusted, and the cell is run through electronic simulation engines until the desired functionality is reached. We propose the development of a formalized circuit design theory for RSFQ logic from first principles using phase-based circuit analysis. The circuit is designed using dc analysis to establish the dc operating point of the circuit. Phase-based analysis and simulation are then used to verify the dynamic circuit functionality. To demonstrate this method, we discuss examples for well-known RSFQ cells. We analyze the initial operating margins of these designs and discuss design accuracy and efficiency. Methods for current regulation to minimize current leakage between cells are discussed. We also present how this design methodology can be used to design new circuits such as an RSFQ XNOR cell. We investigate how an inverting (NOT) cell can be combined with other logic cells to minimize cell latency.

Congestion and Timing Aware Macro Placement Using Machine Learning Predictions from Different Data Sources: Cross-design Model Applicability and the Discerning Ensemble

Abstract: Modern very large-scale integration (VLSI) designs typically use a lot of macros (RAM, ROM, IP) that occupy a large portion of the core area. Also, macro placement being an early stage of the physical design flow, followed by standard cell placement, physical synthesis (place-opt), clock tree synthesis and routing, etc., has a big impact on the final quality of result (QoR). There is a need for Electronic Design Automation (EDA) physical design tools to provide predictions for congestion, timing, and power etc., with certainty for different macro placements before running time-consuming flows. However, the diversity of IC designs that commercial EDA tools must support and the limited number of similar designs that can provide training data, make such machine learning (ML) predictions extremely hard. Because of this, ML models usually need to be completely retrained for unseen designs to work properly. However, collecting full flow macro placement ML data is time consuming and impractical. To make things worse, common ML methods, such as regression, support vector machine (SVM), random forest (RF), neural network (NN) in general, lack a good estimation of prediction accuracy or confidence and lack debuggability for cross-design applications. In this paper, we present a novel discerning ensemble technique for cross-design ML prediction for macro placement. We developed our solution based on a large number of designs with different design styles and technology nodes, and tested the solution on 8 leading-edge industry designs and achieved comparable or even better results in a few hours (per design) than manual placement results that take many engineers weeks or even months to achieve. Our method shows great promise for many ML problems in EDA applications, or even in other areas.

Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs

Abstract: Hierarchical very-large-scale integration (VLSI) flows are an understudied yet critical approach to achieving design closure at giga-scale complexity and gigahertz frequency targets. This paper proposes a novel hierarchical physical design flow enabling the building of high-density and commercial-quality two-tier face-to-face-bonded hierarchical 3D ICs. We significantly reduce the associated manufacturing cost compared to existing 3D implementation flows and, for the first time, achieve cost competitiveness against the 2D reference in large modern designs. Experimental results on complex industrial and open manycore processors demonstrate in two advanced nodes that the proposed flow provides major power, performance, and area/cost (PPAC) improvements of 1.2 to 2.2 × compared with 2D, where all metrics are improved simultaneously, including up to power savings.

RTL-MP: Toward Practical, Human-Quality Chip Planning and Macro Placement

Abstract: In a typical RTL-to-GDSII flow, floorplanning plays an essential role in achieving decent quality of results (QoR). A good floorplan typically requires interaction between the frontend designer, who is responsible for the functionality of the RTL, and the backend physical design engineer. The increasing complexity of macro-dominated designs (especially machine learning accelerators with autogenerated RTL) has made the floorplanning task even more challenging and time-consuming. In this paper, we propose RTL-MP, a novel macro placer which utilizes RTL information and tries to "mimic" the interaction between the frontend RTL designer and the backend physical design engineer to produce human-quality floorplans. By exploiting the logical hierarchy and processing logical modules based on connection signatures, RTL-MP can capture the dataflow inherent in the RTL and use the dataflow information to guide macro placement. We also apply autotuning to optimize hyperparameter settings based on input designs. We have built RTL-MP based on OpenROAD infrastructure and applied RTL-MP to a set of industrial designs. RTL-MP outperforms state-of-the-art commercial macro placers and achieves QoR similar to that of handcrafted floorplans.

VLSI Physical Design: From Graph Partitioning to Timing Closure

Abstract: This textbook introduces and compares algorithms that are used during the physical design phase of integrated-circuit design.

In-Route Pin Access-Driven Placement Refinement for Improved Detailed Routing Convergence

Abstract: Pin access is increasingly important in advanced nodes. Neighboring or cell-boundary pins can have degraded pin accessibility, causing design rule violations (DRCs) during routing, which are runtime expensive to resolve. Conventional physical design tool flow uses pessimistic and/or inaccurate understanding of pin access during the placement stage and keeps the location of cells fixed during routing. This can leave pin access issues unsolvable and block further routing solution improvement. The timeliness of our present work is confirmed by the recent ICCAD-2020 CAD Contest, Problem B formulation from Synopsys, Inc. (Hu and Yang, 2020). The organizers give a succinct motivation for what we study—to eliminate preserved margins and misalignment issues from conventional placement models. In this work, we develop an in-route, pin access-driven local placement refinement. Experiments across industry designs in a wide range of advanced technology nodes confirm that our optimization can significantly improve routing convergence (i.e., subsequent detailed routing runtime and initial detailed routing DRCs). Our optimization can reduce congestion and wirelength without timing degradation.

Scalability and Generalization of Circuit Training for Chip Floorplanning

Abstract: Chip floorplanning is a complex task within the physical design process, with more than six decades of research dedicated to it. In a recent paper published in Nature~\citemirhoseini2021graph, a new methodology based on deep reinforcement learning was proposed that solves the floorplanning problem for advanced chip technologies with production quality results. The proposed method enables generalization, which means that the quality of placements improves as the policy is trained on a larger number of chip blocks. In this paper, we describe Circuit Training, an open-source distributed reinforcement learning framework that re-implements the proposed methodology in TensorFlow v2.x. We will explain the framework and discuss ways it can be extended to solve other important problems within physical design and more generally chip design. We also show new experimental results that demonstrate the scaling and generalization performance of Circuit Training.

PPATuner: pareto-driven tool parameter auto-tuning in physical design via gaussian process transfer learning

Abstract: Thanks to the amazing semiconductor scaling, incredible design complexity makes the synthesis-centric very large-scale integration (VLSI) design flow increasingly rely on electronic design automation (EDA) tools. However, invoking EDA tools especially the physical synthesis tool may require several hours or even days for only one possible parameters combination. Even worse, for a new design, oceans of attempts to navigate high quality-of-results (QoR) after physical synthesis have to be made via multiple tool runs with numerous combinations of tunable tool parameters. Additionally, designers often puzzle over simultaneously considering multiple QoR metrics of interest (e.g., delay, power, and area). To tackle the dilemma within finite resource budget, designing a multi-objective parameter auto-tuning framework of the physical design tool which can learn from historical tool configurations and transfer the associated knowledge to new tasks is in demand. In this paper, we propose PPATuner, a Pareto-driven physical design tool parameter tuning methodology, to achieve a good trade-off among multiple QoR metrics of interest (e.g., power, area, delay) at the physical design stage. By incorporating the transfer Gaussian process (GP) model, it can autonomously learn the transfer knowledge from the existing tool parameter combinations. The experimental results on industrial benchmarks under the 7nm technology node demonstrate the merits of our framework.

Automated Deep Learning Platform for Accelerated Analog Circuit Design

Abstract: We present an analog design framework for circuit sizing selection using neural networks. The proposed automated deep learning (ADL) platform uses neural networks (NN) as a differentiable surrogate model for circuit performance to model the nonlinear and high dimensional relationships between sizing performance and circuit performance in analog circuits. Gradient-based constrained optimization is then used to propose new sizing parameters for the desired design closure, which are then verified using EDA tools. If circuit performance falls short of desired performance, the simulation results from the EDA tools are also used as additional training data to update the neural network model for the next design iteration. The tight coupling between NN and EDA tools in an iterative design loop achieves multi-variate design closure and has the capability to synthesize circuits with a significantly reduced number of circuit simulations.

Physical Design and optimization method of a feedthrough signal line based on low-power integrated circuit

Abstract: In view of the contradiction between the optimization of chip area and the closure of signal timing in the physical design of low-power Integrated Circuit, by planning the input and output signals and calculating the resource of routing channel, as well as a deep understanding of the global macro unit of the chip, a new way to design and implement the signal line is proposed, which not only satisfies the demand of the chip's compressed area cost, but also satisfies the timing optimization of the key input and output signals, it lays a solid foundation for further improving the performance of the chip in the later period.

RosettaStone: Connecting the Past, Present, and Future of Physical Design Research

Abstract: Editor’s notes: In this article, the authors introduce RosettaStone, an open and extensible foundation, which leverages a standard physical design data model (LEF/DEF 5.8) and open-source database implementation (OpenDB) to effectively connect the academic physical design field’s past, present, and future. The authors also show how RosettaStone enables integration of closed-source research tools and nonstandard data formats for robust evaluation with modern technologies and testcases. Following the release of the IEEE CEDA DATC Robust Design Flow, RosettaStone is expected to contribute to a standard backplane for integration and testing of new methods in academic research on physical design and its translation into industry practice. —Yiran Chen, Duke University

Asynchronous Circuit Principles and a Survey of Associated Design Tools

Abstract: Planning and implementing a semiconductor integrated circuit is a highly complex process. Although physical limits seem to be approaching, it currently follows a growing evolutionary path. As deep submicron technologies evolve towards perhaps even sub-nano geometries, the design process complicates accordingly. Once subtle in higher geometry nodes, some effects become relevant or even dominant. Examples are effects that tamper the reliability of wires, such as crosstalk, or the adequate behaviour of gates, such as the increasing sensitivity to single event effects. Design techniques must thus also evolve, to provide a wide range of tools to deal with new effects during the integrated circuit design and test processes. This tutorial covers one set of design techniques that is often overlooked, but which can reveal themselves instrumental in dealing with the mentioned technology evolution, the use of clockless or asynchronous circuits. The tutorial is divided into three parts: first it introduces a metamodel for the digital circuit design process enabling to reason about distinct design styles; second, it covers the main principles of asynchronous circuit design, differentiating it from mainstream circuit design techniques such as conventional synchronous design; the third and last part presents a set of tools and systems that can be employed to effectively design asynchronous design, with emphasis on material that can be used to produce manufacturable circuits and systems, often associated to commercial integrated circuit synthesis, implementation and test tools and frameworks.

GraphPlanner: Floorplanning with Graph Neural Network

Abstract: Chip floorplanning has long been a critical task with high computation complexity in the physical implementation of VLSI chips. Its key objective is to determine the initial locations of large chip modules with minimized wirelength while adhering to the density constraint, which in essence is a process of constructing an optimized mapping from circuit connectivity to physical locations. Proven to be an NP-hard problem, chip floorplanning is difficult to be solved efficiently using algorithmic approaches. This article presents GraphPlanner, a variational graph-convolutional-network-based deep learning technique for chip floorplanning. GraphPlanner is able to learn an optimized and generalized mapping between circuit connectivity and physical wirelength and produce a chip floorplan using efficient model inference. GraphPlanner is further equipped with an efficient clustering method, a unification of hyperedge coarsening with graph spectral clustering, to partition a large-scale netlist into high-quality clusters with minimized inter-cluster weighted connectivity. GraphPlanner has been integrated with two state-of-the-art mixed-size placers. Experimental studies using both academic benchmarks and industrial designs demonstrate that compared to state-of-the-art mixed-size placers alone, GraphPlanner improves placement runtime by 25% with 4% wirelength reduction on average.

PPATuner

Abstract: Thanks to the amazing semiconductor scaling, incredible design complexity makes the synthesis-centric very large-scale integration (VLSI) design flow increasingly rely on electronic design automation (EDA) tools. However, invoking EDA tools especially the physical synthesis tool may require several hours or even days for only one possible parameters combination. Even worse, for a new design, oceans of attempts to navigate high quality-of-results (QoR) after physical synthesis have to be made via multiple tool runs with numerous combinations of tunable tool parameters. Additionally, designers often puzzle over simultaneously considering multiple QoR metrics of interest (e.g., delay, power, and area). To tackle the dilemma within finite resource budget, designing a multi-objective parameter auto-tuning framework of the physical design tool which can learn from historical tool configurations and transfer the associated knowledge to new tasks is in demand. In this paper, we propose PPATuner, a Pareto-driven physical design tool parameter tuning methodology, to achieve a good trade-off among multiple QoR metrics of interest (e.g., power, area, delay) at the physical design stage. By incorporating the transfer Gaussian process (GP) model, it can autonomously learn the transfer knowledge from the existing tool parameter combinations. The experimental results on industrial benchmarks under the 7nm technology node demonstrate the merits of our framework.

An Improved Harmony Search Approach for Block Placement for VLSI Design Automation

Abstract: The technology grows quickly in the area of the VLSI physical design; it is crucial to integrate the greater number of transistors and parts into a very small range. Before the placement is completed, the physical and technical positioning of the blocks in the chip area is planned, which is nothing but floor planning. In order to lessen the placement region in the physical layout, floor planning must be carried out effectively. This paper proposes a blended harmony search and particle swarm optimization (BHSPS) algorithm which is the deliberate blend of the harmony search (HS) algorithm, and the particle swarm optimization (PSO) algorithm is proposed to acquire the central goal of the VLSI placement strategy. The objective here is to lessen the field of plan. The MATLAB code for the blended harmony search and particle swarm optimization (BHSPS) algorithm is compiled, and investigations were carried out for better examination through the standard MCNC, i.e., North Carolina Microelectronics Center benchmark circuits.

Towards a Reference Place and Route Flow for Academic Research

Abstract: Due to the complexity of contemporary circuits, physical synthesis has become a crucial step for achieving design closure. The placement of cells direct impacts the routing solution. For example, a region with a high cell density can lead to pin access issues in detailed routing. Therefore, small inefficiencies in the placement solution can be boosted during routing, which has a negative impact on design quality and convergence. Unfortunately, most academic research works evaluate the results only in the target step without considering the complete place and route flows. In this work, we experimentally explored different flows built up from academic placers and routers to find which one leads to the best overall results so that researchers can use them as a reference. In order to evaluate those flows, we used the ISPD 2018 and ISPD 2019 CAD Contest benchmarks, which are the most realistic academic benchmarks available with placement and routing information. Considering the evaluator reports, no combination of tools achieved the best result for all circuits. Nevertheless, the flow Contest placement + CUGR + TritonRoute achieved the best results in fifteen out of twenty benchmarks.

Machine Learning Approaches for Electronic Design Automation in IC Design Flow

Abstract: Due to the vast amount of data collected and the very high level of complexity in VLSI design and manufacturing, the implementation using machine learning can be used in physical design has increased significantly. ML can be used to increase the abstraction level that is obtained from complex simulations based on physics models and provide results that represent a significant level of quality. Computer science techniques such as pattern matching and machine learning can reduce the design time of VLSI circuits by working with large datasets.

Intelligent Circuit Design and Implementation with Machine Learning

Abstract: The stagnation of EDA technologies roots from insufficient knowledge reuse. In practice, very similar simulation or optimization results may need to be repeatedly constructed from scratch. This motivates my research on introducing more 'intelligence' to EDA with machine learning (ML), which explores complex correlations in design flows based on prior data. Besides design time, I also propose ML solutions to boost IC performance by assisting the circuit management at runtime. In this dissertation, I present multiple fast yet accurate ML models covering a wide range of chip design stages from the register-transfer level (RTL) to sign-off, solving primary chip-design problems about power, timing, interconnect, IR drop, routability, and design flow tuning. Targeting the RTL stage, I present APOLLO, a fully automated power modeling framework. It constructs an accurate per-cycle power model by extracting the most power-correlated signals. The model can be further implemented on chip for runtime power management with unprecedented low hardware costs. Targeting gate-level netlist, I present Net2 for early estimations on post-placement wirelength. It further enables more accurate timing analysis without actual physical design information. Targeting circuit layout, I present RouteNet for early routability prediction. As the first deep learning-based routability estimator, some feature-extraction and model-design principles proposed in it are widely adopted by later works. I also present PowerNet for fast IR drop estimation. It captures spatial and temporal information about power distribution with a customized CNN architecture. Last, besides targeting a single design step, I present FIST to efficiently tune design flow parameters during both logic synthesis and physical design.

Practical Substrate Design Considering Symmetrical and Shielding Routes

Abstract: In modern package design, the flip-chip package has become mainstream because of the benefit of its high I/O pins. However, the package design is still done manually in the industry. The lack of automation tools makes the package design cycle longer due to complex routing constraints, and the frequent modification requests. In this work, we propose yet another routing framework for substrate routing. Compared with previous works, our routing algorithm generates a feasible routing solution in a few seconds for industrial design and considers important symmetry and shielding constraints that have not been handled before. Benefiting from the efficiency of our routing algorithm, the designer can get the result immediately and accommodate some modifications to reduce the cost. The experimental result shows that the routing result generated from our router is in good quality, very close to the manual design.

Metal Layer Sharing: A Routing Optimization Technique for Monolithic 3D ICs

Abstract: As Moore’s law with traditional process node scaling is slowing down, other techniques are required for the advancement of process nodes. In this work, we focus on one such alternative: 3-D physical design of integrated circuits (ICs). While many recent studies have shown the benefits of 3-D IC design on timing and power consumption of circuits, routing in 3-D is solely done with the automatic commercial routers and has not been well studied. In this article, we discuss the various routing scenarios that arise from cell partitioning and the metal layer stack in 3-D. Unlike a 2-D IC, the metal layer configuration in 3-D depends on the orientation in which the dies are bonded together. Due to this, depending on the configuration, cells in one tier tend to use routing layers from the other tier. This is referred to as metal layer (or) routing sharing. This depends on the metal layer stack and the cell partitioning in 3-D, as well as the via pitch used for 3-D connections. By analyzing metal layer sharing in detail, we see that it can help reduce metal layer costs in 3-D as well as improve the power consumption and, in some cases, the maximum achievable performance of the circuits. Overall, the 3-D metal layer cost can decrease by 9% along with an improved power delay product of up to 7.5% just from the routing sharing in monolithic 3-D ICs.

Physical Design at the Transistor Level Beyond Standard-Cell Methodology

Abstract: This talk offers a review of possibilities to explore on VLSI layout beyond traditional standard cell methodology. Existing Physical Design tools strictly avoid any modification to the contents of Standard Cells. Here, a post-processing step based on SAT solvers is proposed to obtain optimal solutions for local transistor level layout synthesis problems. This procedure can be constrained by metrics that ensure that quality is not degraded, and an acceptable and better-quality timing model can be rebuilt for the block. These problems and techniques are open research opportunities in Physical Design as they are not sufficiently explored in the literature and can bring significant improvements to the quality of a VLSI circuit.

Modeling and Predicting Transistor Aging under Workload Dependency using Machine Learning

Abstract: The pivotal issue of reliability is one of colossal concern for circuit designers. The driving force is transistor aging, dependent on operating voltage and workload. At the design time, it is difficult to estimate close-to-the-edge guardbands that keep aging effects during the lifetime at bay. This is because the foundry does not share its calibrated physics-based models, comprised of highly confidential technology and material parameters. However, the unmonitored yet necessary overestimation of degradation amounts to a performance decline, which could be preventable. Furthermore, these physics-based models are exceptionally computationally complex. The costs of modeling millions of individual transistors at design time can be evidently exorbitant. We propose the revolutionizing prospect of a machine learning model trained to replicate the physics-based model, such that no confidential parameters are disclosed. This effectual workaround is fully accessible to circuit designers for the purposes of design optimization. We demonstrate the models' ability to generalize by training on data from one circuit and applying it successfully to a benchmark circuit. The mean relative error is as low as 1.7%, with a speedup of up to 20X. Circuit designers, for the first time ever, will have ease of access to a high-precision aging model, which is paramount for efficient designs. This work is a promising step in the direction of bridging the wide gulf between the foundry and circuit designers.

Methodology for Structured Data-Path Implementation in VLSI Physical Design: A Case Study

Abstract: State-of-the-art modern microprocessor and domain-specific accelerator designs are dominated by data-paths composed of regular structures, also known as bit-slices. Random logic placement and routing techniques may not result in an optimal layout for these data-path-dominated designs. As a result, implementation tools such as Cadence’s Innovus include a Structured Data-Path (SDP) feature that allows data-path placement to be completely customized by constraining the placement engine. A relative placement file is used to provide these constraints to the tool. However, the tool neither extracts nor automatically places the regular data-path structures. In other words, the relative placement file is not automatically generated. In this paper, we propose a semi-automated method for extracting bit-slices from the Innovus SDP flow. It has been demonstrated that the proposed method results in 17% less density or use for a pixel buffer design. At the same time, the other performance metrics are unchanged when compared to the traditional place and route flow.