Showing papers on "Pipeline (computing) published in 1979"

Prediction Method for Buried Pipeline Voltages Due to 60 Hz AC Inductive Coupling Part I-Analysis

Abstract: The voltages induced on gas transmission pipelines by 60 Hz ac power transmission lines sharing a joint right-of-way are predicted using electrical transmission line theory. Thevenin equivalent circuits for pipeline sections are developed which allow the decomposition of complex pipeline-power line geometries. Programmable hand calculator techniques are used to determine inducing fields, pipeline characteristics, and Thevenin circuits.

Data processing system having a high speed pipeline processing architecture

Abstract: A data processing system having a pipeline processing architecture for performing a sequence of operations upon each group of data, one of which is a conditional group, comprising a main pipeline for performing the sequence of operations upon the data other than the conditional data and a sub-pipeline for processing the conditional data, wherein the two pipelines are synchronized on the same time base so that executing time is determined only by the main pipeline.

Prediction Method for Buried Pipeline Voltages Due to 60 Hz AC Inductive Coupling Part II--Field test Verification

Abstract: The results of field tests on a buried, 34-inch diameter gas pipeline adjacent to a 525 kV ac power transmission line for 54 miles are discussed. Comparison is made between measured inductive coupling data and predictions obtained using the theory developed in part I of this paper. An excellent agreement of the predicted and measured results is shown for the location and magnitude of all induced voltage peaks on the pipeline.

A data flow evaluation system based on the concept of recursive locality

Abstract: In an attempt to increase the performance of computing machines, there appears to be two main approaches—(1) to use faster components in existing architectures and (2) to design new architectures which are capable of exploiting some form of concurrency. The first approach is inherently limited in that the effects of reduced integrated circuit geometry, new process technology, and new logic families can be expected to increase overall system performance by only a couple of orders of magnitude. While this is initially impressive, it does not allow the desired machine performance projected to be necessary to solve large physics problems, or needed for accurate weather prediction. 16 The second approach, while being a considerably more difficult organizational problem, is inherently unlimited in nature. There are numerous levels at which concurrency can be exploited in digital computers, i.e. multiple data paths, more concurrent realization of low-level circuit functions, overlap and pipeline processing within a single processing element, multiple processors, etc. In developing any new "fast as possible" machine, it is important to attempt to implement all of the above suggestions. However the work reported here will mainly be concerned with solving the problem of how to utilize and organize systems containing large numbers of independent processors.

Mitigation of Buried Pipeline Voltages due to 60 Hz AC Inductive Coupling Part I-Design of Joint Rights-of-Way

Abstract: Useful mitigation techniques are presented for the reduction of voltages induced on gas transmission pipelines by 60 Hz ac power transmission lines sharing a joint right-of-way Part I describes how a joint pipeline/power line corridor can be designed to minimize inductive coupling This allows installation of the utilities with significantly reduced requirements for pipeline voltage mitigation using grounding techniques

Mitigation of Buried Pipeline Voltages Due to 60 Hz AC Inductive Coupling Part II --Pipeline Grounding Methods

Abstract: This paper presents useful mitigation techniques for the reduction of voltages induced on gas transmission pipelines by 60 Hz ac power transmission lines sharing a joint right-of-way. Part II describes how pipeline grounding methods can be implemented to reduce pipeline voltage peaks after installation of the utilities on the joint right-of-way. The use of properly -designed grounding systems permits the maximum mitigation of pipeline voltages at minimum cost.

On-line algorithms for the design of pipeline architectures

Abstract: This paper presents a class of algorithms, On-Line Continued Sums/Products, which are amenable for the efficient implementation by a pipeline architecture. The implementation of these algorithms provides a simple and fast method for the evaluation of several of the elementary functions; i.e., addition, subtraction, multiplication, division, logarithm, exponentiation, sine, cosine, and tangent. In addition to possessing the expected properties necessary for the efficient implementation in a pipeline architecture, the On-Line Continued Sums/Products algorithms allow for the possibility of implementing a pipeline architecture which is dynamically reconfigurable and which can process variable precision operands.

Method and apparatus for detecting the location of a marine pipeline or cable

Abstract: Method and apparatus for detecting the location of a marine pipeline or cable, whereby acoustic pulses are transmitted by a submarine pulse transmitter carried by a vessel. These pulses, as well as the reflections of the pulses on the seabottom and on the pipeline or cable are detected by means of two detectors that are carried by two paravanes towed by the vessel. The signals received by the detectors are combined and the record of the combined signals is displayed. The signal parts that are representative of the acoustic waves reflected by the pipeline are identified in the record by separate colors or various intensities of a single color.

Special Feature: Developing a Multiple-Instructon-Stream Single-Chip Processor

Abstract: Multiprocessing within a chip may be the next step in the evolution of single-chip microprocessors. The methodology described here achieves multiple-instruction-stream concurrency with a shared-resource pipeline architecture.

High-speed synchronous computer using pipelined registers and a two-level fixed priority circuit

Abstract: A digital processor including both macro and micro instruction generators. The micro-instruction generator comprises a sequencer for generating instruction addresses, a memory for generating instructions in response to the addresses and a pipeline register adapted to receive the instructions for execution. The sequencer operates at a constant CLK 1 rate while the pipeline register operates at a variable CLK 2 rate; i.e., the occurrence of a branch instruction in the pipeline register operates to inhibit CLK 2 for one CLK 1 time so as to prevent loading for execution of the aborted sequential instruction during the loading of a new non-sequential instruction address. CLK 2 resumes upon the next CLK 1 signal to resume sequential operation. Special branch instructions are utilized to fetch macro-instructions from a pipelined system of macro-instruction registers. A two-tier synchronous arbitration system for memory requests is also disclosed.

Pipeline leak detection

Abstract: The present invention pertains to a process for detecting leaks in a pipeline when the flow is in a transient or steady condition. A mathematical model of the pipeline is constructed and real pressures and real flows are compared at various locations in the pipeline with predicted pressures and flows of the model at such locations. Leaks in the pipeline are indicated when upstream of the leak real pressure decreases and real flow increases with respect to the model and downstream of the leak real pressure decreases and real flow decreases with respect to the model.

Sequential successive approximation analog-to-digital converter

Abstract: A pipelined analog-to-digital (A/D) conversion system enhances the effective data rate of the converter in direct proportion to the number of stages in the pipeline. The pipelined A/D converter operates in conjunction with a charge-coupled device (CCD) multilevel storage (MLS) in a three-bit (eight-level) implementation. Three comparators are used in the three-bit system arranged in a sequential successive approximation configuration with control circuits and a CCD shift register.

Method of laying offshore pipeline from a reel carrying vessel

Abstract: Disclosed are methods and techniques related to the control of pipelaying operations from a self-propelled reel pipelaying vessel. The methods are concerned with (1) controlling pipeline geometry as a function of pipe entry angle into the water and tension on the pipeline; (2) monitoring the excursion of the pipeline outside certain defined limits and controlling the pipeline geometry based on such measured excursions; and (3) compensating for pipeline induced turning moments which would otherwise tend to draw the pipelaying vessel off course and off the predetermined pipeline right of way.

Pipeline leak detection method and control device therefor

Abstract: For sealing a pipeline at selective locations in order to perform leak tests, a pipeline packer assembly capable of internal travel within the pipeline can be moved to and stopped at selected locations and the packer inflated against the interior pipe walls to prevent further movement of the unit, and to provide a seal so that the pipeline may be subjected to internal high pressures to detect leaks. According to the invention, a control device for such unit comprises a gamma ray detector and signal processor receiving the electrical analogue signal from the gamma ray detector. An energizing signal from the signal processor actuates a stepping switch which provides "inflate" and "deflate" energization of the packer, and is kept in "off" condition while the packer is inoperative as in transit within the pipeline. A radiation source on the surface or selectively inserted into a bore hole near the pipeline provides a stimulus for the gamma ray detector which controls the operation of the stepping switch. The insertion and subsequent withdrawal of the radiation source from the vicinity of the pipe adjacent the control unit, successively causes the successive stepping of the stepping switch to "inflate", "deflate" and "off" conditions. The assembly is moved through the pipeline at low pressure, and the pipeline subjected to high pressure behind the packer when it is inflated, thereby to permit leak detection at successive locations within the pipeline.

Low-level processing for real-time image analysis

Abstract: This paper describes a system that detects object outlines in television images in real-time. A high-speed pipeline processor transforms the raw image into an edge map and a microprocessor, which is integrated into the system, clusters the edges and represents them as chain codes. Image statistics, useful for higher level tasks such as pattern recognition, are computed by the micro processor. Peak intensity and peak gradient values are extracted within a programmable window and are used for iris and focus control. The algorithms implemented in hardware and the pipeline processor architecture are described. The strategy for partitioning functions in the pipeline was chosen to make the implementation modular. The microprocessor interface allows flexible and adaptive control of the feature extraction process.

Pipeline transportation system

Abstract: A hydraulic capsule pipelining system including a pipeline adapted for flow therethrough of water or other carrier liquid to propel cargo-containing capsules through the pipeline, and means for pumping the liquid through the pipeline utilizing a segment of length of the pipeline as a pump cyclinder and utilizing capsules passing through said pump cylinder segment of the pipeline as pistons in said segment for pumping the liquid forward through the pipeline, capsules being propelled through said segment by an externally produced electromagnetic field.

Rapid analysis of hematology image data: the ADC-500 preprocessor.

Abstract: A sequential, pipeline processor (that we have named the ADC-500 preprocessor) has been developed which scene segments the three color image data from the ADC-500 optics one image element at a time, groups together image elements from each object in the scene and extracts features from each object. The processing occurs at television frame rates, requiring 16.7 msec to process the entire image. This speed was instrumental in allowing the ADC-500 automated differential analyzer to perform routine 500-cell differentials. The preprocessor also contains hardware which simplifies compilation of the three color histograms. The segmentation algorithms implemented in the preprocessor are multicolor extensions of the classical monochrome density histogram threshold method. For most cell image analysis tasks, a sequential pipeline processor of this type should be more economical and as fast or faster than a parallel processor.

Computer architectures for vision

Abstract: It is estimated that systems capable of executing 1 to 100 billion operations per second will be required to achieve near-real time performance in image analysis tasks. In this paper, we present three aspects of architecture for realizing economical solutions to this problem. At the Processor-Memory-Switch (PMS) level, we consider parallel and pipeline architectures using multiprocessor and array processor systems. At the Instruction-Set-Processor (ISP) level, we consider the firmware implementation of special instruction sets for image processing. At the processor design level, we consider the design of complex Arithmetic-Logic-Units (ALU) for execution of complex image operations. Given these alternative aspects, we present hardware and software design considerations affecting the overall architecture. Together, they appear to hold the promise of several orders of magnitude improvement in speed over general purpose systems.

Method of marking and detecting a pipeline location

Abstract: A method of marking a pipeline location eliminates ambiguity in case there are leaks near the location of a marker It employs a marker that emits two separate frequencies that are modulated by a third frequency lower than either of the other two Detection of the marker on a pipeline pig is done by separating the two frequencies and demodulating the third Then by determining the coincidence of all three for a predetermined number of consecutive cycles of the third frequency, the marker location will be positively identified

Cellular two's complement serial-pipeline multipliers

Abstract: Serial two's complement pipeline multipliers are the basic module in the serial arithmetic implementation of digital signal processing algorithms. These multipliers accept the data serially in two's complement notation and generate a serial output product in two's complement notation as well. The designs, however, presented up to now lack in modularity; in addition, they have the problem of the internal overflow. In this paper a new two's complement multiplication algorithm is worked out, that allows cellular implementation of serial-pipeline multipliers and does not limit the dynamic range of the data input. In addition, by using the proposed cell, useful functions for digital signal processing can be performed. Methods are proposed for overflow detection, and comparison is made with previously proposed realizations.

Microprogram control system

Abstract: PURPOSE:To make microprogram control high-speed by transferring a micro instruction, which is to be executed, from a pipeline register to an operation part and transferring the operation result dependent upon the instruction, which has been already executed, at the same time approximately. CONSTITUTION:Microprogram memory 10 which stores micro instructions, pipeline register 11 which holds temporarily an instruction read from memory 10, address register 12 which holds an address of memory 10, and operator 13 which executes an instruction from register 12 are provided, and further, multiplexer 14 which selects the address of an instruction which is next executed, incrementer 15 which adds ''1'' to the output of register 12, and comparator 16 which compares address signals are provided. Branch processing circuit 17 which determines a next executed processing according to the output of comparator 16 is provided to transfer an insturction from register 11 to operator 13 and transfer the operation result dependent upon the insturction, which has been already executed, at the same time approximately.

Freight Pipeline, Rail, and Truck Cost Comparison

Abstract: This paper describes the use of four models for comparing the cost of transporting manufactured products via freight pipeline, truck, truck on flat car (TOFC), and rail carload. It was found that cost comparison is sensitive to the transportation configuration, i.e., location, transport distance, and the number of terminals, annual tonnage, the size of shipment, the design of pipeline system, access conditions, and accounting procedure. The study shows that, based on the annualized cost methodology, the transport cost per ton-mile via freight pipeline is cost competitive with truck, rail, and TOFC for four of the five configurations within the Philadelphia-Chicago transportation corridor if the annual tonnage is high. For the fifth configuration, truck is clearly a less expensive mode. However, based on the project's present value methodology, pipeline is cost competitive in all five configurations. Based on the annualized cost methodology, pipeline becomes reasonably attractive for three configurations and for one configuration it compares very favorably (2.7 cents/ton-mile for pipe vs. 2.8 cents/ton-mile for T-R combination).