Showing papers on "Pipeline (computing) published in 1982"
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04 Jan 1982TL;DR: In this paper, the memory bus is a packet-oriented bus, which is composed of processor buses (105) and corresponding control lines; and memory buses (107) with corresponding control line (108).
Abstract: A number of intelligent bus interface units (100) are provided in a matrix of orthogonal lines interconnecting processor modules (110) and memory control unit (MCU) modules (112). The matrix is composed of processor buses (105) and corresponding control lines; and memory buses (107) with corresponding control lines (108). At the intersection of these lines is a bus interface unit node (100). The bus interface units function to pass memory requests from a processor module to a memory module attached to an MCU node and to pass any data associated with the requests. The memory bus is a packet-oriented bus. Accesses are handled by means of a series of messages transmitted by message generator (417) in accordance with a specific control protocol. Packets comprising one or more bus transmission slots are issued sequentially and contiguously. Each slot in a packet includes an opcode, address, data, control, and parity-check bits. Write-request packets and read-request packets are issued to the memory-control unit. The memory-control unit responds with reply packets. A message controller (416), bus monitor (413), and pipeline and reply monitor ( 414), run the memory bus in a three-level pipeline mode. There may be three outstanding requests in the bus pipeline. Any further requests must wait for a reply message to free-up a slot in the pipeline before proceeding. Request messages increase the length of the pipeline and reply messages decrease the length of a pipeline. A control message, called a blurb, does not affect the pipeline length and can be issued when the pipeline is not full. The different messages are distinguished by three control signals (405) that parallel the data portion of the bus. The message generator (417) and interface logic (404) drive these control lines to indicate the message type, the start and end of the message, and possible error conditions. The pipeline and reply monitor (414) and the message controller (416) cooperate to insert a reply to a particular request in the pipeline position corresponding to the particular request that invoked the reply.
142 citations
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05 Oct 1982TL;DR: The MIPS processor is a fast pipelined engine without pipeline interlocks, which attempts to achieve high performance with the use of a simplified instruction set, similar to those found in microengines.
Abstract: MIPS is a new single chip VLSI microprocessor. It attempts to achieve high performance with the use of a simplified instruction set, similar to those found in microengines. The processor is a fast pipelined engine without pipeline interlocks. Software solutions to several traditional hardware problems, such as providing pipeline interlocks, are used.
92 citations
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11 Mar 1982TL;DR: In this article, a plurality of serial neighborhood transformation pipelines are provided for simultaneously operating on adjacent segments of a partitioned image matrix, and techniques for bi-directionally transferring pixel data on the edges of adjoining segments of the image matrix between adjacent processors in a manner which minimizes the number of interconnections there between.
Abstract: A plurality of serial neighborhood transformation pipelines are provided for simultaneously operating on adjacent segments of a partitioned image matrix. Techniques are disclosed for bi-directionally transferring pixel data on the edges of adjoining segments of the image matrix between adjacent processors in a manner which minimizes the number of interconnections therebetween. In such manner a parallel pipeline image processing system can be implemented in integrated circuit form while keeping the number of pins for each stage in the pipeline to a minimum.
72 citations
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TL;DR: A new hardware algorithm of parallel enumeration sorting circuits whose processing time is linearly proportional to the number of data for sorting is designed, suitable for VLSI implementation.
Abstract: We propose a new parallel sorting scheme, called the parallel enumeration sorting scheme, which is suitable for VLSI implementation. This scheme can be introduced to conventional computer systems without changing their architecture. In this scheme, sorting is divided into two stages, the ordering process and the rearranging one. The latter can be efficiently performed by central processing units or intelligent memory devices. For implementations of the ordering process by VLSI technology, we design a new hardware algorithm of parallel enumeration sorting circuits whose processing time is linearly proportional to the number of data for sorting. Data are serially transmitted between the sorting circuit and memory devices and the total communication between them is minimized. The basic structure used in the algorithm is called a bus connected cellular array structure with pipeline and parallel processing. The circuit consists of a linear array of one type of simple cell and two buses connecting all cells for efficient global communications in the circuit. The sorting circuit is simple, regular and small enough for realization by today's VLSI technology. We discuss several applications of the sorting circuit and evaluate its performance.
69 citations
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13 Oct 1982TL;DR: In this article, the authors present a method for prefetching instructions for a pipelined central processor unit for a general purpose digital data processing system, where a table is maintained for predicting the target addresses of transfer and indirect instructions based on past history of the execution of those instructions.
Abstract: Method and apparatus for prefetching instructions for a pipelined central processor unit for a general purpose digital data processing system. A table is maintained for purposes of predicting the target addresses of transfer and indirect instructions based on past history of the execution of those instructions. The prefetch mechanism forms instruction addresses and fetches instructions in parallel with the execution of previously fetched instructions by a central execution pipeline unit of the central processor unit. As instructions are prefetched, the transfer and indirect prediction (TIP) table is checked to determine the past history of those instructions. If no transfers or indirects are found, the prefetch proceeds sequentially. If transfer or indirect instructions are found, then the prefetch uses information in the TIP table to begin fetching the target instruction(s). The purpose of the prediction of target addresses is so that in the usual case instructions following a transfer can be executed at a rate of one instruction per pipeline cycle regardless of the pipeline depth or the frequency of transfers. Instructions are fetched two words at a time in order that the instruction fetch unit can stay ahead of the central execution pipeline. An instruction stack is provided for purposes of buffering double words of instructions fetched by the instruction fetch unit while waiting for execution by the central execution pipeline unit. The TIP table is updated based upon the actual execution of instructions by the central execution pipeline unit, and the correctness of the TIP table predictions is checked during execution of every instruction.
58 citations
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19 Jan 1982TL;DR: In this paper, a pipeline of programmable serial neighborhood stages is used to automatically check for adherence to a set of predetermined geometrical constraints or design rules used in the fabrication of electronic components such as integrated circuit devices.
Abstract: A pipeline of programmable serial neighborhood stages is used to automatically check for adherence to a set of predetermined geometrical constraints or design rules used in the fabrication of electronic components such as integrated circuit devices. In a disclosed embodiment, bit-map representations of several IC masks are superimposed in one composite image matrix for processing in the pipeline. Advantages in processing speed, especially for design rule checking requiring data from more than one mask, are obtained since all necessary data is available to the stages in the pipeline.
54 citations
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01 Dec 1982TL;DR: In this article, a data processing apparatus executing a plurality of instructions in a pipeline mode by dividing each of the instructions into plurality of stages, its operation circuit includes a first execution (E) unit capable of execution of operations required by all of the plural instructions and a second E unit only.
Abstract: In a data processing apparatus executing a plurality of instructions in a pipeline mode by dividing each of the instructions into a plurality of stages, its operation circuit includes a first execution (E) unit capable of execution of operations required by all of the plural instructions and a second E unit capable of execution of operations required by part of the plural instructions only. A queue of data including decoded information of the instructions required for execution of operation stages are stored in a circuit to be selectively supplied by first and second circuits to the first and second E units, respectively. The first and second circuits sequentially select succeeding data in synchronism with the end of operations in the first and second E units respectively. As a result, when a stage of a succeeding instruction requires the result of operation of a preceding instruction being executed, that stage of the succeeding instruction is executed after the second E unit completes the operation of the preceding instruction, even when the first E unit is executing an instruction further preceding the preceding instruction.
35 citations
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31 Mar 1982
TL;DR: In this paper, a method for the location of pipeline damage and medium leak therefrom by acoustical monitoring of the soil about a pipe and recording emission noise by microphone and an amplifier which controls a peak noise indicator is provided.
Abstract: Apparatus and method are provided for the location of pipeline damage and medium leak therefrom by acoustical monitoring of the soil about a pipe and recording emission noise by microphone and an amplifier which controls a peak noise indicator. Each measurement point detected by the amplifier is applied to a digital memory to display a histogram showing noise distribution along the pipe. The main frequency of the loudest measurement point is determined, and an octave filter is utilized to determine the frequency characterizing medium leakage to precisely locate the pipeline damage. Bar diagrams may be provided on a viewplate by bands of parallel arrays of light emitting diodes to display noise distribution along the pipeline. A frequency analyzer may transmit from the amplifier to the memory the peak frequency value of each observed frequency band to enable frequency analysis of the loudest measurement point. The apparatus may have a case with a lid defining openings sized for viewing the bar diagrams.
30 citations
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21 Oct 1982TL;DR: In this paper, a method and system for monitoring the operating status of a materials distribution network having a distribution pipeline and a plurality of pumping stations located at spaced intervals along the pipeline for pumping material through the pipeline, wherein each station includes one or more pumps connected to the pipeline and having shafts connected respectively to the pumps for operating the pumps.
Abstract: A method and system are disclosed for monitoring the operating status of a materials distribution network having a distribution pipeline and a plurality of pumping stations located at spaced intervals along the pipeline for pumping material through the pipeline, wherein each station includes one or more pumps connected to the pipeline and one or more motors having shafts connected respectively to the pumps for operating the pumps. A plurality of primary input parameters at each of the pumping stations are sensed, including the shaft speed of each of the motors, the output torque of each of the motors, and the energy input to each of the motors. A plurality of values including the power produced by each of the motors, and the operating efficiency of each of the motors are calculated from the input parameters. The calculated efficiency values are displayed for operator use. The economic and financial savings or losses are calculated for management use.
29 citations
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25 Jan 1982TL;DR: The basic problem of reorganization of machine level instructions at compile-time is shown to be NP-complete and a heuristic algorithm is proposed and its properties and effectiveness are explored.
Abstract: Pipeline interlocks are used in a pipelined architecture to prevent the execution of a machine instruction before its operands are available. An alternative to this complex piece of hardware is to rearrange the instructions at compile-time to avoid pipeline interlocks. This problem, called code reorganization, is studied. The basic problem of reorganization of machine level instructions at compile-time is shown to be NP-complete. A heuristic algorithm is proposed and its properties and effectiveness are explored. The impact of code reorganization techniques on the rest of a compiler system are discussed.
29 citations
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TL;DR: Three parallel versions of this algorithm for the rounding exact summation of floating point numbers are proposed, namely a pipeline version, an algorithm similar to the exchange methods for sorting and a tree-like algorithm, associating a tree to the sum.
Abstract: Pichat and Bohlender studied an algorithm for the rounding exact summation of floating point numbers which can be executed on any floating point arithmetic unit. We propose parallel versions of this algorithm, namely a pipeline version, an algorithm similar to the exchange methods for sorting and a tree-like algorithm, associating a tree to the sum. For all these algorithms we discuss the properties, a multiprocessor architecture should have for an efficient implementation of an algorithm without restricting us to a special architecture.
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12 Oct 1982TL;DR: A pipeline clamp for securing a heated arctic pipeline to its support structure comprises a sandwich material of inner and outer layers of fiber reinforced rigid polymer and an intermediate core layer of honeycomb-form aramid paper as mentioned in this paper.
Abstract: A pipeline clamp for securing a heated arctic pipeline to its support structure comprises a sandwich material of inner and outer layers of fiber reinforced rigid polymer and an intermediate core layer of honeycomb-form aramid paper. The clamp affords all the engineering advantages of prior steel clamps without the disadvantages of being heat conductive which can result in conductance of pipeline heat to the permafrost layer as well as "freezing out" of low melting paraffins flowing within the pipeline which decrease pipeline efficiencies.
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14 Dec 1982TL;DR: In this article, a pipeline arithmetic apparatus is presented, where an arithmetic operation is divided into a plurality of stages and processed in an overlapping manner in each of the stages, and a set of arithmetic circuits are provided each in association with each stage.
Abstract: In a pipeline arithmetic apparatus, an arithmetic operation is divided into a plurality of stages and processed in an overlapping manner in each of the stages. Arithmetic circuits are provided each in association with each stage. Registers hold control information indicating the contents of arithmetic operations to the individual arithmetic circuits or to a predetermined number of the arithmetic circuits, respectively. The control information held by each of the registers is supplied to the associated arithmetic circuit or circuits straight-forwardly or after having been decoded to command the arithmetic operation to be executed by each of the arithmetic circuits. The control information held by each of the registers as well as the output from each of the arithmetic circuits is transferred to the registers and the arithmetic circuits of the succeeding stages, respectively.
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TL;DR: A FDCT (fast discrete cosine transform) processor is designed to have throughput rates consistent with high speed, (real time) processing of standard National Television Systems Committee (NTSC) color television signal sampled at 3fsc = 10.7 MHz.
Abstract: A FDCT (fast discrete cosine transform) processor is designed to have throughput rates consistent with high speed, (real time) processing of standard National Television Systems Committee (NTSC) color television signal sampled at 3fsc = 10.7 MHz where fsc is the color subcarrier frequency. This is achieved by using a highly modular structure in a pipeline configuration. The development phase includes the selection of a suitable algorithm and the utilization of important features of the algorithm for hardware implementation. Since the prototype is used for research purposes, provisions are made for versatility of the control and selectabilifty of , the processing accuracy. The FDCT processor is capable of processing 4- or 8- or 16- point input segments and can also be used as a part of a larger system which processes a 32-point input segment. With minor modifications, the algorithm and the basic hardware design can be used for the fast inverse DCT (FIDCT) processor.
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10 May 1982TL;DR: In this paper, a pipelined Fast Fourier Transform (FFT) processor is described for continuous sets of N samples in a highly efficient manner, which achieves high arithmetic unit efficiency while minimizing the memory required by allowing each arithmetic unit in the pipeline, with the exception of the last, to operate on the even or odd numbered samples first, after which the remaining samples are appropriately delayed and switched through shift registers and switches.
Abstract: A pipelined Fast Fourier Transform (FFT) processor is described for proceng continuous sets of N samples in a highly efficient manner. Within a single set of N inputs, the samples arrive in pairs (sample 0, and 1, 2 and 3, 4 and 5, etc.). This input sequence can be obtained from a sequential stream of inputs (sample 0 followed by smples 1, 2, 3, 4, etc.) by delaying the even numbered sample by one time unit. Alternately, the device could be made to operate on sequential samples within a set of N samples by internal pipelining of the arithmetic units. The device achieves high arithmetic unit efficiency while minimizing the memory required by allowing each arithmetic unit in the pipeline, with the exception of the last, to operate on the even or odd numbered samples first, after which it will operate on the remaining samples, which have been appropriately delayed and switched through shift registers and switches. The structure of the device, through its novel arrangement of shift registers and switches, allows an internal reordering of the data such that 100 percent arithmetic unit efficiency can be obtained, while requiring only 2(N-1)-(N/2) memory locations.
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TL;DR: The concept of pseudoparallelism, in which the serial algorithm is partitioned into several noninteractive independent subtasks so that parallelism can be used within each subtask level, is introduced.
Abstract: In this paper we introduce the concept of pseudoparallelism, in which the serial algorithm is partitioned into several noninteractive independent subtasks so that parallelism can be used within each subtask level. This approach is illustrated by applying it to a real-time dynamic scene analysis. Complete details of such a pseudoparallel architecture with an emphasis to avoid interprocessor communications have been worked out. Problems encountered in the course of designing such a system with a distributed operating system (no master control) have been outlined and necessary justifications have been provided. A scheme indicating various memory modules, processing elements, and their data-path requirements is included and ways to provide continuous flow of partitioned information in the form of a synchronized pipeline are described.
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12 Apr 1982
TL;DR: In this paper, a method for distributing fluid along the interior wall of a pipeline wherein a quantity of fluid is placed at a location in the pipeline and exposed at one side to a force acting in an axial and rotational direction.
Abstract: A method for distributing fluid along the interior wall of a pipeline wherein a quantity of fluid is placed at a location in the pipeline and exposed at one side to a force acting in an axial and rotational direction. This force will cause at least a portion of the fluid to enter a helical path adjacent the pipeline which will force the material to be coated on the inner wall of the pipeline. As the fluid is coated on the pipeline wall it is exposed to an axial wiping force which smooths out the fluid coated onto the inner wall of the pipeline by removing the excess material.
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13 Oct 1982TL;DR: In this paper, the authors present a method and a central execution pipeline unit for initiating the execution of instructions of a synchronous central processor unit (CPU) of a general-purpose digital data processing system.
Abstract: A method and a central execution pipeline unit for initiating the execution of instructions of a synchronous central processor unit (CPU) of a general-purpose digital data processing system. Instructions containing address information and an instruction field are obtained in program order from an instruction fetch unit of the CPU. In a first stage, requiring one clock period, the address information of an instruction is utilized to form the carrys and sums of an effective address and to initiate the formation of a virtual address. Concurrently, the instruction field is decoded to produce memory command signals and data alignment signals. In a second stage, the formation of the effective and virtual addresses initiated in the first stage is completed, and the word address portion of the virtual address is transmitted to the cache unit of the CPU. Also during the second stage, memory command signals are sent to the cache unit and the instruction field is converted to an execution code for one of a plurality of execution units, and the execution unit to execute the code is designated. In a third stage, the virtual address is converted to a physical address, or real page number, which is transmitted to the cache unit. The execution code is sent to the designated execution unit; however, if the execution unit is the central unit, the execution unit is the central unit, the execution code for that unit is converted into execution unit control signals. In the fourth stage, data alignment control signals are sent to a distributor of the central execution pipeline unit.
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24 Sep 1982TL;DR: A telescoping boom assembly supported articulated well service pipeline for the transfer of pressurized fluids from service vehicles to petroleum wellheads for the treatment and stimulation of production oil wells is described in this paper.
Abstract: A telescoping boom assembly supported articulated well service pipeline for the transfer of pressurized fluids from service vehicles to petroleum wellheads for the treatment and stimulation of production oil wells. The boom assembly is mounted on a truck, trailer, or other suitable mobile transport, and the articulated pipeline comprises a plurality of long straight pipeline sections interconnected by a plurality of shorter pipe sections and by swivel joints. The inboard end of the pipeline is connected to a supply line by an inboard pipe and a pair of swivel joints. The pipeline can be folded into a cluster and tilted for storage adjacent the inboard end of the boom assembly and the clustered pipeline moved away from the service vehicle before unfolding the pipeline from the cluster. Retaining the pipeline in a compact cluster while moving the clustered pipeline between the storage position and a position beside the service vehicle provides an extra amount of clearance between the service vehicle and the pipeline to prevent a collision with any obstacle on the service vehicle.
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13 Feb 1982
TL;DR: In this article, the authors propose to omit read/write of unnecessary element data and to improve processing efficiency by reading previously a mask register and detecting nonfulfilment about elememts of ones interleaved.
Abstract: PURPOSE:To omit read/write of unnecessary element data and to improve processing efficiency by reading previously a mask register and by detecting nonfulfilment about elememts of ones interleaved. CONSTITUTION:Element data read from a vector register designated in an operand part of an instruction are stored successively in a read register 2, and it is then, after being delayed by a buffer register 4 by one-time slot, added to an arithmetic pipeline 5. Further, element data that are designated and read out in an next operand part are successively set in a read register 3 and are inputted into the line 5. An arithmetic result outputted from said pipeline is set in a write register 1, further is written in a vector register designated in the operand part of the instruction. Further, a mask element read from an operand register designated in the mask operand part of the instruction is read out and is set in a register 6, further the output is inputted into the line 5, thereby determining execution of an operation by the logic of the mask element.
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IBM1
TL;DR: In this paper, a data pipeline processor is used for time-shared I/O channel processing, where the data and addresses are stored in memory and a storage array for holding the addresses is arranged to hold addresses for four activity levels for each process.
Abstract: Several I/O channel processes time share a data pipeline processor. For each stage of the pipeline, there is a control memory and means for shifting an address from memory to memory as a process in the pipeline proceeds from stage to stage. The number of processes is greater than the number of pipeline stages, and storage is provided for the data and for the addresses while a process is out of the pipeline, waiting to be re-entered for a next pass. A storage array for holding the addresses is arranged to hold addresses for four activity levels for each process. While an address is held in the array it can be modified for the next pass through the pipeline or the process can be switched from a lower priority level activity to a higher level activity.
01 Jan 1982
TL;DR: A new architecture is developed to realize the overlap-save method using one FNT and several inverse FNTS of 128 points to alleviate the usual dynamic range limitation inFNTS of long transform lengths.
Abstract: A parallel architecture for computation of the linear convolution of two sequences of arbitrary lengths using the Fermat number transform (FNT) is described. In particular a pipeline structure is designed to compute a 128-point FNT. In this FNT, only additions and bit rotations are required. A standard barrel shifter circuit is modified so that it performs the required bit rotation operation. The overlap-save method is generalized for the FNT to compute a linear convolution of arbitrary length. A parallel architecture is developed to realize this type of overlap-save method using one FNT and several inverse FNTs of 128 points. The generalized overlap save method alleviates the usual dynamic range limitation in FNTs of long transform lengths. Its architecture is regular, simple, and expandable, and therefore naturally suitable for VLSI implementation.
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TL;DR: In this paper, a beam-on-elastic foundation approach was used for the analysis of buried pipelines subjected to longitudinal soil strain resulting from earthquakes or man-made underground explosions, and the effects of this soil strain on the axial strain in the pipeline and relative displacement at the pipeline joints were determined using a beam on elastic foundation approach.
Abstract: A technique for the analysis of buried pipelines subjected to longitudinal soil strain resulting from earthquakes or manmade underground explosions is presented. The effects of this soil strain on the axial strain in the pipeline as well as relative displacement at the pipeline joints are determined using a beam on elastic foundation approach. The pipeline is assumed to be straight and of prismatic cross section. The pipeline, pipeline joints and surrounding soil are assumed to behave as linear elastic materials. Non-dimensional curves are presented relating pipeline strains and relative joint displacement to the relative stiffness of the soil, joint and pipeline.
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TL;DR: In this article, a continuation technique is developed to solve convergence problems in a general pipeline and riser model with twist, and several three-dimensional pipeline problems are used to illustrate the model.
Abstract: Several three-dimensional pipeline problems are used to illustrate a general pipeline and riser model with twist. A continuation technique is developed to solve convergence problems. Suitable stiff numerical methods are reviewed for general applications. 14 refs.
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TL;DR: The design of an interesting special-purpose chip implementing a dynamic pipeline bracket counter, where each stage makes use of a PLA to carry out the counting function and each stage can count synchronously, thus speeding up the counting operation.
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TL;DR: In this article, a methodology was developed to calculate the dynamic probabilistic movement and resulting stresses for marine pipelines subjected to storm waves, where a directional wave spectrum was used with a Fourier series expansion to simulate short-crested waves and calculate their loads on the pipeline.
01 Jun 1982
TL;DR: The idea set forth is for all the information that allows for a highly accurate prediction of branches to be kept in a generalized table.
Abstract: The idea set forth is for all the information that allows for a highly accurate prediction of branches to be kept in a generalized table.
01 Jan 1982
TL;DR: A new, distributed processing architecture using three microcomputers in a pipeline configuration is proposed for the efficient execution of a broad class of advanced manipulator control algorithms that will facilitate the implementation of advanced control strategies in industrial robots at a competitive cost.
Abstract: Summary form only given. A new, distributed processing architecture using three microcomputers in a pipeline configuration is proposed for the efficient execution of a broad class of advanced manipulator control algorithms. This design will facilitate the implementation of advanced control strategies in industrial robots at a competitive cost. A simple example illustrates the advantages of the pipeline architecture over existing solutions.
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01 May 1982
TL;DR: Recent advances in technology of VLSI circuits enable economical hardware implementation of highly sophisticated signal processing algorithms that provides the capability of realising a signal processor with uniform hardware for wide real-time applications.
Abstract: Recent advances in technology of VLSI circuits enable economical hardware implementation of highly sophisticated signal processing algorithms. This provides the capability of realising a signal processor with uniform hardware for wide real-time applications. The adaption of the VLSI circuits to special application is possible by appropriate microprograms. The processor speed is determined by the arithmetic unit, particularly if floating point arithmetic is necessary. The processing speed can be increased by decreasing the operation time of the arithmetic unit and by the use of several adders, several multipliers, multiport memory and pipeline technique.