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Pipeline (computing)

About: Pipeline (computing) is a research topic. Over the lifetime, 26760 publications have been published within this topic receiving 204305 citations. The topic is also known as: data pipeline & computational pipeline.


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Patent
Robert G. Duncan1
04 Oct 1995
TL;DR: In this paper, a programmable logic device (PLD) for implementing pipelined designs is described, which comprises registers and function generators arranged along a line in a first direction.
Abstract: A programmable logic device (PLD) for implementing pipelined designs is described. A pipeline array of registers and function generators, comprises registers and function generators arranged along a line in a first direction, the first direction being a direction of propagation of data signals, and registers and function generators arranged along a line in a second direction, the second direction being a direction of propagation of carry signals and control signals. Each of said function generators is operatively connected by routing resources to at least two of the registers within the pipeline array. A synchronization ring of the PLD comprises shift registers, each of the shift registers being programmable such that its bit length can be adjusted from one bit to a predefined maximum number of bits. The synchronization ring surrounds and is operatively connected by routing resources to the pipeline array. An Input/Output (I/O) ring of the PLD comprises programmable logic resources for processing signals entering and exiting the PLD. The I/O ring surrounds and is operatively connected by routing resources to the synchronization ring.

67 citations

Journal ArticleDOI
01 Feb 2011
TL;DR: To eliminate the read-only memories used to store the twiddle factors, the proposed architecture applies a reconfigurable complex multiplier and bit-parallel multipliers to achieve a ROM-less FFT/IFFT processor, thus consuming lower power than the existing works.
Abstract: 4G and other wireless systems are currently hot topics of research and development in the communication field. Broadband wireless systems based on orthogonal frequency division multiplexing (OFDM) often require an inverse fast Fourier transform (IFFT) to produce multiple subcarriers. In this paper, we present the efficient implementation of a pipeline FFT/IFFT processor for OFDM applications. Our design adopts a single-path delay feedback style as the proposed hardware architecture. To eliminate the read-only memories (ROM's) used to store the twiddle factors, the proposed architecture applies a reconfigurable complex multiplier and bit-parallel multipliers to achieve a ROM-less FFT/IFFT processor, thus consuming lower power than the existing works. The design spends about 33.6K gates, and its power consumption is about 9.8mW at 20MHz.

67 citations

Patent
Reynold V. D'Sa1, Rebecca E. Hebda1, Stavros Kalafatis1, Alan B. Kyker1, Robert B. Chaput1 
20 Feb 1998
TL;DR: In this paper, an instruction pipeline in a microprocessor is described, which includes a plurality of pipeline units, each of which is a source of at least some of the instructions for the pipeline.
Abstract: An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the plurality of pipeline units processing a plurality of instructions. At least two of the plurality of pipeline units are a source of at least some of the instructions for the pipeline. The pipeline further includes at least two speculative return address stacks, each of the speculative return address stacks coupled is coupled to at least one of the instruction source units. Each of the speculative return return address stacks are capable of storing at least two speculative return addresses.

67 citations

Journal ArticleDOI
TL;DR: A multi-objective optimization model in optimizing the operation of natural gas pipeline networks is presented and a set of Pareto optimal points from which a decision maker can select a specific preferred solution is obtained.

67 citations

Proceedings ArticleDOI
07 Nov 2005
TL;DR: The goal of this paper is to further reduce simulation time for architecture design space exploration by finding similarity between benchmarks and program inputs at the level of samples, and shows that this provides approximately the same accuracy as the SimPoint sampling approach while reducing the number of simulated instructions by a factor of 1.5.
Abstract: Modern architecture research relies heavily on detailed pipeline simulation. Simulating the full execution of an industry standard benchmark can take weeks to complete. Simulating the full execution of the whole benchmark suite for one architecture configuration can take months. To address this issue researchers have examined using targetted sampling based on phase behavior to significantly reduce the simulation time of each program in the benchmark suite. However, even with this sampling approach, simulating the full benchmark suite across a large range of architecture designs can take days to weeks to complete. The goal of this paper is to further reduce simulation time for architecture design space exploration. We reduce simulation time by finding similarity between benchmarks and program inputs at the level of samples (100M instructions of execution). This allows us to use a representative sample of execution from one benchmark to accurately represent a sample of execution of other benchmarks and inputs. The end result of our analysis is a small number of sample points of execution. These are selected across the whole benchmark suite in order to accurately represent the complete simulation of the whole benchmark suite for design space exploration. We show that this provides approximately the same accuracy as the SimPoint sampling approach while reducing the number of simulated instructions by a factor of 1.5.

67 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202218
20211,066
20201,556
20191,793
20181,754
20171,548