Topic
Pipeline (computing)
About: Pipeline (computing) is a research topic. Over the lifetime, 26760 publications have been published within this topic receiving 204305 citations. The topic is also known as: data pipeline & computational pipeline.
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TL;DR: Results show that simultaneous batch injections lead to a better use of the pipeline transport capacity and a substantial reduction on the overall time needed to meet depot demands.
66 citations
TL;DR: In this paper, a study of pipeline network planned in the Humber region of the UK is presented, where steady state process simulation models of the CO 2 transport pipeline network were developed using Aspen HYSYS®.
66 citations
05 Feb 1998
TL;DR: This single-ended 12b 20 MSample/s pipeline ADC has good performance for Nyquist frequency inputs and a novel input common-mode feedback technique in the S/H stage.
Abstract: This paper describes a fully monolithic 12-bit, 20 Msample/s, A/D converter. A power dissipation of 250 mW from a single 5 V supply is achieved using a radix=2 pipeline architecture. Linearity and full-scale errors are removed through self-calibration and digital correction with on-chip circuitry. A novel single-ended to differential sample and hold stage is proven to have very good single-ended input performance up to the Nyquist frequency. The total silicon area is 3.2/spl times/3.1 mm/sup 2/ in a 0.7 /spl mu/m CMOS process. Several circuit techniques used in this design together with experimental results are presented.
66 citations
17 Sep 2002
TL;DR: This paper applies static program analysis methods to determine an upper bound for the WCET, and believes to be the first to have developed a tool that implements these techniques for all the features of a real-life, non-trivial processor, the Motorola ColdFire 5307.
Abstract: In hard real-time systems, the worst-case execution times of programs must be known. Obtaining safe upper bounds for these times by measuring actual executions is rarely possible, since the worst case input is normally not known. We apply static program analysis methods to determine an upper bound for the WCET. While this approach is not new, we believe to be the first to have developed a tool that implements these techniques for all the features of a real-life, non-trivial processor, the Motorola ColdFire 5307. Our tool is, to the best of our knowledge, the first one that can determine a safe and rather precise WCET bound for a processor that has caches and pipelines and performs branch prediction and instruction prefetching.Our approach to use a pipeline model in the analysis of the processor behavior opens up new perspectives towards a generative analysis approach and can prove helpful in investigating other processor properties. The emphasis of this paper is on the modeling of the pipeline behavior as input to the derivation of a pipeline analysis.
66 citations
20 Oct 1999
TL;DR: This work discusses the design and implementation of a high-speed, low power 1024-point pipeline FFT processor, which is efficient in terms of power consumption and chip area.
Abstract: We discuss the design and implementation of a high-speed, low power 1024-point pipeline FFT processor. Key features are flexible internal data length and a novel processing element. The FFT processor, which is implemented in a standard 0.35 /spl mu/m CMOS process, is efficient in terms of power consumption and chip area.
65 citations