Pipeline (computing)

About: Pipeline (computing) is a research topic. Over the lifetime, 26760 publications have been published within this topic receiving 204305 citations. The topic is also known as: data pipeline & computational pipeline.

Computing machine having improved computing architecture and related system and method

Abstract: A computing machine includes a first buffer and a processor coupled to the buffer. The processor executes an application, a first data-transfer object, and a second data-transfer object, publishes data under the control of the application, loads the published data into the buffer under the control of the first data-transfer object, and retrieves the published data from the buffer under the control of the second data-transfer object. Alternatively, the processor retrieves data and loads the retrieved data into the buffer under the control of the first data-transfer object, unloads the data from the buffer under the control of the second data-transfer object, and processes the unloaded data under the control of the application. Where the computing machine is a peer-vector machine that includes a hardwired pipeline accelerator coupled to the processor, the buffer and data-transfer objects facilitate the transfer of data between the application and the accelerator.

Intermediate Palomar Transient Factory: Realtime Image Subtraction Pipeline

Abstract: A fast-turnaround pipeline for realtime data reduction plays an essential role in discovering and permitting follow-up observations to young supernovae and fast-evolving transients in modern time-domain surveys. In this paper, we present the realtime image subtraction pipeline in the intermediate Palomar Transient Factory. By using high-performance computing, efficient databases, and machine-learning algorithms, this pipeline manages to reliably deliver transient candidates within 10 minutes of images being taken. Our experience in using high-performance computing resources to process big data in astronomy serves as a trailblazer to dealing with data from large-scale time-domain facilities in the near future.

Low cost DNA data storage using photolithographic synthesis and advanced information reconstruction and error correction.

Abstract: Due to its longevity and enormous information density, DNA is an attractive medium for archival storage. The current hamstring of DNA data storage systems—both in cost and speed—is synthesis. The key idea for breaking this bottleneck pursued in this work is to move beyond the low-error and expensive synthesis employed almost exclusively in today’s systems, towards cheaper, potentially faster, but high-error synthesis technologies. Here, we demonstrate a DNA storage system that relies on massively parallel light-directed synthesis, which is considerably cheaper than conventional solid-phase synthesis. However, this technology has a high sequence error rate when optimized for speed. We demonstrate that even in this high-error regime, reliable storage of information is possible, by developing a pipeline of algorithms for encoding and reconstruction of the information. In our experiments, we store a file containing sheet music of Mozart, and show perfect data recovery from low synthesis fidelity DNA. The current bottleneck for DNA data storage systems is the cost and speed of synthesis. Here, the authors use inexpensive, massively parallel light-directed synthesis and correct for a high error rate with a pipeline of encoding and reconstruction algorithms.

Pipelined memory having synchronous and asynchronous operating modes

Abstract: A pipelined memory (20) has a synchronous operating mode and an asynchronous operating mode. The memory (20) includes output registers (34) and output enable registers (48) which are used to electrically switch between the asynchronous operating mode and the synchronous operating mode. In addition, in the synchronous operating mode, the depth of pipelining can be changed between a three stage pipeline and a two stage pipeline. By changing the depth of pipelining, the memory (20) can operate using a greater range of clock frequencies. In addition, the operating frequency can be changed to facilitate testing and debugging of the memory (20).

Apparatus for superscalar instruction predecoding using cached instruction lengths

Abstract: A method and apparatus for eliminating the delay in a parallel processing pipeline. In a parallel processing pipeline system, a circuitry is provided to determine the length and align two instructions in parallel. Parallel decoding circuitry is provided for decoding and executing the two instructions. A branch prediction cache stores the target instruction and next sequential instruction, and is tagged by the address of the branch instruction, as in the prior art. In addition, however, the branch prediction cache also stores the length of the first and second instructions and the address of the second instruction. This additional data allows the target and next sequential instructions to be directly aligned and presented to the parallel decoding circuits without waiting for a calculation of their lengths and starting addresses.