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Pipeline (computing)

About: Pipeline (computing) is a research topic. Over the lifetime, 26760 publications have been published within this topic receiving 204305 citations. The topic is also known as: data pipeline & computational pipeline.


Papers
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Proceedings ArticleDOI
01 Oct 2017
TL;DR: The first photometric registration pipeline for Mixed Reality based on high quality illumination estimation using convolutional neural networks (CNNs) is presented, and experimental results show that the proposed method yields highly accurate estimates for photo-realistic augmentations.
Abstract: This paper presents the first photometric registration pipeline for Mixed Reality based on high quality illumination estimation using convolutional neural networks (CNNs). For easy adaptation and deployment of the system, we train the CNNs using purely synthetic images and apply them to real image data. To keep the pipeline accurate and efficient, we propose to fuse the light estimation results from multiple CNN instances and show an approach for caching estimates over time. For optimal performance, we furthermore explore multiple strategies for the CNN training. Experimental results show that the proposed method yields highly accurate estimates for photo-realistic augmentations.

57 citations

Patent
G. Glenn Henry1, Gerard M. Col1, Colin Eddy1, Rodney E. Hooker1, Terry Parks1 
06 Apr 2012
TL;DR: In this article, a microprocessor instruction translator translates a conditional load instruction into at least two microinstructions, and an out-of-order execution pipeline executes the instructions.
Abstract: A microprocessor instruction translator translates a conditional load instruction into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives source operands from the source registers of a register file and responsively generates a first result using the source operands. To execute a second the microinstruction, an execution unit receives a previous value of the destination register and the first result and responsively reads data from a memory location specified by the first result and provides a second result that is the data if a condition is satisfied and that is the previous destination register value if not. The previous value of the destination register comprises a result produced by execution of a microinstruction that is the most recent in-order previous writer of the destination register with respect to the second microinstruction.

57 citations

Journal ArticleDOI
TL;DR: In this article, a semi-Markov model of the system operation processes is proposed and its selected characteristics are determined, and the mean values of the pipeline system operation process unconditional sojourn times in particular operation states are found and applied to determining this process transient probabilities in these states.

57 citations

Patent
03 Oct 2006
TL;DR: In this article, the rotor that includes the induction magnets is deployed within the main flow passage of the pipeline and thereby sealed within the pipeline, and he induction coil assembly is deployed outside the pipeline such that the fluid is sealed within a pipeline away from the induction coils.
Abstract: The hydroelectric generator of the present invention provides a pre-sealed, watertight device in which the rotor that includes the induction magnets is deployed within the main flow passage of the pipeline and thereby sealed within the pipeline, and he induction coil assembly is deployed outside of the pipeline such that the fluid is sealed within the pipeline away from the induction coils.

57 citations

Proceedings ArticleDOI
11 Aug 2002
TL;DR: This implementation of an optical flow algorithm on a pipeline image processor achieves very low computation delays that allow it to operate at standard video frame-rate and resolutions.
Abstract: This paper presents the implementation of an optical flow algorithm on a pipeline image processor The overall optical flow computation method is presented and evaluated on a common set of image sequences. Results are compared to other implementations according to two different error measures. Due to its deterministic architecture, this implementation achieves very low computation delays that allow it to operate at standard video frame-rate and resolutions. It compares favorably to recent implementations in parallel hardware.

57 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202218
20211,066
20201,556
20191,793
20181,754
20171,548