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Pipeline (computing)

About: Pipeline (computing) is a research topic. Over the lifetime, 26760 publications have been published within this topic receiving 204305 citations. The topic is also known as: data pipeline & computational pipeline.


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Proceedings ArticleDOI
07 Apr 1997
TL;DR: In simulations using hSpice, the throughput of the asynchronous circuit matches that of a two-phase clocked design and from test measurements, it is estimated that the internal FIFO stages could support a maximum throughput from 930 million data items per second for the slowest of the 50 chips to 1126 million persecond for the fastest chip.
Abstract: We describe a high-speed FIFO circuit intended to compare the performance of an asynchronous FIFO with that of a clocked shift register using the same data path. The FIFO uses a pulse-like protocol to advance data along the pipeline. Use of this protocol requires careful management of circuit delays within its control circuits, as well as in the coordination of control signals with movement of bundled data. In simulations using hSpice, the throughput of the asynchronous circuit matches that of a two-phase clocked design. We fabricated 50 parts through MOSIS using their 0.6 micron design rules. We estimate from test measurements that the internal FIFO stages could support a maximum throughput from 930 million data items per second for the slowest of the 50 chips to 1126 million per second for the fastest chip. All 50 samples operated correctly as 3.3 V nominal Vdd varied from 1.67 V to over 4.8 V, with corresponding changes in operating speed and power as the supply voltage changed.

55 citations

Journal ArticleDOI
TL;DR: PynPoint as mentioned in this paper is a data-reduction pipeline for processing and analysis of high-contrast imaging data obtained with pupil-stabilized observations, which is particularly suitable for the 3-5 μm wavelength range where typically thousands of frames have to be processed and an accurate subtraction of the thermal background emission is critical.
Abstract: Context. The direct detection and characterization of planetary and substellar companions at small angular separations is a rapidly advancing field. Dedicated high-contrast imaging instruments deliver unprecedented sensitivity, enabling detailed insights into the atmospheres of young low-mass companions. In addition, improvements in data reduction and point spread function (PSF)-subtraction algorithms are equally relevant for maximizing the scientific yield, both from new and archival data sets.Aims. We aim at developing a generic and modular data-reduction pipeline for processing and analysis of high-contrast imaging data obtained with pupil-stabilized observations. The package should be scalable and robust for future implementations and particularly suitable for the 3–5 μ m wavelength range where typically thousands of frames have to be processed and an accurate subtraction of the thermal background emission is critical.Methods. PynPoint is written in Python 2.7 and applies various image-processing techniques, as well as statistical tools for analyzing the data, building on open-source Python packages. The current version of PynPoint has evolved from an earlier version that was developed as a PSF-subtraction tool based on principal component analysis (PCA).Results. The architecture of PynPoint has been redesigned with the core functionalities decoupled from the pipeline modules. Modules have been implemented for dedicated processing and analysis steps, including background subtraction, frame registration, PSF subtraction, photometric and astrometric measurements, and estimation of detection limits. The pipeline package enables end-to-end data reduction of pupil-stabilized data and supports classical dithering and coronagraphic data sets. As an example, we processed archival VLT/NACO L ′ and M ′ data of β Pic b and reassessed the brightness and position of the planet with a Markov chain Monte Carlo analysis; we also provide a derivation of the photometric error budget.

55 citations

Proceedings ArticleDOI
01 Jun 1996
TL;DR: A new optimization technique called architectural retiming is presented which is able to improve the performance of many latency-constrained circuits by increasing the number of registers on the latency- Constrained path while preserving the functionality and latency of the circuit.
Abstract: This paper presents a new optimization technique called architectural retiming which is able to improve the performance of many latency-constrained circuits. Architectural retiming achieves this by increasing the number of registers on the latency-constrained path while preserving the functionality and latency of the circuit. This is done using the concept of a negative register, which can be implemented using precomputation and prediction. We use the name architectural retiming since it both reschedules operations in time and modifies the structure of the circuit to preserve its functionality. We illustrate the use of architectural retiming on two realistic examples and present performance improvement results for a number of sample circuits.

55 citations

Proceedings ArticleDOI
19 Mar 2006
TL;DR: The characterizations done in this paper are driven by 'interval analysis', an analytical approach that models superscalar processor performance as a sequence of inter-miss intervals.
Abstract: Despite years of study, branch mispredictions remain as a significant performance impediment in pipelined superscalar processors. In general, the branch misprediction penalty can be substantially larger than the frontend pipeline length (which is often equated with the misprediction penalty). We identify and quantify five contributors to the branch misprediction penalty: (i) the frontend pipeline length, (ii) the number of instructions since the last miss event (branch misprediction, I-cache miss, long D-cache miss)-this is related to the burstiness of miss events, (iii) the inherent ILP of the program, (iv) the functional unit latencies, and (v) the number of short (LI) D-cache misses. The characterizations done in this paper are driven by 'interval analysis', an analytical approach that models superscalar processor performance as a sequence of inter-miss intervals.

55 citations

Proceedings ArticleDOI
18 Jun 2008
TL;DR: Simulations indicate that the architecture and circuitry are well suited to scaling below 90 nm, and the prototype ADC, implemented in 0.18 mum CMOS, provides 10.65 ENOB at 250 MS/s while consuming only 140 mW, yielding an exceptionally low FoM of 0.28 pJ/conversion-step.
Abstract: A 13-bit ADC is implemented using a novel charge-domain architecture. Enhanced bucket-brigade circuitry and a tapered charge pipeline provide precision charge-domain operation in a standard CMOS process, while eliminating the need for signal-path op-amps. The prototype ADC, implemented in 0.18 mum CMOS, provides 10.65 ENOB at 250 MS/s while consuming only 140 mW, yielding an exceptionally low FoM of 0.28 pJ/conversion-step. Simulations indicate that the architecture and circuitry are well suited to scaling below 90 nm.

55 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202218
20211,066
20201,556
20191,793
20181,754
20171,548