Pipeline (computing)

About: Pipeline (computing) is a research topic. Over the lifetime, 26760 publications have been published within this topic receiving 204305 citations. The topic is also known as: data pipeline & computational pipeline.

High-level synthesis of asynchronous systems by data-driven decomposition

Abstract: We present a method for decomposing a high-level program description of a circuit into a system of concurrent modules that can each be implemented as asynchronous pre-charge half-buffer pipeline stages (the circuits used in the asynchronous R3000 MIPS microprocessor). We apply it to designing the instruction fetch of an asynchronous 8051 microcontroller, with promising results. We discuss new clustering algorithms that will improve the performance figures further.

Pipelined data parallel algorithms-I: concept and modeling

Abstract: The basic concept of pipelined data-parallel algorithms is introduced by contrasting the algorithms with other styles of computation and by a simple example (a pipeline image distance transformation algorithm). Pipelined data-parallel algorithms are a class of algorithms which use pipelined operations and data level partitioning to achieve parallelism. Applications which involve data parallelism and recurrence relations are good candidates for this kind of algorithm. The computations are ideal for distributed-memory multicomputers. By controlling the granularity through data partitioning and overlapping the operations through pipelining, it is possible to achieve a balanced computation on multicomputers. An analytic model is presented for modeling pipelined data-parallel computation on multicomputers. The model uses timed Petri nets to describe data pipelining operations. As a case study, the model is applied to a pipelined matrix multiplication algorithm. Predicted results match closely with the measured performance on a 64-node NCUBE hypercube multicomputer. >

A power-aware scalable pipelined Booth multiplier

Abstract: Energy-efficient power-aware design is highly desirable for DSP functions that encounter a wide diversity of operating scenarios in battery-powered wireless sensor network systems Addressing this issue, this paper presents a low-power power-aware scalable pipelined Booth multiplier that makes use of the sharing common functional unit, ensemble of optimized Wallace-trees and a 4-bit array-based adder-tree for DSP applications Our multiplier detects the input operands for their dynamic range and accordingly implements a 16-bit, 8-bit or 4-bit multiplication operation "The multiplication mode is determined by the dynamic-range detection unit, which generates and dispatches the control signals for the pipeline stages For the 8-bit and 4-bit computations, the proposed Booth multiplier leads to a 29% and 58% power consumption reduction over a non-scalable Booth multiplier, respectively The proposed scalable pipelined Booth multiplier proves to be globally 20% more power efficient than a non-scalable pipelined Booth multiplier, and also it has fast speed due to pipelining

Crack detection in pipelines using multiple electromechanical impedance sensors

Abstract: An extensive network of pipeline systems is used to transport and distribute national energy resources that heavily influence a nation's economy. Therefore, the structural integrity of these pipeline systems must be monitored and maintained. However, structural damage detection remains a challenge in pipeline engineering. To this end, this study developed a modified electromechanical impedance (EMI) technique for crack detection that involves fusing information from multiple sensors. We derived a new damage-sensitive feature factor based on a pipeline EMI model that considers the influence of the bonding layer between the EMI sensors and pipeline. We experimentally validated the effectiveness of the proposed method. Finally, we used a damage index—root mean square deviation—to examine the degree and position of crack damage in a pipeline.