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Pipeline (computing)

About: Pipeline (computing) is a research topic. Over the lifetime, 26760 publications have been published within this topic receiving 204305 citations. The topic is also known as: data pipeline & computational pipeline.


Papers
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Patent
04 Apr 2000
TL;DR: In this paper, a memory interface controller includes a read buffer to pipeline data from a synchronous dynamic random access memory (DRAM) in response to a plurality of consecutive SDRAM burst read requests.
Abstract: A memory interface controller includes a read buffer to pipeline data from a synchronous dynamic random access memory (DRAM) in response to a plurality of consecutive SDRAM burst read requests, a write buffer to store write data, an exclusive or (XOR) engine to XOR the write data with the data from the read buffer, and a write interface to write resulting data from XORing the write data and the data from the read buffer to the synchronous DRAM. Data is pipelined in the read buffer by repeatedly issuing an SDRAM burst read request before data is transferred out of the synchronous DRAM in response to a previous SDRAM burst read request until a desired amount of data is stored in the read buffer. The memory interface controller thus can perform an external read-modify-write cycle for the synchronous DRAM. The synchronous DRAM can serve as a RAID (Redundant Array s of Inexpensive Disks) memory.

49 citations

Patent
11 Aug 1980
TL;DR: In this article, a method and apparatus for detecting and locating holidays in an insulating coating of a subterranean pipeline is described, where an alternating current is induced in the portion of the pipeline being surveyed, and the electrical current signal is displayed to provide an indication of the location and magnitude of the holiday.
Abstract: A method and apparatus are provided for detecting and locating holidays in an insulating coating of a subterranean pipeline. An alternating current is induced in the portion of the pipeline being surveyed. The pipeline is tracked by sensing the normal electromagnetic field generated by the current flowing in the pipeline. Leakage current indicative of the location and magnitude of a holiday in the pipeline coating is sensed by a pair of coil members adapted to be located above the ground on opposite sides of a vertical plane including the longitudinal axis of the pipeline with the central axes of the coil members being oriented generally parallel to the central axis of the pipeline, whereby an electrical current signal is induced in the pair of coil members by an electromagnetic field generated by the leakage current. The electrical current signal is displayed to provide an indication of the location and magnitude of the holiday.

49 citations

Patent
13 Jul 1990
TL;DR: In this article, a processor pipeline control system and method provides a complete set of very simple and very fast pipeline control signals encompassing stalls and interrupts, where exceptional conditions are signaled within the processor by deasserting the LoadX signals required by that exception.
Abstract: A processor pipeline control system and method provides a complete set of very simple and very fast pipeline control signals encompassing stalls and interrupts. Each pipeline stage has associated with it a signal called "LoadX", where X is the pipeline stage name, e.g., LoadID. Instead of signalling exceptional conditions in terms of the event, e.g., "cache miss", exceptional conditions are signalled within the processor by deasserting the LoadX signals required by that exception. When the pipeline control for one pipestage is deasserted, in order to prevent previous instructions from entering the stalled pipestage, the detector of the exceptional condition must deassert all LoadX control signals for stages previous to X as well.

49 citations

Journal ArticleDOI
TL;DR: A novel 128/256/512/1024/1536/2048-point single-path delay feedback (SDF) pipeline FFT processor for long-term evolution and mobile worldwide interoperability for microwave access systems and formulated a hardware-sharing mechanism to reduce the memory space requirements of the proposed 1536-point FFT computation scheme.
Abstract: Fast Fourier transform (FFT) is widely used in digital signal processing and telecommunications, particularly in orthogonal frequency division multiplexing systems, to overcome the problems associated with orthogonal subcarriers. This paper presents a novel 128/256/512/1024/1536/2048-point single-path delay feedback (SDF) pipeline FFT processor for long-term evolution and mobile worldwide interoperability for microwave access systems. The proposed design employs a low-cost computation scheme to enable 1536-point FFT, which significantly reduces hardware costs as well as power consumption. In conjunction with the aforementioned 1536-point FFT computation scheme, the proposed design included an efficient three-stage SDF pipeline architecture on which to implement a radix-3 FFT. The new radix-3 SDF pipeline FFT processor simplifies its data flow and is easy to control, and the complexity of the resulting hardware is lower than that of existing structures. This paper also formulated a hardware-sharing mechanism to reduce the memory space requirements of the proposed 1536-point FFT computation scheme. The proposed design was implemented using 90 nm CMOS technology. Postlayout simulation results revealed a die area of approximately $1.44 \times 1.44~\mathrm{mm}^{2}$ with power consumption of only 9.3 mW at 40 MHz.

49 citations

Patent
04 May 2001
TL;DR: In this paper, the authors propose a branch prediction apparatus that employs dual call/return stacks to predict return addresses in a microprocessor. But their approach requires the microprocessor to decode the instruction before decoding it to know whether it is actually a return instruction.
Abstract: A branch prediction apparatus that employs dual call/return stacks to predict return addresses in a microprocessor. The apparatus includes a first call/return stack that provides a speculative return address based upon a return instruction hit in a speculative branch target address cache (BTAC) of an instruction cache fetch address prior to decoding of the instruction to know whether it is actually a return instruction. The speculative return address is provided early in the pipeline and the microprocessor speculatively branches to the speculative return address. Later in the pipeline, a second call/return stack provides a non-speculative return address after the instruction is decoded and verified to be a return instruction. A comparator compares the speculative and non-speculative return addresses, and if the two addresses mismatch, the microprocessor branches to the non-speculative return address.

48 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202218
20211,066
20201,556
20191,793
20181,754
20171,548