Pipeline (computing)

About: Pipeline (computing) is a research topic. Over the lifetime, 26760 publications have been published within this topic receiving 204305 citations. The topic is also known as: data pipeline & computational pipeline.

Dual pipeline superscalar reduced instruction set computer system architecture

Abstract: A microprocessor core operating on instructions in a dual six-stage pipeline. Instructions are fetched and decoded by an instruction scheduling unit which includes a queuing stage for facilitating conditional branch operations. Instructions can be executed in five execution units including a load/store/add unit, an ALU unit, a shift/multiply unit, a branch unit, and a coprocessor which interfaces with the microprocessor core. Exceptions are handled by the coprocessor which includes a plurality of registers and a multiple entry translation lookaside buffer and an exception program counter. When an exception is detected the coprocessor loads the exception program counter with a restart address where execution can resume after the exception is serviced, the plurality of registers being used during the exception processing. One of the registers is a circulate mask register which is used by the coprocessor in executing an Add with Circular Mask instruction in which an immediate field of the instruction is sign-extended and added to the contents of a general register, the result being masked with the extended value in the circular mask register.

Modeling and optimization of the lightweight HIGHT block cipher design with FPGA implementation

Abstract: The growth of low-resource devices has increased rapidly in recent years. Communication in such devices presents two challenges: security and resource limitation. Lightweight ciphers, such as HIGHT cipher, are encryption algorithms targeted for low resource systems. Designing lightweight ciphers in reconfigurable platform e.g., field-programmable gate array provides speedup as well as flexibility. The HIGHT cipher consists of simple operations and provides adequate security level. The objective of this research work is to design, optimize, and model FPGA implementation of the HIGHT cipher. Several optimized designs are presented to minimize the required hardware resources and energy including the scalar and pipeline ones. Our analysis shows that the scalar designs have smaller area and power dissipation, whereas the pipeline designs have higher throughput and lower energy. Because of the fact that obtaining the best performance out of any implemented design mainly requires balancing the design area and energy, our experimental results demonstrate that it is possible to obtain such optimal performance using the pipeline design with two and four rounds per stage as well as with the scalar design with one and eight rounds. Comparing the best implementations of pipeline and scalar designs, the scalar design requires 18% less resources and 10% less power, while the pipeline design has 18 times higher throughput and 60% less energy consumption. Copyright © 2016 John Wiley & Sons, Ltd.

Data prefetch technique using prefetch cache, micro-TLB, and history file

Abstract: A memory cache method and apparatus with two memory execution pipelines, each having a translation lookaside buffer (TLB). Memory instructions are executed in the first pipeline ( 324 ) by searching a data cache ( 310 ) and a prefetch cache ( 320 ). A large data TLB ( 330 ) provides memory for storing address translations for the first pipeline ( 324 ) A second pipeline ( 328 ) executes memory instructions by accessing the prefetch cache ( 320 ). A second micro-TLB ( 340 ) is associated with the second pipeline ( 328 ). It is loaded in anticipation of data that will be referenced by the second pipeline ( 328 ). A history file ( 360 ) is also provided to retain information on previous instructions to aid in deciding when to prefetch data. Prefetch logic ( 370 ) determines when to prefetch data, and steering logic ( 380 ) routes certain instructions to the second pipeline ( 328 ) to increase system performance.

Real-time pipeline fast fourier transform processors

Abstract: A real-time pipeline processor, which is particularly suited for VLSI implementation, is based on a hardware oriented radix-22 algorithm derived by integrating a twiddle factor decomposition technique in a divide and conquer approach. The radix-22 algorithm has the same multiplicative complexity as a radix-4 algorithm, but retains the butterfly structure of a radix-2 algorithm. A single-path delay-feedback architecture is used in order to exploit the spatial regularity in the signal flow graph of the algorithm. For a length-N DFT transform, the hardware requirements of the processor proposed by the present invention is minimal on both dominant components: Log4N-1 complex multipliers, and N-1 complex data memory.

Lookahead register value generator and a superscalar microprocessor employing same

Abstract: A lookahead register value generator is provided which is configured to maintain lookahead values for registers with respect to instructions decoded in prior clock cycles. Each clock cycle, an instruction having one of these registers and an operand may receive a corresponding operand value generated using the values stored in these lookahead registers while the associated instruction is in the decode stage of the instruction processing pipeline. If the operand value is an address, the value may be used to fetch operand data residing at the address before the instruction arrives in the execute stage of the instruction processing pipeline. Additionally, the lookahead register value generator generates operand values for a second instruction which is dependent upon a concurrently decoded first instruction, thereby removing the dependency therebetween. Instructions for which the values are generated may execute concurrently, as opposed to serially executing.