Pipeline (computing)

About: Pipeline (computing) is a research topic. Over the lifetime, 26760 publications have been published within this topic receiving 204305 citations. The topic is also known as: data pipeline & computational pipeline.

FPGA-Based Dynamically Reconfigurable SQL Query Processing

Abstract: In this article, we propose an FPGA-based SQL query processing approach exploiting the capabilities of partial dynamic reconfiguration of modern FPGAs. After the analysis of an incoming query, a query-specific hardware processing unit is generated on the fly and loaded on the FPGA for immediate query execution. For each query, a specialized hardware accelerator pipeline is composed and configured on the FPGA from a set of presynthesized hardware modules. These partially reconfigurable hardware modules are gathered in a library covering all major SQL operations like restrictions and aggregations, as well as more complex operations such as joins and sorts. Moreover, this holistic query processing approach in hardware supports different data processing strategies including row- as column-wise data processing in order to optimize data communication and processing. This article gives an overview of the proposed query processing methodology and the corresponding library of modules. Additionally, a performance analysis is introduced that is able to estimate the processing time of a query for different processing strategies and different communication and processing architecture configurations. With the help of this performance analysis, architectural bottlenecks may be exposed and future optimized architectures, besides the two prototypes presented here, may be determined.

Detection and location of a leak in a gas‐transport pipeline by a new acoustic method

Abstract: A new method is described for detecting and locating a leak in a gas transport pipeline lying between two pump stations by an indirect acoustic method. The basic concept is to treat the pipeline as an acoustic tube (similar to a wind instrument), and to estimate the impulse response of the acoustic wave in the pipeline solely from the acoustic signal detected at two terminal sites in the pipeline. The test signal introduced at the input site is only acoustic noise; pipeline operation need not be interrupted. If a leak occurs in the pipeline, the impulse response of the acoustic wave in the pipeline has a sharp pulse or a step at a certain time that can be directly related to the site of the leak. Using the mathematical model of the pipeline acoustics, i.e., the wave equation, a theoretical basis is developed to explain how and why the leak can be detected and located. Experiments carried out in the laboratory under conditions comparable to realistic field conditions demonstrate the validity of the proposed detection method.

WavePipe: parallel transient simulation of analog and digital circuits on multi-core shared-memory machines

Abstract: While the emergence of multi-core shared-memory machines offers a promising computing solution to ever complex chip design problems, new parallel CAD methodologies must be developed to gain the full benefit of these increasingly parallel computing systems. We present a parallel transient simulation methodology and its multi-threaded implementation for general analog and digital ICs. Our new approach, Waveform Pipelining (abbreviated as WavePipe), exploits coarsegrained application-level parallelism by simultaneously computing circuit solutions at multiple adjacent time points in a way resembling hardware pipelining. There are two embodiments in WavePipe: backward and forward pipelining schemes. While the former creates independent computing tasks that contribute to a larger future time step by moving backwards in time, the latter performs predictive computing along the forward direction of the time axis. Unlike existing relaxation methods, WavePipe facilitates parallel circuit simulation without jeopardying convergence and accuracy. As a coarse-grained parallel approach, WavePipe not only requires low parallel programming effort, more importantly, it creates new avenues to fully utilize increasingly parallel hardware by going beyond conventional finer grained parallel device model evaluation and matrix solutions.

Parallel apparatus for high-speed, highly compressed LZ77 tokenization and Huffman encoding for deflate compression

Abstract: Parallel compression is performed on an input data stream by processing circuitry. The processing circuitry includes hashing circuitry, match engines, pipeline circuitry and a match selector. The hashing circuitry identifies multiple locations in one or more history buffers for searching for a target data in the input data stream. The match engines perform multiple searches in parallel for the target data in the one or more history buffers. The pipeline circuitry performs pipelined searches for multiple sequential target data in the input data stream in consecutive clock cycles. Then the match selector selects a result from the multiple searches and pipelined searches to compress the input data stream.