Pipeline (computing)

About: Pipeline (computing) is a research topic. Over the lifetime, 26760 publications have been published within this topic receiving 204305 citations. The topic is also known as: data pipeline & computational pipeline.

Methods and apparatus for dynamically scaling images

Abstract: An image processing system is disclosed in which the various image processing circuits are arranged in a pipeline such that the output of each circuit is passed on to the next circuit in the pipeline without storing the data between circuits of the pipeline. The individual processing circuits are program-controlled by a common controller in order to properly synchronize various operations such as scanning, compressing, expanding, rescaling, windowing and rotating. The rescaling operation is carried out by executing a sequence of program instructions applying to single pixels, or to single lines of the image. These instructions include deletion, duplication and passing through of the image element. Windowing is provided by inserting start-of-window and end-of-window instructions in the appropriate places in the sequence of rescaling instructions.

DNA Data Storage and Hybrid Molecular–Electronic Computing

Abstract: Moore’s law may be slowing, but our ability to manipulate molecules is improving faster than ever. DNA could provide alternative substrates for computing and storage as existing ones approach physical limits. In this paper, we explore the implications of this trend in computer architecture. We present a computer systems perspective on molecular processing and storage, positing a hybrid molecular–electronic architecture that plays to the strengths of both domains. We cover the design and implementation of all stages of the pipeline: encoding, DNA synthesis, system integration with digital microfluidics, DNA sequencing (including emerging technologies such as nanopores), and decoding. We first draw on our experience designing a DNA-based archival storage system, which includes the largest demonstration to date of DNA digital data storage of over three billion nucleotides encoding over 400 MB of data. We then propose a more ambitious hybrid–electronic design that uses a molecular form of near-data processing for massive parallelism. We present a model that demonstrates the feasibility of these systems in the near future. We think the time is ripe to consider molecular storage seriously and explore system designs and architectural implications.

System and method for a data processing pipeline

Abstract: OF THE DISCLOSURE An electronic data processing pipeline system and method for processing encoded control points representing graphical illustrations. The pipeline comprises a number of separate micro-programmed circuit cards, each of which are programmed to perform a specific processing operation. A command is sent to a matrix maker card which calculates a transformation matrix representing the desired transformation. Electronic representations of control data points are then trasmitted to the pipeline for processing. These control points are 3D points comprising both the vertices which terminate linear edges of the illustration and the control points corresponding to curved edges of the illustration. The control points are then multiplied by the transformation matrix in a vector multiplier circuit card. They are then clipped to the planes of the viewing frustum and are mapped onto the 2D viewing window. The clipped control points are then exploded to generate a plurality of small line segments representing each of the curved edges of the illustration. The appropriate portions of the illustration are rendered as a line drawing and the processed data is converted into a form which is appropriate for scan conversion.

Method of operating a video decoding system

Abstract: A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel. The variable-length decoders operate as part of a pipeline wherein the variable-length decoders alternate, stage-by-stage, decoding macroblocks.

Single chip integrated circuit system architecture for document instruction set computing

Abstract: An improved system utility using pointers and stacks and a method for high level language procedure for representing, storing, retrieving, processing, and/or manipulating documents, said system utilities facilitates compilation, linkage, processing, and management of said high level language procedures. Call, return, and auxiliary stacks are included to store pointers of normal, exceptional/conditional, and alternative operations. A bit mapping logic and smart object memory are used to look ahead, monitor, and predict forthcoming exceptional/conditional operation, a system look-up table further prefetch relevant procedural and data pointers for maintaining pipeline coherence.