Pipeline (computing)

About: Pipeline (computing) is a research topic. Over the lifetime, 26760 publications have been published within this topic receiving 204305 citations. The topic is also known as: data pipeline & computational pipeline.

Implementation of a Clifford Algebra Co-Processor Design on a Field Programmable Gate Array

Abstract: We present the design of a Clifford algebra co-processor and its implementation on a Field Programmable Gate Array (FPGA). To the best of our knowledge this is the first such design developed. The design is scalable in both the Clifford algebra dimension and the bit width of the numerical factors. Both aspects are only limited by the hardware resources. Furthermore, the signature of the underlying vector space can be changed without reconfiguring the FPGA. High calculation speeds are achieved through a pipeline architecture.

A SRAM-based Architecture for Trie-based IP Lookup Using FPGA

Abstract: Internet Protocol (IP) lookup in routers can be implemented by some form of tree traversal. Pipelining can dramatically improve the search throughput. However, it results in unbalanced memory allocation over the pipeline stages. This has been identified as a major challenge for pipelined solutions. In this paper, an IP lookup rate of 325 MLPS (millions lookups per second) is achieved using a novel SRAM-based bidirectional optimized linear pipeline architecture on Field Programmable Gate Array, named BiOLP, for tree-based search engines in IP routers. BiOLP can also achieve a perfectly balanced memory distribution over the pipeline stages. Moreover, by employing caching to exploit the Internet traffic locality, BiOLP can achieve a high throughput of up to 1.3 GLPS (billion lookups per second). It also maintains packet input order, and supports route updates without blocking subsequent incoming packets.

Processor executing plural instruction sets (ISA's) with ability to have plural ISA's in different pipeline stages at same time

Abstract: A method and apparatus for transitioning a processor from a first mode of operation for processing a first instruction set architecture (instruction set) to a second mode of operation for processing a second set instruction set. The method provides that instructions of a first instruction set architecture (instruction set) are processed in a pipelined processor in a first mode of operation, and instructions of a second, different, instruction set, are processed in the pipelined processor in a second, different, mode of operation. While operating in one mode and before a switch to the other mode occurs, the pipeline is loaded with a set of instructions that transition the processor from one mode to the other, wherein the set of instructions are substantially insensitive to the mode that the processor operates in. The processor begins processing the set of instructions while in one mode, and finishes processing the instructions after switching to the other mode, and the set of instructions are held in a permanent memory, and are ready to be executed and do not require decoding. The processor switches mode in response to a mode switch instruction in the pipeline, and the set of instructions follow the mode switch instruction in the pipeline by a spacing which is less than the number of stages in the pipeline. The transition instructions include mode sensitive instructions that follow the mode insensitive instructions, and the mode sensitive instructions enter the pipeline after the mode switch has occurred. Further, the pipeline has alternate front end stages, one operating to decode instructions in one mode of operation, and the other to decode instructions in the other mode of operation. In addition, one of the front end stages translates instructions from one instruction set to another.

Experience with pipelined multiple instruction streams

Abstract: Pipelining has been used to implement efficient, high-speed vector computers. It is also an effective method for implementing multiprocessors. The Heterogeneous Element Processor (HEP) built by Denelcor Incorporated is the first commercially available computer system to use pipelining to implement multiple processes. This paper introduces the architecture and programming environment of the HEP and surveys a range of scientific applications programs for which parallel versions have been produced, tested, and analyzed on this computer. In all cases, the ideal of one instruction completion every pipeline step time is closely approached. Speed limitations in the parallel programs are more often a result of the extra code necessary to ensure synchronization than of actual synchronization lockout at execution time. The pipelined multiple instruction stream architecture is shown to cover a wide range of applications with good utilization of the parallel hardware.

Performance and the i860 microprocessor

Abstract: The internal design of the i860 CPU, which exploits pipelining and parallelism more than previous microprocessors, is described. The i860 uses RISC concepts and memory-performance optimizations in several novel ways. Other innovations include simultaneous floating-point operations similar to digital signal processing, a two-instruction-per-clock mode, fast floating-point pipelines graphics instructions, and high-bandwidth registers and caches on-chip. These features make it one of the fastest single-chip processors available. >