Pipeline (computing)

About: Pipeline (computing) is a research topic. Over the lifetime, 26760 publications have been published within this topic receiving 204305 citations. The topic is also known as: data pipeline & computational pipeline.

Self-calibrating pipelined subranging analog-to-digital converter

Abstract: An approach to A/D converter architecture is based on a "pipelined and subranging" architecture in a converter (3a) which includes a pipeline of elemental stages each of which comprises a low-resolution flash A/D subconverter (12), a D/A converter (14), and a unity-gain buffer (16) providing reference voltage to the next stage. To minimize converter nonlinearity due to component mismatches, a self-calibration technique based on an "interpolation" scheme is used. This technique employs an on-chip A/D converter (32) to provide the reference for calibration and a 100-bit memory (50) to store nonlinearity information. Long term drift is corrected by a calibrator (34) in parallel with data conversion.

Unaligned memory access prediction

Abstract: In an instruction execution pipeline, the misalignment of memory access instructions is predicted. Based on the prediction, an additional micro-operation is generated in the pipeline prior to the effective address generation of the memory access instruction. The additional micro-operation accesses the memory falling across a predetermined address boundary. Predicting the misalignment and generating a micro-operation early in the pipeline ensures that sufficient pipeline control resources are available to generate and track the additional micro-operation, avoiding a pipeline flush if the resources are not available at the time of effective address generation. The misalignment prediction may employ known conditional branch prediction techniques, such as a flag, a bimodal counter, a local predictor, a global predictor, and combined predictors. A misalignment predictor may be enabled or biased by a memory access instruction flag or misaligned instruction type.

Method of inserting a sensor into a pipeline

Abstract: A method of inserting a sensor into a pipeline including the steps of securing a fitting onto the pipeline, tapping an opening in the pipeline through the fitting, installing a housing on the fitting, the housing having a nipple extending at an angle to the pipeline, attaching a sensor insertion assembly to the nipple, the insertion assembly having a launch tube movable axially between the insertion assembly and the pipeline, extending the launch tube from the insertion assembly and through the pipeline opening into the pipeline, the launch tube intersecting the pipeline at an acute angle and providing communication between the sensor insertion assembly and the interior of the pipeline, and passing a sensor from the insertion assembly and through the launch tube into the pipeline.

The Microcomputer and Pipeline Transients

Abstract: A number of concepts related to computer studies of transient flow in pipeline systems are addressed. The topics are directed to applications on microcomputers, but are not limited to that special purpose. The topics include organizational concepts for system data handling, and ideas to realize certain storage and computational efficiencies when using the method of characteristics as the computational procedure. Alternatives to the method of specified time intervals, namely a staggered grid and an algebraic treatment, are discussed. A simple improved modification in the friction term is also emphasized. Two common elements in hydraulic systems that influence the form of pressure waves, series connections and lossy elements, are focused upon with a view to providing an improved visualization of their response characteristics. Equations and graphs are presented for cases with and without initial through flow. Finally, an example of the failure of a physical system is presented to emphasize the importance of unsteady flow visualization in hydraulic system design.

Data marshaling for multi-core architectures

Abstract: Previous research has shown that Staged Execution (SE), i.e., dividing a program into segments and executing each segment at the core that has the data and/or functionality to best run that segment, can improve performance and save power. However, SE's benefit is limited because most segments access inter-segment data, i.e., data generated by the previous segment. When consecutive segments run on different cores, accesses to inter-segment data incur cache misses, thereby reducing performance. This paper proposes Data Marshaling (DM), a new technique to eliminate cache misses to inter-segment data. DM uses profiling to identify instructions that generate inter-segment data, and adds only 96 bytes/core of storage overhead. We show that DM significantly improves the performance of two promising Staged Execution models, Accelerated Critical Sections and producer-consumer pipeline parallelism, on both homogeneous and heterogeneous multi-core systems. In both models, DM can achieve almost all of the potential of ideally eliminating cache misses to inter-segment data. DM's performance benefit increases with the number of cores.