Topic
Pipeline (computing)
About: Pipeline (computing) is a research topic. Over the lifetime, 26760 publications have been published within this topic receiving 204305 citations. The topic is also known as: data pipeline & computational pipeline.
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01 Dec 2004
TL;DR: Parker et al. as discussed by the authors used Natural Gas Transmission Pipeline costs to estimate Hydrogen Pipeline costs and found that hydrogen pipeline costs were higher than natural gas transmission pipeline costs, and that hydrogen pipelines were less expensive.
Abstract: Using Natural Gas Transmission Pipeline Costs to Estimate Hydrogen Pipeline Costs Nathan Parker ncparker@ucdavis.edu UCD-ITS-RR-04-35 Institute of Transportation Studies University of California One Shields Avenue Davis CA 95616
119 citations
Patent•
23 Dec 1994
TL;DR: In this paper, a data stream processing unit comprises a CPU which comprises an ALU, a shift/extract unit, timers, a scheduler, an event system, a plurality of sets of general purpose registers and masquerade registers, pipeline controller, a memory controller and a pair of internal buses.
Abstract: A data stream processing unit comprises a CPU which comprises an ALU, a shift/extract unit, timers, a scheduler, an event system, a plurality of sets of general purpose registers, a plurality of sets of special purpose registers, masquerade registers, pipeline controller, a memory controller and a pair of internal buses. The multiple sets of general and special purpose registers improves the speed of the CPU in switching between environments. The pipeline controller, the scheduler, the events system, and the masquerade registers facilitate the implementation and execution of the methods of the present invention such as efficient thread scheduling, branch delays, elimination of delay slots after stores that provide further increases in the performance and bandwidth.
119 citations
30 Aug 2004
TL;DR: In this article, the authors investigated the impact of pipelining on energy consumption of two representative FPGA devices: a 0.13μm CMOS high density/high speed FPGAs (Altera Stratix EP1S40) and an 0.18μm MCOS low-cost FPGa (Xilinx XC2S200).
Abstract: This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13μm CMOS high density/high speed FPGA (Altera Stratix EP1S40), and a 0.18μm CMOS low-cost FPGA (Xilinx XC2S200). The results are obtained by both measurements and execution of vendor-supplied tools for power estimation. It is found that pipelining can reduce the amount of energy per operation by between 40% and 90%. Further reduction in energy consumption can be achieved by power-aware clustering, although the effect becomes less pronounced for circuits with a large number of pipeline stages.
118 citations
01 Apr 1994
TL;DR: This paper used trace-driven simulation to show that the proposed design, which uses fewer resources, offers better performance than previously proposed alternatives for most programs, and indicates how to further improve this design.
Abstract: Accurate branch prediction is critical to performance; mispredicted branches mean that ten's of cycles may be wasted in superscalar architectures. Architectures combining very effective branch prediction mechanisms coupled with modified branch target buffers (BTB's) have been proposed for wide-issue processors. These mechanisms require considerable processor resources. Concurrently, the larger address space of 64-bit architectures introduce new obstacles and opportunities. A larger address space means branch target buffers become more expensive. In this paper, we show how a combination of less expensive mechanisms can achieve better performance than BTB's. This combination relies on a number of design choices described in the paper. We used trace-driven simulation to show that our proposed design, which uses fewer resources, offers better performance than previously proposed alternatives for most programs, and indicate how to further improve this design.
117 citations
TL;DR: The pipeline deals with architectures that are made of planar faces and faithfully constructs a polyhedron of low complexity based on the incomplete scans, which offers a convenient user interface but minimizes the necessity of user intervention.
Abstract: We present a pipeline to reconstruct complete geometry of architectural buildings from point clouds obtained by sparse range laser scanning. Due to limited accessibility of outdoor environments, complete and sufficient scanning of every face of an architectural building is often impossible. Our pipeline deals with architectures that are made of planar faces and faithfully constructs a polyhedron of low complexity based on the incomplete scans. The pipeline first recognizes planar regions based on point clouds, then proceeds to compute plane intersections and corners (in this paper, we use the informal terms corner or vertex corner to stand for a polyhedron vertex. See the Overview section for notation declarations), and finally produces a complete polyhedron. Within the pipeline, several algorithms based on the polyhedron geometry assumption are designed to perform data clustering, boundary detection, and face extraction. Our system offers a convenient user interface but minimizes the necessity of user intervention. We demonstrate the capability and advantage of our system by modeling real-life buildings.
117 citations