Pipeline (computing)

About: Pipeline (computing) is a research topic. Over the lifetime, 26760 publications have been published within this topic receiving 204305 citations. The topic is also known as: data pipeline & computational pipeline.

Pipeline start-up with entrapped air

Abstract: A mathematical model for the assessment of the pressure head maxima that air pockets within a pipeline can originate on start-up is presented. This model is based on a general model addressing the ...

Parallel processing computer systems with reduced power consumption and methods for providing the same

Abstract: A parallel processing computing system includes an ordered set of m memory banks and a processor core. The ordered set of m memory banks includes a first and a last memory bank, wherein m is an integer greater than 1. The processor core implements n virtual processors, a pipeline having p ordered stages, including a memory operation stage, and a virtual processor selector function.

Research on the Steady Operation Optimization Model of Natural Gas Pipeline Considering the Combined Operation of Air Coolers and Compressors

Abstract: Based on the mutual coupling effect among the compressor, the air cooler and pipes in the system of natural gas pipeline, innovatively with the goal of minimum energy consumption, this paper established a combined operation optimization model of the air cooler and compressor through the optimization of the switching scheme of compressors and air coolers, which can greatly reduce the production energy consumption of the pipeline system. Moreover, when the air temperature is taken as an optimization variable, the most proper temperature to start the air cooler of each compressor station can be worked out to guide the optimized operation of the pipeline, which is of high value for promotion and application. The case analysis of west-east natural gas pipeline II showed that among genetic algorithm (GA), particle swarm optimization (PSO), and simulated annealing (SA) algorithm that are used to solve the optimization model, the genetic algorithm is the fastest, and the simulated annealing algorithm the slowest, but the optimization results of the simulated annealing algorithm is the best, in which the reduced production energy consumption accounted for 33.77%, testifying the practicability and creativity of the optimization model.

Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers

Abstract: High-speed field-programmable gate array (FPGA) implementations of an adaptive least mean square (LMS) filter with application in an electronic support measures (ESM) digital receiver, are presented. They employ "fine-grained" pipelining, i.e., pipelining within the processor and result in an increased output latency when used in the LMS recursive system. Therefore, the major challenge is to maintain a low latency output whilst increasing the pipeline stage in the filter for higher speeds. Using the delayed LMS (DLMS) algorithm, fine-grained pipelined FPGA implementations using both the direct form (DF) and the transposed form (TF) are considered and compared. It is shown that the direct form LMS filter utilizes the FPGA resources more efficiently thereby allowing a 120 MHz sampling rate.

Pipelining in algorithms with quantizer loops

Abstract: High-speed implementation of signal processing algorithms for digital transmission is addressed. The internal feedback or recursion in these algorithms makes it difficult to implement recursive systems concurrently using either pipelining or parallelism. In the past, look-ahead computation techniques were successfully applied to create necessary concurrency in linear recursive and some nonlinear recursive operations (such as the add-compare-select operation). Novel computation approaches are proposed, and the look-ahead technique is extended to pipeline the feedback loops containing finite-level quantizers. Approaches to pipeline piecewise-linear recursive systems are presented. The proposed architectures are suitable for real-time high-speed implementation of quantizer loop operations where the levels of quantizer and the order of the loops are small. >