Topic
Pipeline (computing)
About: Pipeline (computing) is a research topic. Over the lifetime, 26760 publications have been published within this topic receiving 204305 citations. The topic is also known as: data pipeline & computational pipeline.
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01 May 1999
TL;DR: A method to predict the behavior of pipelined superscalar processors is described and initial results of a prototypical implementation for the SuperSPARC I processor are reported.
Abstract: For real time systems not only the logical function is important but also the timing behavior, e. g. hard real time systems must react inside their deadlines. To guarantee this it is necessary to know upper bounds for the worst case execution times (WCETs). The accuracy of the prediction of WCETs depends strongly on the ability to model the features of the target processor.Cache memories, pipelines and parallel functional units are architectural components which are responsible for the speed gain of modern processors. It is not trivial to determine their influence when predicting the worst case execution time of programs.This paper describes a method to predict the behavior of pipelined superscalar processors and reports initial results of a prototypical implementation for the SuperSPARC I processor.
96 citations
06 May 1980
TL;DR: This paper presents a new architecture for image processing that consists of a pipeline of identical programmable serial processing stages, referred to as a cytocomputer, and shows generally to possess the advantages of lower complexity, high bandwidth and greater architectural flexibility.
Abstract: This paper presents a new architecture for image processing. It consists of a pipeline of identical programmable serial processing stages, referred to as a cytocomputer. Comparisons are made between cytocomputer and parallel array systems. Cytocomputer systems are shown generally to possess the advantages of lower complexity, high bandwidth and greater architectural flexibility. A first generation system is described and examples of processing are illustrated. Finally, current development efforts are described.
96 citations
TL;DR: A “learned integrated sensing pipeline” (LISP), including in an end‐to‐end fashion both physical and processing layers, is shown to enable joint learning of optimal measurement strategies and a matching processing algorithm, making use of a priori knowledge on task, scene, and measurement constraints.
Abstract: The rapid proliferation of intelligent systems (e.g., fully autonomous vehicles) in today's society relies on sensors with low latency and computational effort. Yet current sensing systems ignore most available a priori knowledge, notably in the design of the hardware level, such that they fail to extract as much task-relevant information per measurement as possible. Here, a "learned integrated sensing pipeline" (LISP), including in an end-to-end fashion both physical and processing layers, is shown to enable joint learning of optimal measurement strategies and a matching processing algorithm, making use of a priori knowledge on task, scene, and measurement constraints. Numerical results demonstrate accuracy improvements around 15% for object recognition tasks with limited numbers of measurements, using dynamic metasurface apertures capable of transceiving programmable microwave patterns. Moreover, it is concluded that the optimal learned microwave patterns are nonintuitive, underlining the importance of the LISP paradigm in current sensorization trends.
96 citations
TL;DR: In this article, the authors investigated the mechanical behavior of drainage pipeline under traffic load before and after polymer grouting and cement grouting trenchless repairing through three-dimensional finite element method (FEM).
95 citations
28 Jun 1998
TL;DR: A framework for verifying a pipelined microprocessor whose implementation contains precise exceptions, external interrupts, and speculative execution is described and a table-based model of pipeline execution is created that records committed and in-flight instructions as performed by the microarchitecture.
Abstract: We describe a framework for verifying a pipelined microprocessor whose implementation contains precise exceptions, external interrupts, and speculative execution. We present our correctness criterion which compares the state transitions of pipelined and non-pipelined machines in presence of external interrupts. To perform the verification, we created a table-based model of pipeline execution. This model records committed and in-flight instructions as performed by the microarchitecture. Given that certain requirements are met by this table-based model, we have mechanically verified our correctness criterion using the ACL2 theorem prover.
95 citations