Pipeline (computing)

About: Pipeline (computing) is a research topic. Over the lifetime, 26760 publications have been published within this topic receiving 204305 citations. The topic is also known as: data pipeline & computational pipeline.

HDTV1080p H.264/AVC Encoder Chip Design and Performance Analysis

Abstract: A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30 fps is proposed in this paper. On the basis of the specifications and algorithm optimizations, the dedicated hardware engines and one 32-bit media embedded processor (MeP) equipped with hardware extensions are mapped into the three-stage macroblock pipelining system architecture. This paper describes the design considerations for chief components, including high throughput integer motion estimation, data reusing fractional motion estimation, and hardware friendly mode reduction for intra prediction. The 11.5 Gbps 64 Mb system-in-silicon DRAM is embedded to alleviate the external memory bandwidth. Using TSMC one-poly six-metal 0.18 mum CMOS technology, the prototype chip is implemented with 1140 k logic gates and 108.3 KB internal SRAM. The SoC core occupies 27.1 mm2 die area and consumes 1.41 W at 200 MHz execution speed in typical work conditions.

High-speed QDI asynchronous pipelines

Abstract: This paper introduces two new high-speed quasi delay insensitive (QDI) asynchronous pipeline templates. These new high throughput templates support complex non-linear pipeline structures and are well suited for fine-grain pipelining. Timing analysis and HSPICE simulations show that these templates are 20% and 40% faster than known QDI counterparts.

Computer architecture for conserving power by using shared resources and method for suspending processor execution in pipeline

Abstract: A computer architecture and method capable of retaining data after a system clock has been halted to conserve power. The computer comprises first processing circuitry, the first circuitry comprising dynamic components. The dynamic components include such devices as intermediate pipeline registers, arithmetic logic units, address generators, and instruction decode and control circuitry. The computer further comprises second processing circuitry, the second circuitry comprising static components. In a preferred embodiment, the static components comprise instruction registers, stop controls, general purpose registers, status registers, and random access memory. The use of dynamic components in the architecture of a preferred embodiment maximizes cost and size considerations, while the static components allows instruction execution and the system clock to be halted. The combination of dynamic and static components preserves information which enables the system to resume execution after the system clock has been stopped without data loss. This architecture reduces power consumption compared to a system implemented entirely in dynamic logic, while minimizing cost and area. Methods are also provided to stop this architecture and restart it without data loss.

Retropath: Automated Pipeline for Embedded Metabolic Circuits

Abstract: Metabolic circuits are a promising alternative to other conventional genetic circuits as modular parts implementing functionalities required for synthetic biology applications. To date, metabolic design has been mainly focused on production circuits. Emergent applications such as smart therapeutics, however, require circuits that enable sensing and regulation. Here, we present RetroPath, an automated pipeline for embedded metabolic circuits that explores the circuit design space from a given set of specifications and selects the best circuits to implement based on desired constraints. Synthetic biology circuits embedded in a chassis organism that are capable of controlling the production, processing, sensing, and the release of specific molecules were enumerated in the metabolic space through a standard procedure. In that way, design and implementation of applications such as therapeutic circuits that autonomously diagnose and treat disease, are enabled, and their optimization is streamlined.