PLL multibit

About: PLL multibit is a research topic. Over the lifetime, 2007 publications have been published within this topic receiving 34970 citations.

A phase tracking system for three phase utility interface inverters

Abstract: The analysis and design of the phase-locked loop (PLL) system is presented for the phase tracking system of the three phase utility interface inverters. The dynamic behavior of the closed loop PLL system is investigated in both continuous and discrete-time domains, and the optimization method is considered for the second order PLL system. In particular, the performance of the three phase PLL system is analyzed in the distorted utility conditions such as the phase unbalancing, harmonics, and offset caused by the nonlinear load conditions and measurement errors. The tracking errors under these distorted utility conditions are also derived. The phase tracking system is implemented in a digital manner using a digital signal processor (DSP) to verify the analytic results. The design considerations for the phase tracking system are deduced from the analytic and experimental results.

Operation of a phase locked loop system under distorted utility conditions

Abstract: Operation of a phase locked loop (PLL) system under distorted utility conditions is presented. A control model of the PLL system is developed and recommendations are made on tuning of this model specially for operation under common utility distortions such as line notching, voltage unbalance/loss, and frequency variations. The PLL is completely implemented in software without any filters. All analytical results are experimentally verified.

Low-jitter and process independent DLL and PLL based on self biased techniques

Abstract: Delay-locked loop (DLL) and phase-locked loop (PLL) designs based upon self-biased techniques are presented. The DLL and PLL designs achieve process technology independence, fixed damping factor, fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancellation, and, most importantly, low input tracking jitter. Both the damping factor and the bandwidth to operating frequency ratio are determined completely by a ratio of capacitances. Self-biasing avoids the necessity for external biasing, which can require special bandgap bias circuits, by generating all of the internal bias voltages and currents from each other so that the bias levels are completely determined by the operating conditions. Fabricated in a 0.5-/spl mu/m N-well CMOS gate array process, the PLL achieves an operating frequency range of 0.0025 MHz to 550 MHz and input tracking jitter of 384 ps at 250 MHz with 500 mV of low frequency square wave supply noise.

Delta-sigma modulation in fractional-N frequency synthesis

Abstract: A description is given of a delta-sigma ( Delta - Sigma ) modulation and fractional-N frequency division technique for performing indirect digital frequency synthesis using a phase-locked loop (PLL). The use of Delta - Sigma modulation concepts results in beneficial shaping of the phase noise (jitter) introduced by fractional-N division. The technique has the potential to provide low phase noise, fast settling time, and reduced impact of spurious frequencies when compared with existing fractional-N PLL techniques. >

Three-Phase PLLs: A Review of Recent Advances

Abstract: A phase-locked loop (PLL) is a nonlinear negative-feedback control system that synchronizes its output in frequency as well as in phase with its input PLLs are now widely used for the synchronization of power-electronics-based converters and also for monitoring and control purposes in different engineering fields In recent years, there have been many attempts to design more advanced PLLs for three-phase applications The aim of this paper is to provide overviews of these attempts, which can be very useful for engineers and academic researchers