Showing papers on "Polycrystalline silicon published in 1973"

Growth and Characterization of Polycrystalline Silicon

Abstract: Polycrystalline silicon is deposited by pyrolysis of silane in an rf heated epitaxial reactor. The grains exhibit a fibrous microstructure having an 〈110〉 preferred orientation in the growth direction. Growth is inhibited in the presence of excess arsine and accelerated in the presence of diborane. The results are explained in terms of catalysis and poisoning of surface adsorption sites responsible for reaction. A simple model for current conduction in polycrystalline silicon is described based on grain size, grain doping, and effective barrier height due to the grain boundary. This model satisfactorily explains the observed temperature dependence of the resistivity of undoped films and also the large values of resistivity which are observed for dopant concentrations .

Influence of AsH3, PH 3,and B 2 H 6 on the Growth Rate and Resistivity of Polycrystalline Silicon Films Deposited from a SiH4 ‐ H 2 Mixture

Abstract: The deposition rate of polycrystalline silicon from a mixture is significantly influenced by the addition of , ,and . At a deposition temperature of 680 °C causes a decrease by a factor of 7, causes a decrease by a factor of 2.5, while a two times higher deposition rate is obtained with addition. Out of these three dopant hydrides and do not affect the activation energy of the deposition reaction compared to undoped growth (37 kcal/mole). The Arrhenius plot for the deposition of silicon from a mixture shows two activation energies: 20 kcal/mole at and 7 kcal/mole below 620°C. The experimentally found minimum values of the resistivity of doped polycrystalline silicon can be explained in terms of solid solubility and carrier mobility. At deposition temperatures below 700 °C with and without addition of dopants the polycrystalline silicon surface is mirror‐like. Significant differences have, however, been observed by electron microscopy. Compared to undoped growth boron was found to lower the etch rate of the polycrystalline silicon film markedly.

System and process for deposition of polycrystalline silicon with silane in vacuum

Abstract: SYSTEM AND PROCESS FOR DEPOSITION OF POLYCRYSTALLINE SILICON WITH SILANE IN VACUUM ABSTRACT OF THE DISCLOSURE The present invention is directed to the method and means for depositing polycrystalline silicon from silane in a vacuum. This process contemplates the use of a gas source and a means for assuring a uniform flow of gas into the deposition chamber. The deposition chamber is a hot wall furnace. The deposition zone is kept at as uniform a tem-perature as possible. The preferred temperature is 600°Cwith a workable range extending from 600°C to 700°C. While the deposition zone is profiled flat from a temperature point of view, the deposition rate over the length of the tube appears as a flattened curve. This means that at the source and exhaust portions of the tube, the deposition rates are different from that rate in the central flattened portion. The boat upon which the wafers are placed is centered within the center portion of the curve along its flattest portion. Wafers are placed perpendicular to the gas flow with a preferred spacing approximately 50 mils on center when using wafers 20 mils thick. The wafers are placed in the tube from the source input end. At the gas exhaust end, intermediate the tube and the vacuum pump, is an optical baffle. The function of the optical baffle is to collect the undeposited silane material and silicon by-products which pass through the tube. The undeposited silane material appears in the form of a brown dust which is granular silicon and silicon monoxide. This granular material forms around the exit end of the tube and in the baffle.

Process for preparing semiconductor

Abstract: A semiconductor is prepared by continuously etching at least two types of silicon compound membranes such as silicon dioxide (SiO2), silicon nitride (Si3N4) or a polycrystalline silicon membrane which are formed on a silicon substrate. A freon gas plasma is used for etching so that the two types of silicon compound membranes are continuously etched in a sloped form without any undercutting, as occurs in conventional chemical solution etching.

Polycrystalline silicon pressure sensor

Abstract: 1. A POLYCRYSTALLINE SILICON PRESSURE SENSOR COMPRISING: A. A SUBSTRATE SUPPORT MEMBER HAVING A FLAT UPPER SURFACE, A FLEXIBLE INNER SECTION, AND A RIGID PERIPHERAL SECTION, RELATIVELY THICK COMPARED WITH THE FLEXIBLE SECTION, DOWNWARDLY DISPOSED TO FORM A SUPPORT FOR THE FLEXIBLE SECTION, THE MEMBER BEING OF A MATERIAL ON WHICH POLYCRYSTALLINE SILICON IS CAPABLE OF BEING DEPOSITED; B. A FIRST LAYER OF POLYCRYSTALLINE SILICON FORMED OVER THE FLAT UPPER SURFACE, SUFFICIENTLY THIN TO ENABLE FLEXING WITH THE FLEXIBLE INNER SECTION OF THE MEMBER; AND C. AT LEAST ONE PIEZORESISTIVE PRESSURE SENSITIVE ELEMENT OF A FIRST CONDUCTIVITY TYPE, FORMED THROUGH THE TOP SURFACE OF THE FIRST LAYER OVER THE FLEXIBLE INNER SECTION AND ESTENDING TO THE PERIPHERAL SECTION.

Integrated circuit fabrication process

Abstract: Integrated circuits of high density are fabricated in a simplified process which allows both the use of multiple conducting layers in a dielectric above a semiconductor substrate, such as a polycrystalline silicon (polysilicon) field shield and metal interconnection lines, while also making provision for very precise alignment of subsequent layers to diffusions. A doped oxide containing a suitable dopant, such as arsenic in the case of a p-type silicon substrate, is deposited on the substrate. A pattern corresponding to desired diffusions is generated by normal photolithographic and etching techniques. A second, undoped oxide layer is thermally grown over the semiconductor substrate with dopant from the doped oxide simultaneously diffusing into areas of the substrate underlying the doped oxide. The undoped oxide serves to prevent autodoping. Thermally growing the undoped oxide layer converts a layer of the semiconductor surface not covered by doped oxide to the undoped oxide. Both oxide layers are then removed, leaving slight steps at the surface of the semiconductor substrate around the diffusion. The slight steps serve to allow very precise alignment of masks for subsequent process steps. Otherwise, the structure produced is very planar. An insulating layer, desirably a composite of silicon dioxide and silicon nitride in the case of a silicon substrate, is then formed on the substrate, followed by a layer of polycrystalline semiconductor, desirably doped to provide high conductivity. Openings are then etched in the polycrystalline semiconductor layer to allow formation of gate electrodes of FET''s, contact to the substrate, and contact of a subsequent interconnection metallization to diffusions in some of the circuits. A second insulating layer, such as silicon dioxide, is then grown on the polycrystalline semiconductor layer. Contact holes are then made to diffusions in the substrate, the substrate itself, and the polycrystalline silicon. The deposition and etching of an interconnection layer on the second insulating layer completes fabrication of the integrated circuit.

Specific energy loss of 4He ions in silicon (amorphous, polycrystalline, and single crystal)

Abstract: The specific energy loss of 4He ions in silicon has been determined in the energy range 420–2750 keV. Several different methods of determining the specific energy loss were used to check the results. Studies were made of the variation of specific energy loss with silicon density and showed that lower‐density amorphous silicon has relatively higher specific energy losses. Studies were also made of the specific energy loss of 4He ions in radiation‐damaged silicon, polycrystalline silicon, and single‐crystal silicon. The values were then used in a thick‐target calculation to generate spectra of 4He backscattering from silicon targets. These calculations were compared to experimental spectra over a range of energies and backscattering angles. All calculations were within 2% of the experimental spectra. The ``random'' spectrum from a spinning crystal target was compared to thick‐target calculations and shown to be useful as a normalizing spectrum with an accuracy of ±5%.

Method of making capacitor and resistor for monolithic integrated circuits

Abstract: A low-leakage metal-oxide-polycrystalline silicon capacitor is produced on a silicon wafer by a method that is compatible with normal monolithic integrated circuit fabrication. After the base and resistor diffusion step of normal integrated circuit fabrication, a polycrystalline silicon region is grown followed by deposition of a capacitor lower plate mask. Normal IC fabrication is then resumed to complete the manufacture of the unit. The polycrystalline silicon is doped heavily n-type during the process, thus avoiding depletion and inversion effects if the circuit is run with normal power supplies. The capacitor is electrically isolated from the rest of the chip by dielectric isolation techniques. Using the same techniques, compatible polycrystalline silicon resistors can be simultaneously fabricated on the same wafer.

Methods of manufacturing semiconductor devices

Abstract: A method of providing an ohmic contact for a silicon semiconductor device, the ohmic contact including a layer of tungsten or molybdenum on a polycrystalline silicon layer, includes depositing these two layers consecutively in the same deposition apparatus, the polycrystalline layer being deposited from a silane atmosphere at 700* to 750*C and the metal layer being deposited when a vapour of a compound of the metal, such as the hexafluoride, is supplied to modify the deposition atmosphere, the compound being reduced by the silane.

Method of manufacturing semiconductor devices in which silicon oxide regions inset in silicon are formed by a masking oxidation, wherein an intermediate layer of polycrystalline silicon is provided between the substrate and the oxidation mask

Abstract: The manufacture of semiconductor devices, particularly silicon ICs, employing isolating inset oxides is described. To prevent formation of a projecting oxide beak under an oxidation masking layer, a layer of polycrystalline silicon is provided under the oxidation mask instead of the usual silicon oxide.

Dielectrically isolated semiconductor devices

Abstract: A dielectrically isolated semiconductor device can be manufactured The structure is useable for integrated circuits, including field effect and/or bipolar transistors, wherein a significant savings in surface area and reduction in capacitances can be obtained over prior techniques The method involves forming a layer of dielectric material upon a semiconductor body, having a diffused region where a bipolar device is to be formed, and then forming an opening in the layer to expose a part of the surface of the diffused region of the semiconductor body An epitaxial layer of silicon is deposited on top Single crystal silicon will grow over the exposed silicon area and if a diffused region is present in the substrate a pedestal will outdiffuse through the same area from the buried diffused region Polycrystalline silicon will grow on top of the dielectric material The pedestal is formed in a single crystal epitaxial layer of another impurity type Two other active elements of a bipolar transistor, such as the emitter and intrinsic base regions, are then formed in the same single crystal epitaxial layer while the inactive area, such as the extrinsic base, is formed in polycrystalline silicon A reach through is made through the dielectric layer to the third element of the transistor, that is collector region

Electrically erasable floating gate fet memory cell

Abstract: A read-mostly memory cell is disclosed comprising a floating gate avalanche injection field effect transistor storage device equipped with an erasing electrode. The memory portion of the erasable storage devices comprises a P channel FET having a floating polycrystalline silicon gate separated from an N-doped substrate by a layer of silicon dioxide. The erasing portion of the device comprises an erasing electrode separated from the polycrystalline silicon floating gate by a thermally grown layer of silicon dioxide having a leakage characteristic which is low in the presence of low electrical fields and high in the presence of high electrical fields. The floating gate is heavily doped with boron which also partially dopes the thermally grown silicon dioxide layer. The floating gate is charged negatively by avalanche breakdown of the FET drain while the erase gate is grounded to the substrate. The floating gate is discharged (erased) upon the application of a positive pulse to the erase electrode with respect to the semiconductor substrate causing electrodes on the charged floating gate to leak through the thermal oxide to the erasing electrode.

Method for forming silicon conductive layers utilizing differential etching rates

Abstract: A method for forming contoured electrodes of polycrystalline silicon by grading the concentration of dopant diffused into the silicon layers during the deposition process. Upon etching the silicon after deposition to form electrodes, e.g., the gate electrode of a field effect transistor, the electrode is desirably tapered. Conductive and insulator layers subsequently deposited atop the tapered electrode are less subject to cracking and lifting off than standard electrodes.

Polycrystalline silicon resistors for integrated circuits

Abstract: The suitability of thin films of doped polycrystalline silicon on SiO 2 substrates for the production of high value resistors for monolithic integrated circuits is considered. Resistors fabricated from this material posses the advantages of high sheet resistivity and dielectric isolation while still preserving an all silicon technology compatible with conventional production techniques. Relevant structural and electrical properties of doped polycrystalline films produced by both vacuum evaporation onto hot substrates with gas-doping and by diffusion-annealing of amorphous films have been investigated. Sheet resistivities and TCR values measured on 2500 A polycrystalline films have proved superior to those encountered with conventional diffused resistors. Typically films with sheet resistivities of 1 kΩ/□ had TCR's of −1000 ppm/°C while conventional diffused resistors are generally made from material of 200 Ω/□ and +2000 ppm/°C TCR. Etched resistor line widths of 0·25 mil. have been obtained in the polycrystalline material employing conventional photolithographic techniques. The temperature stability and linearity of doped polycrystalline resistors have been investigated.

Self aligned CCD element fabrication method therefor

Abstract: The disclosure relates to a CCD (charge-coupled device) structure and fabrication method therefor, wherein self alignment is achieved between implanted barrier regions in the semiconductor substrate and gate portions of the CCD structure during the fabrication thereof. Additionally, the gate electrodes of the CCD structure are formed in a manner which provides very narrow gaps between electrodes. Multiple layers of insulation are used to form the final CCD structure including the use of two separated layers of silicon nitride. The orthogonal gate electrodes are made of a metal such as aluminum and doped polycrystalline silicon.

Method of simultaneously making a sigfet and a mosfet

Abstract: A method comprising providing a gate electrode layer of polycrystalline silicon for a SIGFET, depositing a layer of silicon dioxide doped with an impurity of opposite conductivity type on the gate electrode layer and on the surface of the single crystal layer except where the channel of a MOSFET is to be located, diffusing dopant from the doped oxide layer into the gate electrode layer, and into the single crystal layer to form source and drain regions of the transistors, depositing a layer of gate insulating material on the channel region of the MOSFET, and depositing metal on the source and drain regions and on the gates of both transistors.

Method for forming a continuous layer of silicon dioxide over a substrate

Abstract: The method of this invention involves forming polycrystalline silicon on a substrate and subsequently converting the polycrystalline silicon into silicon dioxide.

Growth of Polycrystalline Silicon Films: Grain Size

Abstract: Durch Transmissionselektronenmikroskopie werden die Strukturen polykristalliner Si-Filme (die aus der Dampfphase aus Silan erhalten wurden) auf Si3N4- und SiO2-Substraten untersucht.

Method of obtaining high-quality thick films of polycrystalline silicone from dielectric isolation

Abstract: A polycrystalline silicon film is formed in an environment with minimum oxygen, thereby to reduce or substantially eliminate bowing of the wafer on which the polycrystalline silicon film is formed.

Durable high resolution silicon template

Abstract: A template including a polycrystalline silicon layer on a glass substrate and a protective coating on the polycrystalline silicon layer and method of manufacturing same. In one embodiment, the protective coating is an oxide layer which protects the silicon layer from abrasive damage and further functions as a mask to silicon etchant during manufacture of the template, to provide a template having substantially improved resolution. A mixture of hydrazine and catechol is used as a silicon etchant, to eliminate fogging of the substrate material.

Process for manufacturing integrated circuits

Abstract: A PROCESS OF MANUFACTURING INTEGRATED CIRCUITS, PARTICULARLY COMPLEMENTARY INTEGRATED CIRCUITS, IN AN N-TYPE SEMICONDUCTOR MATERIAL WHICH IS FORMED UPON AS INSULATING SUBSTRATE. THE PROCESS INCLUDES STEPS OF PATTERNING A DOPING OXIDE SUCH AS ALUMINUM OXIDE UPON THE SEMICONDUCTOR MATERIAL; FORMING A DIELECTRIC LAYER OVER THE SEMICONDUCTOR MATERIAL AND THE DOPING LAYER; AND THEN FORMING A POLYCRYSTALLINE SILICON HANDLE THEREON. FOLLOWING REMOVAL OF MOST OF THE ORIGINAL SEMICONDUCTOR MATERIAL, A HEATING STEP CAUSES AN UP-DIFFUSION FROM THE DOPING LAYER INTO AND THROUGH THE SEMICONDUCTOR BODY TO FORM P-TYO PE REGIONS OR TUBS, THEREIN.

Properties of nonvolatile semiconductor memories by using silicon clusters in the gate insulator

Abstract: Nonvolatile memories are now focused by many people. One of the most popular structure of the memories is an MNOS (metal-silicon nitride-silicon oxide-semiconductor) structure. However the structure has poor memory retention when B-T (80°c,-10V) stress is applied to the sample. The developed structures are MNCOS and MNCNOS (metal-over silicon nitride-silicon clusters-under silicon nitride-semiconductor), in which the silicon clusters are the small polycrystalline silicon particles having a compressed hemisphere. As the clusters act as trap centers of both holes and electrons, the trapping efficiency of censers increases, and the thicker silicon oxide film (tox= 50 - 60 A) is able to use for the better memory retention. The memories can operate more than ten years under the BT (-10V, 80°c) stress condition.

Germanium bonded silicon substrate and method of manufacture

Abstract: A support member is affixed to a silicon wafer, either patterned or not patterned, forming a substrate, by providing at least the wafer with a first layer of polycrystalline silicon, followed by a second layer of polycrystalline germanium. The support member may be provided with a first layer of polycrystalline silicon followed by a second layer of polycrystalline germanium. However, in the alternative, the support member may be provided with a layer of polycrystalline germanium directly after having properly prepared the surface to which the polycrystalline germanium is to adhere. The germanium layers are placed in contact with each other and heat is applied causing an alloying or an alloy interface between the polycrystalline germanium and the polycrystalline silicon to occur. The result is a silicon substrate, either patterned or unpatterned, in appropriate condition for formation of semiconductive devices and for the attachment of beam leads.

Process of making hollow bodies or tubes of semi-conducting materials

Abstract: Process for making semi-conducting hollow bodies by thermal splitting of volatile semi-conducting silicon compounds comprising passing the volatile silicon compounds over a carbon mold or a carbon-coated mold, and depositing thereon in three successive stages, SiO2, amorphous silicon, and polycrystalline silicon by adjustment of the temperature in each stage, and, after cooling, lifting the polycrystalline silicon body off the mold. The invention also comprises the polycrystalline Si body so made.

Crystal growth combining float zone technique with the water cooled RF container method

Abstract: The disclosure relates to the growth of single crystal material from polycrystalline material by combining the pedestal and cold crucible techniques to yield a method of producing large, high purity single crystals on a commercial scale. The method includes feeding a bar of polycrystalline material, such as silicon, into a cold cage which can be a cold silver crucible or the like having an aperture in the bottom thereof to permit insertion of the polycrystalline feed bar. An RF coil surrounds the cold cage and melts the silicon as it reaches into the cage, the RF coil providing a temperature to the silicon material which is slightly above the melting point thereof. A rod of single crystal material, the same as the feed bar, is positioned in the melt from the top surface of the cold cage and acts as a seed crystal. The single crystal rod is then pulled upwardly from the cage while polycrystalline silicon is fed into the cage through the aperture in the bottom thereof. By continuously forcing the polycrystalline rod into the cage and pulling a rod at the top of the cage, a large single crystal can be grown while maintaining only a small melt volume. The diameter of the single crystal rod being pulled will have a relation to the upper diameter of the cold cage as well as the ratio of the feed rate of the polycrystalline bar relative to the pull rate of the single crystalline bar.

Method of fabricating a thermal display device

Abstract: A plurality of silicon elements are arranged in a printing array with the major faces co-planar and the edges interconnected into a monolithic structure by a grid of polycrystalline silicon and silicon dioxide. The silicon dioxide provides an electrical and thermal barrier, and the polycrystalline silicon provides a strong mechanical interconection. In the preferred embodiment, the silicon elements are monocrystalline and contain one or more electrical components for selectively heating the elements. The method for fabricating the device includes the steps of etching V-shaped grooves in one surface of a silicon slice and then successively growing silicon dioxide and polycrystalline silicon on the etched surface to form a thick slice. The other side of the slice is then lapped away to at least the depth of the silicon dioxide in the grooves and semiconductor elements and conductors formed in and/or on the lapped side. The lapped side is then bonded to a substrate and the polycrystalline silicon and silicon dioxide removed from the surfaces of the elements, but not from the grooves between the elements. The elements are thus part of a monolithic sheet having sufficient structural integrity to withstand thermal fracturing without producing print smearing from element to element.

Mnos memory matrix

Abstract: A semiconductor memory of a matrix of active devices each of which is metal-nitride-oxide-silicon (MNOS) field effect transistor device. Each of the active devices defines one bit of the memory. A polycrystalline silicon member defines the gate electrode for the active device and also the row conductor for the matrix. The source and drain electrodes of columns of the field effect transistors are interconnected in parallel with other source and drain electrodes of single crystal silicon of the field effect devices to define column conductors for the matrix. The matrix is manufactured by providing an insulating substrate having a layer of monocrystalline silicon thereon. The monocrystalline silicon is suitably masked and etched to define a plurality of parallel ladder-like structures wherein the side pieces of the ladder form the column conductors for the matrix while the cross pieces or the rungs of the ladder define the channel of the device. The shaped monocrystalline silicon material and the exposed substrate is then covered by a layer of silicon dioxide, a layer of silicon nitride and a layer of polycrystalline silicon utilizing suitable masking and etching steps. The polycrystalline silicon, the silicon-nitride and silicon-dioxide are removed to form the row conductors and gate electrodes for the active devices, while exposing portions of the side pieces of the ladders of semiconductor material. A single diffusion step is then required to create the source and drain junctions for the active devices; render conductive the column conductors; and render conductive the gate electrode and row conductors formed by the polycrystalline silicon, that portion of the monocrystalline silicon on the substrate underlying the gate electrode being masked by the gate electrode so as to define the channel in the originally deposited rung of the monocrystalline silicon.