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Showing papers on "Polycrystalline silicon published in 1974"


Patent
30 Dec 1974
TL;DR: In this paper, a double polycrystalline silicon gate memory device having a floating gate for storing charge and a control gate was used as a single device cell in a memory array, where a double self-aligning method was used to form the source and drain regions while doping the gates.
Abstract: A double polycrystalline silicon gate memory device having a floating gate for storing charge and a control gate. The memory device may be used as a single device cell in a memory array. A double self-aligning method is used to form the source and drain regions while doping the gates. Through a predeposition step a lightly doped secondary source and drain regions are formed in alignment with the floating gate prior to the formation of the primary source and drain regions in alignment with the control gate.

119 citations


Patent
25 Nov 1974
TL;DR: In this paper, a semiconductor pressure transducer having a polycrystalline silicon diaphragm providing an extremely pressure sensitive and temperature stable device, and a method of making the same.
Abstract: A semiconductor pressure transducer having a polycrystalline silicon diaphragm providing an extremely pressure sensitive and temperature stable device, and a method of making the same. The polycrystalline silicon can easily be vapor deposited on an etch resistant layer covering a surface of a wafer or base, preferably monocrystalline silicon. Such vapor deposition of the polycrystalline silicon more accurately and consistently defines the thickness of the diaphragm than can be obtained by grinding or etching. A pressure responsive resistor formed in the diaphragm is automatically electrically isolated by the comparatively high resistivity of the polycrystalline silicon. Accordingly, PN junction isolation and passivating oxides on the diaphragm are not required thereby resulting in increased temperature stability.

57 citations


Patent
Arthur K. Hochberg1
03 May 1974
TL;DR: In this article, a method of fabricating dielectrically isolated semiconductor regions adapted for the construction of an integrated circuit on an epitaxial wafer was proposed. But this method is limited to the case where the wafer has a first layer of monocrystalline n+ type silicon of a predetermined thickness and a second layer of epitaxially deposited n-type silicon which is substantially thinner than the first layer.
Abstract: The invention is a method of fabricating dielectrically isolated semiconductor regions adapted for the construction of an integrated circuit on an epitaxial wafer wherein the epitaxial wafer has a first layer of monocrystalline n+ type silicon of a predetermined thickness and a second layer of epitaxially deposited n-type silicon which is substantially thinner than the first layer. A layer of silicon dioxide is grown on the back side of the first layer of the wafer and a layer of polycrystalline silicon is deposited onto the silicon dioxide layer. An aluminum oxide mask is formed defining a plurality of grooves around active semiconductor regions within the n-type silicon layer. The grooves are formed by a sputter etching process. Silicon dioxide is thermally grown within each of the grooves exposed by the sputter etching process to dielectrically isolate the active semiconductor regions after which semiconductor devices may be formed in each of the active semiconductor regions.

50 citations


Patent
Gregory L. Kuhn1
29 Nov 1974
TL;DR: In this article, a two-step process is described for filling grooves, moats, and channels formed by both channel and anisotropic etching techniques, where a P+ (boron) doped oxide is placed in the grooves or moats using spinon techniques followed by a uniform deposition of polycrystalline silicon over the entire wafer.
Abstract: A process is disclosed for filling grooves, moats, and channels formed by both channel and anisotropic etching techniques. Basically the process is a two-step process to be performed on a wafer in which a channel and/or a moat has been formed. A P+ (boron) doped oxide is placed in the grooves or moats using spinon techniques followed by a uniform deposition of polycrystalline silicon over the entire wafer. Due to the spinning effects the P+ doped oxide is collected mostly in the grooves or moats. The P+ doped oxide that remains outside of the grooves and/or moats is removed using standard photolithographic procedures. The wafer is now heated to a temperature sufficient to drive the boron impurities from the P+ doped oxide into the polycrystalline silicon. A portion of a polycrystalline silicon now becomes heavily P+ doped. The remaining polycrystalline silicon remains undoped. The wafer is then etched by an etchant which effectively stops when the material being etched is highly P+ doped. In this manner a portion of the remaining undoped polycrystalline material is removed and the highly doped polycrystalline material is left in the channels and/or moats. The above can be repeated until the moats or channels are completely filled.

48 citations


Journal ArticleDOI
TL;DR: In this article, the work function difference of the AlSiO 2 ǫSi-system was measured by the MOS-capacitance-voltage technique for n - and p -type silicon as substrate and was compared to the results obtained by different authors applying the photoemission technique.
Abstract: The work function difference of the AlSiO 2 Si-system was measured by the MOS-capacitance-voltage technique for n - and p -type silicon as substrate and was compared to the results obtained by different authors applying the photoemission technique. It could be seen that the work function differences measured in this work differ largely from the values measured by the photoemission technique. On the basis of the results obtained the work function differences of the p + polySiSiO 2  nSi - and n + polySiSiO 2  p Si-system were defined by comparative measurements. From this it was evident that the location of the Fermi level in heavily doped polycrystalline silicon is identical to the location of the Fermi level in monocrystalline silicon of the same impurity concentration.

47 citations


Patent
15 May 1974
TL;DR: In this article, a semiconductor device is provided having at least two semiconductor regions of opposite conductivity type and forming a planar-type PN junction, where a field limiting ring is disposed spaced from the PN.
Abstract: A semiconductor device is provided having at least two semiconductor regions of opposite conductivity type and forming a planar-type PN junction. A field limiting ring is disposed spaced from the PN junction. A high-resistivity polycrystalline silicon layer covers the PN junction and the field limiting ring.

31 citations


Journal ArticleDOI
TL;DR: In this paper, a method for growing silicon with a columnar structure, with a monograin along the growth direction, was proposed to make possible polycrystalline solar cells with good photovoltaic efficiencies.
Abstract: In order to make low‐cost silicon solar cells for large‐scale terrestrial use, we have considered a method for growing silicon with a columnar structure, with a monograin along the growth direction. Such a polycrystal, in contrast to general polycrystal material with randomly oriented grain arrangement, would make possible polycrystalline solar cells with good photovoltaic efficiencies.

30 citations


Journal ArticleDOI
T. Kamins1
TL;DR: In this article, the formation and properties of polycrystalline silicon films for different applications are reviewed, and the use of the films in semiconductor devices is discussed, where the deposition temperature, gases, and impurities are found to have the major influence on the properties of the polysilicon films.
Abstract: In recent years polycrystalline silicon deposited by chemical vapor deposition has become of importance in many semiconductor applications. The formation and properties of films deposited for different applications are reviewed in this paper, and the use of the films in semiconductor devices is discussed. The deposition temperature, gases, and impurities are found to have the major influence on the properties of the films. These deposition variables significantly affect the crystal

29 citations


Patent
26 Jul 1974
TL;DR: In this paper, a silicon substrate is coated with a layer of polycrystalline silicon containing a selected quantity of dopant, and the combination is heated to cause diffusion of the dopant from the film into the substrate.
Abstract: A silicon substrate is coated with a layer of polycrystalline silicon containing a selected quantity of dopant. The combination is heated to cause diffusion of the dopant from the film into the substrate. The polycrystalline coating of silicon may contain more than one dopant. The product is a semiconductor device including crystalline silicon doped to a concentration of 1014 to 1017 protected by a layer of polycrystalline silicon.

28 citations


Patent
10 May 1974
TL;DR: In this article, a method of making a semiconductor device capable of high-speed operation is disclosed in which when the current gain-bandwidth is increased by the formation of a shallow base region.
Abstract: A method of making a semiconductor device capable of high-speed operation is disclosed in which when the current gain-bandwidth is increased by the formation of a shallow base region. A side etching process is used to decrease the base spreading resistance and to allow ease in the formation of an emitter region of fine pattern. When the emitter region is formed by using polycrystalline silicon as a source of impurity diffusion, that area of an insulating film on a semiconductor substrate which adjoins the polycrystalline silicon is removed before the impurity diffusion so as to prevent an abnormal diffusion phenomenon. BACKGROUND OF THE INVENTION

27 citations


Journal ArticleDOI
TL;DR: In this paper, the ability of polycrystalline silicon to form Schottky barriers and p−i−n junctions has been evaluated experimentally and the results show Si grain boundaries behaving as p-type layers separating high resistivity grains.
Abstract: Standard semiconductor measurements and techniques have been applied to undoped, high-purity polycrystalline silicon to determine its electronic properties. Resistivity and Hall mobility were determined as function of temperature, and the ability of polycrystalline silicon to form Schottky barriers and p−i−n junctions has been evaluated experimentally. Present results show Si grain boundaries behaving as p-type layers separating high-resistivity grains. An effective mobility, half the monocrystalline value, and an average carrier density in the 1015 cm−3 range are deduced. A qualitative model is discussed to describe present results.

Patent
16 Aug 1974
TL;DR: An improved process for forming electrically isolated regions in integrated circuits in the form of dielectric moats surrounding the regions and P-N junctions underlying the regions is described in this article.
Abstract: An improved process for forming electrically-isolated regions in integrated circuits in the form of dielectric moats surrounding the regions and P-N junctions underlying the regions. Moats or notches are etched into the substrate prior to the formation of the buried isolation layer or further device information. A dielectric material such as silicon dioxide is deposited in the notches or moats and polycrystalline silicon is thereafter grown on the surface of the wafer to fill the notches or moats. The excess polysilicon formed on the surface of the wafer is then removed by mechanical lapping or polishing. Since there has been no doping or epitaxial growth, the wafer may be lapped directly to the substrate to remove all of the polysilicon and oxide from the surface while leaving the notches or moats lined with dielectric material and filled with polysilicon. There is thus no criticality to the lapping operation.

Journal ArticleDOI
J.M. Jaffe1
TL;DR: In this paper, a monolithic pressure transducer using polycrystalline silicon for both the diaphragm material and an integral piezoresistor has been fabricated, which is very good over a pressure range of 0?11 cm Hg for a 2.4
Abstract: A monolithic pressure transducer using polycrystalline silicon for both the diaphragm material and an integral piezoresistor has been fabricated. The device can be made with good repeatability and with easily varied diaphragm thickness. Electrical-output linearity is very good over a pressure range of 0?11 cm Hg for a 2.4 ?m diaphragm having an area of 0.00136 cm2.

Patent
25 Feb 1974
TL;DR: In this paper, an improved method for manufacturing a semiconductor device is disclosed, wherein self-alignment is achieved between implanted barrier regions in the semiconductor substrate and gate portions of the device.
Abstract: An improved method for manufacturing a semiconductor device is disclosed, wherein self-alignment is achieved between implanted barrier regions in the semiconductor substrate and gate portions of the device. The method includes the step of forming an oxide insulating layer over a polycrystalline silicon layer followed by the step of forming a nitride layer over the oxide layer. In this process the gate electrodes that are formed in the device are separated by very narrow gaps.


Patent
18 Mar 1974
TL;DR: In this article, a mixture of silicon nitride powder and an oxide, hydride or nitride of an element of the lanthanide series in powder form is hot pressed at a temperature ranging from 1600° to 1750° C for a period of 30 to 60 minutes.
Abstract: In a method for fabricating highly dense, polycrystalline silicon nitride bodies, a mixture of silicon nitride powder and an oxide, hydride or nitride of an element of the lanthanide series in powder form is hot pressed at a temperature ranging from 1600° to 1750° C for a period of 30 to 60 minutes. The method is particularly useful for fabricating structural components, such as stators, blades, airfoils and buckets in high performance gas turbine engines.

Patent
Donald K. Roberson1
04 Dec 1974
TL;DR: In this article, an improved integrated semiconductor transistor device with the feature of a heavily doped epitaxial semiconductor region in contact with a buried sub-collector region is described.
Abstract: This disclosure is directed to an improved integrated semiconductor transistor device which has the feature of a heavily doped epitaxial semiconductor region in contact with a buried sub-collector region. Additional features include dielectric sidewall isolation combined with PN junction isolation between the substrate and the collector portion of the transistor. The epitaxial contact to the buried sub-collector region is formed simultaneous with the formation of polycrystalline silicon filler material that fills in the dielectric isolation moat or channel located around the sides of individual electrically isolated transistor devices in order to achieve a planar surface structure. Another feature of the transistor device is the use of a base region that extends completely across and in contact with the sidewalls of the dielectric isolation moat. Preferably, the emitter region also extends across and in contact with three of the four of the sidewalls of the dielectric isolation moat. In this manner, transistor devices can be made very small with external electrical metal contacts made to the emitter region, the base region, and to the heavily doped epitaxial semiconductor region that is in contact with the buried sub-collector region. This epitaxial contact region to the buried sub-collector region is located within a portion of the polycrystalline silicon filler material that is bounded by the dielectric isolation sidewall material.

Patent
Donald K. Roberson1
03 Jan 1974
TL;DR: In this article, an improved integrated semiconductor transistor device with the feature of a heavily doped epitaxial semiconductor region in contact with a buried sub-collector region is described.
Abstract: This disclosure is directed to an improved integrated semiconductor transistor device which has the feature of a heavily doped epitaxial semiconductor region in contact with a buried sub-collector region. Additional features include dielectric sidewall isolation combined with PN junction isolation between the substrate and the collector portion of the transistor. The epitaxial contact to the buried sub-collector region is formed simultaneous with the formation of polycrystalline silicon filler material that fills in the dielectric isolation moat or channel located around the sides of individual electrically isolated transistor devices in order to achieve a planar surface structure. Another feature of the transistor device is the use of a base region that extends completely across and in contact with the sidewalls of the dielectric isolation moat. Preferably, the emitter region also extends across and in contact with three of the four of the sidewalls of the dielectric isolation moat. In this manner, transistor devices can be made very small with external electrical metal contacts made to the emitter region, the base region, and to the heavily doped epitaxial semiconductor region that is in contact with the buried sub-collector region. This epitaxial contact region to the buried sub-collector region is located within a portion of the polycrystalline silicon filler material that is bounded by the dielectric isolation sidewall material.

Journal ArticleDOI
TL;DR: In this article, it was shown that the epitaxial layer is structurally much superior to the substrate material, and good quality pn junctions have been epitaxially grown on these ribbons with reasonable values of minority carrier lifetime and saturation current density, but variations are observed related to structural imperfections.
Abstract: Silicon epitaxial layers have been deposited on polycrystalline silicon ``ribbon'' substrates. It is shown that the epitaxial layer is structurally much superior to the substrate material. Good quality p‐n junctions have been epitaxially grown on these ribbons with reasonable values of minority carrier lifetime and saturation current density, but variations are observed related to structural imperfections.

Patent
01 Apr 1974
TL;DR: In this paper, a sloped tip of a single crystal silicon material located at the end of a polycrystalline silicon layer and making contact with the single-crystal silicon substrate is described.
Abstract: A structure which achieves a sloped topography where a layer of polycrystalline silicon contacts a single crystal silicon substrate and a process for fabricating the structure are disclosed. The structure comprises a sloped tip of a single crystal silicon material located at the end of the polycrystalline silicon layer and making contact with the single crystal silicon substrate. The process involves defining the polycrystalline silicon layer by applying an orientation-selective etch which etches unwanted polycrystalline silicon preferentially to single crystal silicon so that the sloped tip remains essentially intact to achieve said sloped topography contact area.

Patent
Friedrich Hans Dipl-Phys1
09 Aug 1974
TL;DR: In this article, a two-phase charge shift assembly is described, as well as the process for its production, which consists of applying an insulating layer to a semiconductor substrate, applying a highly ohmic polycrystalline silicon layer to the insulating layers, forming metal electrodes on the poly crystal layer to protect the zones lying beneath the electrodes, implanting charge carriers by ion implantation in an oblique direction into zones of the layer of poly crystal silicon to thereby form electrodes in the layer which serve as electrodes between the electrically insulating zones of poly crystalline
Abstract: A two-phase charge shift assembly is described, as well as the process for its production. The process consists of applying an insulating layer to a semiconductor substrate, applying a highly ohmic polycrystalline silicon layer to the insulating layer, forming metal electrodes on the polycrystalline layer to thereby protect the zones lying beneath the electrodes, implanting charge carriers by ion implantation in an oblique direction into zones of the layer of polycrystalline silicon to thereby form electrodes in the layer which serve as electrodes between the electrically insulating zones of polycrystalline material.


Patent
11 Jan 1974
TL;DR: A high yield process for making polycrystalline silicon metal suitable for semiconductor usage which involves vapor phase decomposition of a mixture of dichloro-silane and trichlorosilane is described in this paper.
Abstract: A high yield process for making polycrystalline silicon metal suitable for semiconductor usage which involves vapor phase decomposition of a mixture of dichlorosilane and trichlorosilane.




Journal ArticleDOI
01 Oct 1974
TL;DR: The switching characteristics of polysilicon n-π-n devices present an extended negative-resistance region and allow large current densities as mentioned in this paper, and a breakover threshold field of 104V/cm has been deduced.
Abstract: The switching characteristics of polysilicon n-π-n devices present an extended negative-resistance region and allow large current densities. A breakover threshold field of 104V/cm has been deduced. It is suggested that polysilicon devices should be explored for switching applications.

01 May 1974
TL;DR: In this article, the electrical resistivity of polycrystalline silicon films was investigated and a model based on high dopant atom segregation in the grain boundaries was proposed to explain the results.
Abstract: The electrical resistivity of polycrystalline silicon films was investigated. The films were grown by the chemical vapor decomposition of silane on oxidized silicon wafers. The resistivity was found to be independent of dopant atom concentration in the lightly doped regions but was a strong function of dopant levels in the more heavily doped regions. A model, based on high dopant atom segregation in the grain boundaries, is proposed to explain the results.


Journal ArticleDOI
TL;DR: In this article, die Strukturen polykristalliner Si-Filme (die aus der Dampfphase aus Silan erhalten wurden) auf Si3N4-and SiO2-Substraten untersucht.
Abstract: Durch Transmissionselektronenmikroskopie werden die Strukturen polykristalliner Si-Filme (die aus der Dampfphase aus Silan erhalten wurden) auf Si3N4- und SiO2-Substraten untersucht.