Showing papers on "Polycrystalline silicon published in 1975"

The electrical properties of polycrystalline silicon films

Abstract: Boron doses of 1×1012–5×1015/cm2 were implanted at 60 keV into 1‐μm‐thick polysilicon films. After annealing at 1100 °C for 30 min, Hall and resistivity measurements were made over a temperature range −50–250 °C. It was found that as a function of doping concentration, the Hall mobility showed a minimum at about 2×1018/cm3 doping. The electrical activation energy was found to be about half the energy gap value of single‐crystalline silicon for lightly doped samples and decreased to less than 0.025 eV at a doping of 1×1019/cm3. The carrier concentration was very small at doping levels below 5×1017/cm3 and increased rapidly as the doping concentration was increased. At 1×1019/cm3 doping, the carrier concentration was about 90% of the doping concentration. A grain‐boundary model including the trapping states was proposed. Carrier concentration and mobility as a function of doping concentration and the mobility and resistivity as a function of temperature were calculated from the model. The theoretical and ex...

Interface effects and high conductivity in oxides grown from polycrystalline silicon

Abstract: Several dark‐current and photocurrent techniques have been used to determine the nature of high dark conductivity observed in oxides grown from polycrystalline silicon. Photocurrent measurements on polycrystalline Si‐SiO2‐Al MOS structures give idential interface energy barrier heights to those on single‐crystal Si‐SiO2‐Al MOS structures, and do not show the presence of any measurable oxide charge. Dark‐current measurements on polycrystalline Si MOS structures oxidized to varying degrees show an abrupt conductivity decrease when the polycrystalline Si is completely oxidized to the underlying single‐crystal Si substrate. It is concluded from these experiments that the high dark conductivity observed is an interface phenomenon that is due to localized field enhancement near the injecting contact. This field enhancement, not being due to positive oxide charge, is speculated to be caused by surface asperities.

Concentration profiles of boron implantations in amorphous and polycrystalline silicon

Abstract: Boron was implanted in amorphous silicon at energies in the range 30–200 keV and in polycrystalline silicon at energies in the range 70–800 keV. The boron distributions were measured with secondary ion mass spectrometry. By comparing the boron distributions in amorphous silicon and in polycrystalline silicon it was found that the used polycrystalline silicon behaves similarly to amorphous silicon for the boron stopping process. It was found that with the first four moments of the experimental distributions, an analytic description of the experimental distributions can be given by distributions of the Pearson system. The moments are determined by curve fitting of Pearson distributions to experimental distributions. In this way a systematic extrapolation of the low energy distributions outside the surface is automatically obtained. The moments are compared with the moments calculated by Winterbon and others. A satisfactory correspondence between the experimental and theoretical average ranges and s...

Fabrication of polycrystalline solar cells on low-cost substrates

Abstract: Low-cost polycrystalline silicon cells supported on substrates are prepared by depositing successive layers of polycrystalline silicon containing appropriate dopants over supporting substrates of a member selected from the group consisting of metallurgical-grade polycrystalline silicon, graphite and steel coated with a diffusion barrier of silica, borosilicate, phosphosilicate, or mixtures thereof such that p-n junction devices are formed which effectively convert solar energy to electrical energy.

Dependence of resistivity on the doping level of polycrystalline silicon

Abstract: The electrical resistivity of polycrystalline silicon films has been studied as a function of doping concentration and heat treatment. The films were grown by the chemical vapor decomposition of silane on oxidized silicon wafers. The resistivity of the as−deposited films was widely scattered but independent of dopant atom concentration at the lightly doped levels and was strong function of dopant level in the more heavily doped regions. Postdeposition heat treatments in an oxidizing atmosphere remove scatter in the data. The resultant resistivity for dopant levels less than 1016 atoms/cm3 was approximately equal to that of intrinsic silicon. In the next 2 orders of magnitude increase in dopant level, the resistivity dropped 6 orders of magnitude. A model, based on high dopant atom segregation in the grain boundaries, is proposed to explain the results.

Plasma spraying process for preparing polycrystalline solar cells

Abstract: Polycrystalline silicon films useful in preparing solar cells primarily for terrestrial application are prepared by a plasma spraying process. A doped silicon powder is injected into a high temperature ionized gas (plasma) to become molten and to be sprayed onto a low-cost substrate. Upon cooling, a dense polycrystalline silicon film is obtained. A p-n junction is formed on the sprayed film by spray deposition, diffusion or ion implantation. A sprayed junction is produced by plasma spraying a thin layer of silicon of opposite polarity or type over the initially deposited doped film. In forming a diffused junction, dopant is applied over the surface of the initial plasma-sprayed film usually from the vapor phase and heat is used to cause the dopant to diffuse into the film to form a shallow layer of opposite polarity to that in the original film. A junction is also formed by implanting dopant ions in the surface of the originally deposited film by the use of electrical fields. When used in conjunction with ohmic contacts and electrical conductors, the p-n junctions produced using plasma-sprayed polycrystalline silicon films are formed into solar cells which are useful for directly converting sunlight into electricity by means of the photovoltaic effect.

Self-aligned integrated circuits

Abstract: Semiconductor integrated circuits, including, e.g., field effect transistors and memory cells employing field effect transistors, are formed by providing at a surface of semiconductor substrate a pair of isolation mediums and a plurality of spaced apart conductive lines extending between the isolation mediums. The conductive lines, such as polycrystalline silicon or polysilicon lines, are preferably thermally, chemically or anodically self insulatable in an unmasked batch process step and are made of a material suitable for defining a barrier to a dopant for the semiconductor substrate. Signal or bias voltages are applied to selected or predetermined conductive lines to provide control electrodes or field shields for the transistors. When the substrate has deposited on its surface an insulating medium made of a dual dielectric, such as silicon dioxide-silicon nitride, the dopant may be ion implanted through the insulating medium to form, e.g., the source and drain electrodes of the transistors as defined by the isolation mediums and the conductive lines. Other elements may be added to the structure to form, e.g., a memory cell. By depositing a conductive medium over the insulated conductive lines, the medium may be appropriately etched to provide desired access lines, capacitor electrodes, ground planes or additional field shields for the cells.

Recrystallization processes in polycrystalline silicon

Abstract: Recrystallization processes in polycrystalline silicon made by a chemical vapor deposition technique have been investigated. Primary recrystallization has been observed between 1150 and 1250 °C, secondary recrystallization occurred above 1350 °C. By this procedure, grains of about 100 μm have been obtained. Recrystallized silicon can in principle be used as a substrate for making relatively inexpensive solar cells.

Boron diffusion in polycrystalline silicon layers

Abstract: Boron was diffused into the poly Si layers of 5·5 μm thickness with boron nitride and diborane as boron sources. The diffusion depth was found to be proportional to the square root of diffusion time. The boron diffusion in the poly Si layers can be expressed in the well known complementary error function. The diffusion coefficient of boron in the poly Si layers is larger when diborane is used than when boron nitride is used as a boron source and is 10–50 times larger than that in the single crystal silicon substrates in the experimental range. The diffusion coefficients of boron at 1050°C in the single crystal silicon substrates with diborane as a boron source in the poly Si layers with boron nitride and diborane as boron sources are 8·80 × 10 −14 , 1·17 × 10 −12 and 1·95 × 10 −12 cm 2 /sec, respectively. The activation energies of the diffusion coefficients of boron in the above each case are 3·42, 2·39 and 2·51 eV, respectively.

High‐temperature elastic moduli of polycrystalline silicon nitride

Abstract: Elastic constants are reported for several polycrystalline silicon nitrides with densities between 2.37 and 3.18 g/cm3 in the temperature range 0–1000 °C. The density dependence of the elastic constants is in approximate agreement with the prediction of a theory of composites.

Integrated circuit and manufacture thereof

Abstract: An integrated circuit comprises complementary FET having channels extending on the surface of a substrate and on the surface of a well in the substrate and gates formed in a layer of polycrystalline silicon insulated from the substrate and from each said well. A floating diode, i.e. connected neither to the substrate, nor to a well, is formed simultaneously with the FET by depositing and selectively etching a first doped oxide to cover a first region of the polycrystalline silicon, depositing an oppositely doped oxide over the remainder using the first oxide as mask, and oppositely doping the two regions of polycrystalline silicon by heat treatment. Alternatively, the second region can be doped by treatment in a gaseous phase or by ionic implantation, in either case using the first oxide as mask. Said regions are contiguous under the edge of the first doped oxide to form an autoaligned junction forming said floating diode which has a reverse conductivity notably greater than that of a junction in monocrystalline silicon, and easily reproduceable characteristics.

Semiconductor device having an antireflective coating

Abstract: A polycrystalline silicon layer provides an antireflective coating on a semiconductor surface of a photo-sensitive detector, the polycrystalline silicon layer containing from 25 to 45 atomic percent of oxygen and having a refractive index intermediate that of the semiconductor crystal and the exterior environment.

Thin film resistor

Abstract: A thin film resistor is formed of polycrystalline silicon which contains 2 to 45 atomic percent of oxygen and wherein the resistivity of the polycrystalline silicon film varies as a function of the amount of oxygen contained in the film and wherein the resistivity is substantially higher than polycrystalline silicon not containing oxygen.

Method of producing polycrystalline silicon ribbon

Abstract: A method of producing a ribbon of polycrystalline silicon, which includes contacting a moving surface carrying a layer of particulate semiconductor silicon, with a gaseous silicon source, is disclosed. The gaseous silicon source permeates the layer of particulate silicon and, with heat applied, deposits silicon that knits the silicon particles together to a continuous, coherent polycrystalline ribbon. The ribbon is then separated from the moving surface for further processing, for example, conversion to monocrystalline silicon.

Three mask self aligned IGFET fabrication process

Abstract: A process is disclosed for making a self-aligned IGFET having a polycrystalline silicon gate, using three masking steps. Layers of silicon dioxide, polycrystalline silicon, and silicon nitride are respectively deposited on the surface of a silicon substrate of a first conductivity type. With the first mask, openings are made in regions of these layers above the proposed location for the source and drain. The source and drain are then deposited in the substrate through these openings. The disclosed process continues, growing a silicon dioxide layer on the lateral surfaces of the polysilicon gate, exposed by these openings. Then a silicon nitride layer is deposited on all exposed surfaces and a second mask is employed to permit the removal by etching of this nitride layer from all portions except the proposed location of devices metallization at a first region over the gate, a second region over the source and a third region over the drain of the device. The polycrystalline silicon layer is then etched and removed from the field region of the device. Polysilicon material in the gate region is protected during this etching stop by the first nitride layer and the silicon dioxide layer grown over the lateral exposed surfaces of the gate. The nitride layer regions are then etched away and metallized contacts are formed to the source, drain and polycrystalline silicon gate regions by means of a third and last mask. Alternative steps are disclosed for making the gate and field oxide regions coplanar.

Process for fabricating narrow polycrystalline silicon members

Abstract: A process for fabricating narrow silicon members from a polycrystalline silicon layer, such as gates for MOS field-effect transistors. The edge of a mask is used to define a gap which exposes a narrow line on the underlying silicon layer. A doped region is formed in the silicon layer through the gap and then the layer is selectively etched. The critical dimensions of the fabricated silicon members are determined by the extent of diffusion of the dopant and are substantially independent of masking tolerances.

Controlled temperature polycrystalline silicon nucleation

Abstract: The diffusivity of an impurity in a layer of polycrystalline silicon is controlled by forming the polycrystalline silicon on a thin nucleating layer of polycrystalline silicon possessing a maximum {110} texture

Method of making a semiconductor device

Abstract: Portions of a polycrystalline silicon layer disposed on an insulator are removed after diffusing donor impurities into and through the regions to be removed. The regions to be retained are either previously or simultaneously doped with acceptor impurities. The method provides improved control of the size and the shape of the edges of the retained regions.

Polycrystalline Silicon on Coated Steel Substrates

Abstract: Steel is the most economical substrate for the deposition of silicon. At temperatures used for the chemical vapor deposition of silicon, however, a barrier layer must be used to prevent the diffusion of iron from the substrate into the silicon layer. Tungsten was found to be ineffective as a diffusion barrier when silicon was deposited by the thermal decomposition of silane at 900/sup 0/C and above. Borosilicate deposited by the oxidation of a silicon-diborane mixture was found to be an effective barrier at temperatures up to 1150/sup 0/C. Silicon layers deposited at low temperatures and high rates consist of small crystallites with a strong preferred (110) orientation, while those deposited at high temperatures and low rates consist of larger crystallites with more random orientation. Silicon p--n junctions deposited on borosilicate/steel substrates show poor electrical characteristics because of the high concentration of grain boundaries, and solar cells have low conversion efficiencies.

Process for defining polycrystalline silicon patterns

Abstract: A process and method for accurately defining polycrystalline silicon patterns from a masking member. The critical dimensions of the silicon patterns are controlled by a diffusion step. Self-limiting etching is achieved through use of an etchant which discriminates between doped and undoped polycrystalline silicon. The process which provides significant advantages in production processing, permits fabrication of narrower gates and smoother edges on elongated silicon strips.

Method of preparing a dielectric-isolated substrate for semiconductor integrated circuitries

Abstract: In the preparation of a dielectric-isolated substrate for semiconductor integrated circuits which comprises a plurality of silicon single crystalline islands in which circuit elements are formed, a region made of an alternate laminate of silicon polycrystalline layers and silicon oxide films for supporting the plurality of silicon single crystalline islands, and a silicon oxide film interposed between the silicon single crystalline islands and the support region for isolating each of the silicon single crystalline islands from the remaining ones and the support region, the formation of three to twelve silicon polycrystalline layers in the support region can remarkably reduce the bending of the substrate resulting from the growth stress of the silicon polycrystalline layers or from the difference in thermal expansion coefficients between the single crystalline silicon and the polycrystalline silicon, and therefore produces a dielectric-isolated substrate showing little bending.

Semiconductor field effect device having oxygen enriched polycrystalline silicon

Abstract: A Metal Insulator Semiconductor (MIS) field effect device has an oxygen-doped polycrystalline silicon layer on the field portion in order to prevent an unwanted parasitic inversion layer. The oxygen-doped polycrystalline silicon layer contains oxygen in the range of 2 to 40 atomic percent.

Polycrystalline silicon layers for solar cells

Abstract: Silicon layers on foreign substrates have been used for various device applications during the past fifteen years. The substrate requirements, the deposition techniques, and the characterization of properties of silicon layers are briefly reviewed. Polycrystalline silicon layers deposited on low‐cost substrates is a promising material for the fabrication of low‐cost solar cells. In this work, the thermal decomposition of silane and appropriate dopants has been used to deposit polycrystalline silicon layers containing a shallow p–n junction on steel, graphite, and metallurgical‐grade silicon substrates. When steel was used as a substrate, a borosilicate interlayer was used as a diffusion barrier to eliminate the formation or iron silicides. Silicon deposited on borosilicate/steel substrates exhibited poor microstructure, and the solar cells had low conversion efficiencies. Silicon deposited on graphite substrates showed considerably better microstructure, and conversion efficiencies of up to 1.5% have been...

Transmittance of air/SiO/SUB 2//polysilicon/SiO/SUB 2//Si structures

Abstract: Polycrystalline silicon films are presently used as the semitransparent gate electrodes in front-illuminated charge-coupled device (CCD) and charge-injection device (CID) image sensors. The transmittance of air/SiO/SUB 2//polysilicon/SiO/SUB 2//Si structures is calculated in spectral region between 0.4 and 1.0 /spl mu/. A proper choice of the thicknesses of the oxide films can substantially increase the transmittance over a narrow wavelength band or over the entire wavelength region of interest.

Method of simultaneously forming a polycrystalline silicon gate and a single crystal extension of said gate in silicon on sapphire MOS devices

Abstract: An improvement in polycrystalline silicon gate MOS integrated circuits made of silicon mesas on a sapphire substrate is provided. The improvement is an extension of a polycrystalline silicon gate onto the sapphire substrate as a single crystal layer. The single crystal layer is anisotrophically etched to slant its sidewalls. Metal contacts traversing the slanted sidewalls exhibit increased continuity and the single crystal layer exhibits improved conductivity. The polycrystalline silicon and single crystal silicon are formed simultaneously from a single source.

Etchant for etching silicon

Abstract: A solution comprising fluoroboric acid, nitric acid and ammonium fluoroborate is an isotropic etchant for monocrystalline and polycrystalline silicon which can be used to etch patterns which are delineated by etching masks formed of positive photoresists, thermally grown silicon oxide or deposited silox.

Integrated semiconductor structure with combined dielectric and PN junction isolation including fabrication method therefor

Abstract: This disclosure is directed to an integrated semiconductor structure with combined dielectric and PN junction isolation including the fabrication method therefor wherein a compensating P type channel is formed adjacent to the dielectric side isolation across one end portion of the electrically isolated N type collector region as well as around the bottom portion of the dielectric side isolation material or layer in order to overcome the N channel inversion (in P type semiconductor material) that is formed when the dielectric isolation material is silicon dioxide. The disclosed structure is an NPN transistor device having a buried sub-collector region of N+ type conductivity and further includes a P type substrate thereby providing a PN junction isolating substrate. The silicon dioxide material or layer is used to electrically isolate the side portions of the NPN transistor device from adjacent devices. The side dielectric isolation region is formed in a substantially V-shaped configuration with polycrystalline silicon forming the material located within the dielectric V-shaped member thereby providing a substantially planar surface for the integrated semiconductor structure.