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Showing papers on "Polycrystalline silicon published in 1976"


Patent
30 Nov 1976
TL;DR: A semiconductor switching element comprised by a high resistivity polycrystalline silicon resistor whose resistance irreversibly decreases to a small value at a threshold voltage upon the voltage across the resistor reaching the threshold voltage as mentioned in this paper.
Abstract: A semiconductor switching element comprised by a high resistivity polycrystalline silicon resistor whose resistance irreversibly decreases to a small value at a threshold voltage upon the voltage across the resistor reaching the threshold voltage. A semiconductor memory device is constituted by using the switching element as a memory cell and a semiconductor gate element for controlling the current flowing through the semiconductor switching element.

131 citations


Patent
27 Sep 1976
TL;DR: In this article, a self-aligned N-channel silicon-gate process is used to make a polycrystalline silicon layer which is also used as a gate for an MOS transistor and as an interconnection overlying field oxide.
Abstract: Resistor elements for MOS integrated circuits are made by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The resistor elements are in a part of a polycrystalline silicon layer which is also used as a gate for an MOS transistor and as an interconnection overlying field oxide. Resistors of this type are ideally suited for load devices in static RAM cells.

113 citations


Patent
Hu Shih-Ming1
02 Apr 1976
TL;DR: An integrated circuit structure and method for manufacturing same which provides for gettering with a backside layer of polycrystalline silicon. as discussed by the authors The gettering of unwanted impurities from the integrated circuits involves the deposition of a poly crystal silicon film on a semiconductor wafer prior to any or some high temperature processing steps.
Abstract: An integrated circuit structure and method for manufacturing same which provides for gettering with a backside layer of polycrystalline silicon. The gettering of unwanted impurities from the integrated circuits involves the deposition of a polycrystalline silicon film on a semiconductor wafer prior to any or some high temperature processing steps. The semiconductor body is then subjected to the normal semiconductor processing steps to form semiconductor devices on the surface opposite to the surface having the polycrystalline silicon layer. During these high temperature processing steps, unwanted impurities such as copper, iron, nickel, sodium and potassium ions move toward and into the polycrystalline silicon layer and thereby away from the semiconductor devices. This produces improved yield in the integrated circuit process.

98 citations


Journal ArticleDOI
TL;DR: In this article, the piezoresistive gage factor of boron-doped CVD polysilicon films was found to be between 15 and 27.2 ×10−2 on an aluminumoxide-insulated molybdenum substrate.
Abstract: The piezoresistive gage factor of boron‐doped CVD polysilicon films deposited with a boron‐to‐silicon ratio of 2×10−4–1.2 ×10−2 on an aluminum‐oxide‐insulated molybdenum substrate is found to be between 15 and 27. Annealing increases the gage factor. The higher the doping, the lower is the gage factor. Over the range 20–140 °C, the gage factor is not temperature sensitive if the boron‐to‐silicon ratio is higher than 2×10−3 during deposition. The temperature dependence increases as the doping concentration is decreased. Our analysis shows that the piezoresistive properties in polysilicon is mainly due to the bulk crystallites.

90 citations


Journal ArticleDOI
TL;DR: In this article, the passivation properties of oxygen-doped polycrystalline-silicon (SIPOS) films have been examined as a function of oxygen concentration, and the leakage currents of 800 V pnp transistors did not increase even after the chips were exposed to water vapor at 100°C and to sodium contamination at 200°C.
Abstract: Semi-insulating polycrystalline-silicon (SIPOS) films have been used as a replacement of a silicon dioxide passivation layer of planar devices. The SIPOS films are chemically vapordeposited polycrystalline-silicon doped with oxygen or nitrogen atoms. The passivation properties of oxygen-doped SIPOS films have been examined as a function of oxygen concentration. The npn and pnp transistors rated at 800 V and 2500 V have been produced by the SIPOS process in planar-like structures with field-limiting rings. The leakage currents of 800 V pnp transistors did not increase even after the chips were exposed to water vapor at 100°C and to sodium contamination at 200°C. Thus, the SIPOS transistors can be packaged in low-cost molded epoxy as well as metal cans. Furthermore, 10 kV SIPOS transistors with multiple rings have been fabricated and their operation has been found to be stable.

72 citations


Patent
02 Dec 1976
TL;DR: In this paper, a method of producing a semiconductor device comprises removing all of the masking films used for forming desired semiconductor regions in the substrate, newly forming a first insulation film and selectively forming a second insulation film on predetermined portions of the first insulation by the use of a polycrystalline silicon film as the mask.
Abstract: A method of producing a semiconductor device comprises removing all of the masking films used for forming desired semiconductor regions in the substrate, newly forming a first insulation film and selectively forming a second insulation film on predetermined portions of the first insulation film by the use of a polycrystalline silicon film as the mask.

55 citations


Patent
Vincent Leo Rideout1
09 Feb 1976
TL;DR: In this article, a high electrical conductivity word line is electrically connected to the gate of the FET by means of a "self-registering" metallic line to polysilicon gate contact.
Abstract: Fabricating an integrated circuit array of FET one-device memory cells which includes providing a semiconductive substrate of a first conductive type; delineating field insulation regions; delineating polycrystalline silicon gate regions employing an oxidation barrier masking layer; introducing active impurities of a second and opposite conductive type into predetermined regions of the substrate to provide doped bit lines (FET drains), connection regions (FET sources), and lower conductive electrodes of the storage capacitors; next delineating upper polycrystalline silicon electrodes of the storage capacitors; growing silicon dioxide insulation over all portions of the structure except over the FET gate regions which are protected by the oxidation barrier masking layer; removing the oxidation barrier masking layer over the FET gates with an etchant; delineating contact holes to polycrystalline silicon capacitor electrodes and to FET sources and drains in circuits peripheral to the array of memory cells; and delineating the metallic-type high-conductivity electrical interconnection word line pattern. This fabrication procedure requires five basic lithographic (pattern delineating) masking steps. A high electrical conductivity word line is electrically connected to the gate of the FET by means of a "self-registering" metallic line to polysilicon gate contact. This gate contacting technique is relatively more tolerant to misregistration between the FET gate lithographic pattern and the metallic interconnection line lithographic pattern than are previously known fabrication methods.

55 citations


Patent
14 Apr 1976
TL;DR: In this article, a metal-insulator semiconductor (MIS) device is manufactured by initially forming, on a semiconductor substrate, an insulating film having a hole therethrough and depositing silicon on the substrate to form a first monocrystalline silicon film in the hole and a poly-crystalline poly-poly-silicon film on the insulating material.
Abstract: A metal-insulator semiconductor (MIS) device is manufactured by initially forming, on a semiconductor substrate, an insulating film having a hole therethrough and depositing silicon on the substrate to form a first monocrystalline silicon film in the hole and a polycrystalline silicon film on the insulating film. Then, a further insulating film is formed on the first silicon film, and a second silicon film is formed on the further insulating film. The second silicon film and the further insulating film are removed, so that the monocrystalline and polycrystalline parts of the first silicon film are exposed at both sides of the remaining part of the second silicon film and the further insulating film. Finally, an impurity is diffused to form a source and a drain region in the monocrystalline silicon film and conductive layers of polycrystalline silicon are disposed contiguous to the source and drain regions.

54 citations


Patent
09 Sep 1976
TL;DR: In this paper, a method of manufacturing a metal silicide pattern with respect to which two electrode zones are to be provided in a self-registering manner is described. But this method requires the use of polycrystalline silicon and cannot withstand high temperatures.
Abstract: A method of manufacturing a metal silicide pattern with respect to which two electrode zones are to be provided in a self-registering manner. According to the invention the pattern is provided in the form of a layer of polycrystalline silicon and, by selective oxidation and masking, only the upper surface of the pattern is exposed to the silicide formation so that passivation problems and short circuit are avoided. The use of silicides which cannot withstand high temperatures is also possible.

51 citations


Journal ArticleDOI
TL;DR: In this paper, a double-layer polycrystalline-silicon (SIPOS) film is employed as a replacement of a thick silicon dioxide layer in C/MOS-IC's of channel-stopperless structure and exhibits excellent field-passivating properties.
Abstract: A semi-insulating polycrystalline-silicon (SIPOS) film doped with oxygen atoms is deposited on the surface of silicon substrates by a chemical vapor reaction of silane and nitrous oxide in nitrogen ambient, and has been studied for the surface passivation of MOS-IC's, in particular, C/MOS-IC's of channel-stopperless structure. SIPOS films are semi-insulating and intrinsically neutral. A double-layer system consisting of 3000 A SIPOS and 6000 A SiO2 films is employed as a replacement of a thick silicon dioxide layer in C/MOS-IC's of channel-stopperless structure and exhibits excellent field-passivating properties, namely, a small drain-source leakage current, a high drain breakdown voltage, and a high parasitic threshold voltage. Furthermore, the silicon surface passivated by SIPOS films shows high stability under a severe bias-temperature stress. It is concluded that C/MOS-IC's passivated by SIPOS films are not required to have a channelstopper diffusion region and can be operated at high applied voltages, which leads to higher integrating density and higher reliability.

47 citations


Patent
06 Feb 1976
TL;DR: In this article, a monocrystalline p-type silicon substrate is employed which has its 1-0-0 crystallographic planes at a face on which an n epitaxial layer was grown.
Abstract: The invention concerns a semiconductor structure having a compatible mixture of bipolar and unipolar transistors. In that structure a monocrystalline p-type silicon substrate is employed which has its 1-0-0 crystallographic planes at a face on which an n epitaxial layer was grown. The epitaxial layer is divided into electrically isolated parts by V-grooves that extend down through the epitaxial layer and have their apices terminating in the substrate. A thin silicon dioxide film coats the V-grooves and those grooves are filled with polycrystallie silicon. Where it is desired to use the polycrystalline silicon as the insulated gate of a field effect transistor, the polycrystalline silicon is electrically conductive. Bases for bipolar transistors are formed by diffusion of an appropriate impurity into selected areas of the epitaxial layer. The emitters, drains, and sources are formed by diffusion of a different impurity. Each field effect transistor has its drain and source on adjacent parts of the epitaxial layer which are separated by the V-groove in which the gate is situated. The base and emitter of a bipolar transistor may be situated on one isolated part and the collector may be situated on an adjacent part separated by a V-groove having an electrically conductive polycrystalline filler.

Patent
16 Jan 1976
TL;DR: In this article, a complementary gate field effect transistor structure with complementary p-channel and n-channel devices in the same semiconductor substrate and a process for fabricating the structure incorporate oxide isolation of the active device regions, counterdoping of the p-well with impurities of opposite type to obtain a composite doping profile, reduction of Qss in the isolation oxide, doping of the gate and field oxides with a chlorine species and phosphorus doping of polycrystalline silicon gates.
Abstract: A complementary insulated gate field effect transistor structure having complementary p-channel and n-channel devices in the same semiconductor substrate and a process for fabricating the structure incorporate oxide isolation of the active device regions, counterdoping of the p-well with impurities of opposite type to obtain a composite doping profile, reduction of Qss in the isolation oxide, doping of the gate and field oxides with a chlorine species and phosphorus doping of the polycrystalline silicon gates.

Patent
06 Jan 1976
TL;DR: A polycrystalline silicon body is produced by shaping silicon powder having an average particle size less than 0.2 micron into a green body and sintering the body to a density of at least 60% of the theoretical density of silicon.
Abstract: A polycrystalline silicon body is produced by shaping silicon powder having an average particle size less than 0.2 micron into a green body and sintering the body to a density of at least 60% of the theoretical density of silicon.

Patent
29 Nov 1976
TL;DR: In this paper, a process for the low cost, high volume production of polycrystalline high purity silicon by a vapor phase reduction of a halosilane, with hydrogen, is described.
Abstract: A process is provided for the low cost, high volume production of polycrystalline high purity silicon by a vapor phase reduction of a halosilane, with hydrogen, the resulting polycrystalline silicon being particularly suited for use in the production of single crystal silicon for the manufacture of semiconductor devices, solar cells, and the like. The process of the invention involves the reaction of metallurgical grade silicon (of a purity of about 98%) with a halogen or hydrogen halide to form a halosilane intermediate; the purification of the halosilane and of hydrogen; the separate pre-heating of the purified halosilane and of the purified hydrogen to a temperature range above the chemical reaction temperature of the halosilane and the hydrogen; injection of the halosilane and the hydrogen into a continuous flow reduction tubular reactor wherein the feed materials are instantaneously mixed in a manner which causes chemical reaction to be initiated followed by nucleation and growth of solid high purity silicon particles as the reaction mass flows through the tubular reactor; introduction of the solid-gas reaction mass stream into a cyclone type separator wherein the high purity silicon particles are collected and separated from the gas stream and ejected from the bottom of pg,2 the separator; emitting the gas stream from the top of the separator and conducting the gas stream to a condenser-scrubber system wherein unreacted hydrogen is separated and then recycled to the hydrogen pre-heater for re-use, unreacted silicon halosilane is separated and recycled to the intermediate pre-heater for re-use, and reaction product hydrogen halide is separated and recycled to the silicon halosilane generator for re-use.

Patent
04 Jun 1976
TL;DR: In this paper, the p-n junction is formed by depositing successive layers of polycrystalline silicon containing appropriate dopants over supporting substrates of a member selected from the group consisting of metallurgical-grade polycrystaline silicon, graphite and steel coated with a diffusion barrier.
Abstract: Low-cost polycrystalline silicon solar cells supported on substrates are prepared by depositing successive layers of polycrystalline silicon containing appropriate dopants over supporting substrates of a member selected from the group consisting of metallurgical-grade polycrystalline silicon, graphite and steel coated with a diffusion barrier of silica, borosilicate, phosphosilicate, or mixtures thereof such that p-n junction devices are formed which effectively convert solar energy to electrical energy. To improve the conversion efficiency of the polycrystalline silicon solar cells, the crystallite size in the silicon is substantially increased by melting and solidifying a base layer of polycrystalline silicon before depositing the layers which form the p-n junction.

Patent
06 Jul 1976
TL;DR: In this paper, the solar cell product produced by the above-process may be fabricated in large surface area configurations, suitable for terrestrial as well as extra-terrestrial use, at relatively low cost.
Abstract: The process comprises the following steps: (1) forming a glass sheet which defines a substrate layer for the solar cell product; (2) forming a diffusion barrier layer on at least one surface of the substrate; (3) forming a first electrically-conductive layer on the diffusion barrier, the first electrically-conductive layer being a first electrode in the solar cell product; (4) depositing small-grain polycrystalline silicon in a thin film, i.e., 10-100 micrometers, on the first electrode layer; (5) recrystallizing, typically by heating, the deposited polycrystalline silicon until it reforms into large-grain polycrystalline or single-crystal silicon; (6) forming a PN junction in the recrystallized silicon layer; and (7) forming a second electrically-conductive layer on the recrystallized silicon layer, the second electrically-conductive layer being a second electrode in the solar cell product. The solar cell product produced by the above-process may be fabricated in large surface area configurations, suitable for terrestrial as well as extra-terrestrial use, at relatively low cost.

Journal ArticleDOI
TL;DR: The use of a polycrystalline silicon p-n junction structure deposited on low-cost substrates is a promising approach for the fabrication of low cost solar cells.
Abstract: The use of a polycrystalline silicon p - n junction structure deposited on low-cost substrates is a promising approach for the fabrication of low-cost solar cells. Metallurgical-grade silicon, with a purity of about 98% and a cost of about $1/kg, was cast into plates in a boron nitride container and used as substrates for the deposition of solar cell structures. The substrates were polycrystalline with millimeter size crystallites. Solar cells of the configurations n > + -silicon/p-silicon/metallurgical silicon and n + -silicon/p + -silicon/metallurgical silicon were prepared by the thermal decomposition of silane and the thermal reduction of trichlorosilane containing appropriate dopants. The AMO efficiencies of n + -silicon/ p -silicon/metallurgical silicon solar cells were up to 2.8% (with no anti-reflection coatings) and were limited by the grain boundaries in the p -layer. The grain boundary effects were reduced by increasing the dopant concentration in the p -layer, and AMO efficiencies of about 3.5% were obtained from n + -silicon/p + -silicon/metallurgi silicon solar cells.

Patent
Alfred C. Ipri1
18 Nov 1976
TL;DR: In this paper, a resistive device for use as a current feedback loop in an integrated CMOS shift register circuit is made of an island of polycrystalline silicon with a sheet resistivity of from 10 6 to 10 8 ohms per square.
Abstract: A resistive device for use as a current feedback loop in an integrated CMOS shift register circuit is made of an island of polycrystalline silicon with a sheet resistivity of from 10 6 to 10 8 ohms per square. The polycrystalline silicon island has two contacts thereon fashioned in the manner of MOS source and drain contacts and a dummy polycrystalline silicon insulated gate contact thereon. The device structure is designed to be and is fully compatible with CMOS mesa processing. The method for making the device incorporates into the processing steps for CMOS manufacture the formation of polycrystalline silicon islands on the substrate along with monocrystalline silicon islands. In the process, the polycrystalline silicon island is doped, through source and drain mask openings, with impurities of the same conductivity type as that predominating in the polycrystalline silicon island.

Patent
13 Feb 1976
TL;DR: A polycrystalline silicon layer is deposited by chemical vapor deposition method at a predetermined location on an oxide film grown by thermal oxidation on a surface of a monocrystal silicon substrate.
Abstract: A polycrystalline silicon layer is deposited by chemical vapor deposition method at a predetermined location on an oxide film grown by thermal oxidation on a surface of a monocrystal silicon substrate. Nitrogen ions are implanted in the outer surface of the polycrystalline silicon layer and the exposed surface of the oxide film. The whole surfaces are oxidized by wet oxidation so as to form a thick oxide layer at the surface of the oxide film which is not covered by the polycrystalline silicon layer.

Patent
William G. Oldham1
10 Feb 1976
TL;DR: In this paper, a low resistance crossunder (interconnect) for n-channel, silicon gate integrated circuits, particularly useful where shallow source and drain regions are employed, is presented.
Abstract: A low resistance crossunder (interconnect) for n-channel, silicon gate integrated circuits, particularly useful where shallow source and drain regions are employed. The crossunder is formed in the substrate from a doped polycrystalline silicon layer which contacts the substrate at the site of the crossunder. The crossunder is formed without substantial alterations to the standard process flow.

Patent
Mario Ghezzo1
20 Sep 1976
TL;DR: In this article, a method of forming a conductive member of N-type conductivity polycrystalline silicon on the surface of an insulating substrate with at least one side of the substrate sloping gradually to the surface was proposed.
Abstract: A method of forming a conductive member of N-type conductivity polycrystalline silicon on the surface of an insulating substrate with at least one side thereof sloping gradually to the surface of the insulating substrate utilizing the location dependent diffusivity of doping impurities in the polycrystalline silicon formed on the surface of the insulating substrates and also utilizing the etch inhibiting properties of polycrystalline silicon doped with boron impurities.

Patent
Eugene Greenstein1
13 Dec 1976
TL;DR: In this paper, a monolithic integrated circuit structure with an integral high value surge protection resistor of polycrystalline silicon on a thermally grown thick silicon dioxide plateau having no surface diffusion regions thereunder is presented.
Abstract: A monolithic integrated circuit structure having an integral high value surge protection resistor of polycrystalline silicon on a thermally grown thick silicon dioxide plateau having no surface diffusion regions thereunder. The structure can be made by merely adding intermediate steps to existing integrated circuit processing. It is capable of absorbing transients of hundreds of volts.

Patent
02 Feb 1976
TL;DR: In this article, a method for fabricating a semiconductor device includes the steps of forming a first polycrystalline silicon layer containing oxygen atoms on the semiconductor layer, forming a second poly-crystalized silicon layer with nitrogen atoms on it, and removing a predetermined part of the first and second poly crystalline silicon layers to form an opening therein, and diffusing impurity material into the semiconducting layer through the opening in order to form a diffused region.
Abstract: A method for fabricating a semiconductor device includes the steps of forming a first polycrystalline silicon layer containing oxygen atoms on a semiconductor layer, of forming a second polycrystalline silicon layer containing nitrogen atoms on the first polycrystalline silicon layer, of removing a predetermined part of the first and second polycrystalline silicon layers to form an opening therein, and of diffusing impurity material into the semiconductor layer through the opening in order to form a diffused region. The fabricating process can be remarkably simplified.

Patent
28 Sep 1976
TL;DR: In this paper, the method of coating includes the step of carbonizing the surface of such a substrate and then contacting the carbonized surface of the ceramic with the molten silicon, whereupon a large-grain silicon coating is produced wherever the ceramic is carbonized.
Abstract: It is desirable to coat large area, thin sheets of large-grain polycrystalline silicon on an inexpensive ceramic substrate for use in solar cell applications and the like. Such ceramic substrates as are used are chosen from those having thermal expansion coefficients similar to those of silicon. The ceramics meeting these requirements, for example mullite, alumina and zirconia, when brought into contact with molten silicon, however, are not wet by the silicon and no coating takes place. In this invention the method of coating includes the step of carbonizing the surface of such a substrate and then contacting the carbonized surface of the ceramic with the molten silicon, whereupon a large-grain silicon coating is produced wherever the ceramic is carbonized. In this way the ceramic of the type which is not wet by molten silicon can be successfully coated with silicon.

Patent
Gerald Rogers1
15 Nov 1976
TL;DR: An MOS capacitor for N-channel silicon gate integrated circuits employs a polycrystalline silicon layer as one plate, and a silicon oxide dielectric. as discussed by the authors The lower plate consists of a region which is implanted by an ion beam to produce a depleted region.
Abstract: An MOS capacitor for N-channel silicon gate integrated circuits employs a polycrystalline silicon layer as one plate, and a silicon oxide dielectric. The lower plate consists of a region which is implanted by an ion beam to produce a depleted region. This device has a constant capacitance regardless of gate voltage in normal operating logic levels.

Patent
02 Nov 1976
TL;DR: In this paper, the authors proposed a method of producing a semiconductor device, comprising the steps of forming a polycrystalline semiconductor layer on the exposed surface of a single crystalline polysilicon substrate, the substrate containing an impurity of one conductivity type and the poly-stalline layer an impurate of the other conductivity types, and heating the polycrystaline layer for the activation thereof at a temperature substantially preventing the impurity contained therein from being diffused into the substrate.
Abstract: A method of producing a semiconductor device, comprising the steps of forming a polycrystalline semiconductor layer on the exposed surface of a single crystalline semiconductor substrate, the substrate containing an impurity of one conductivity type and the polycrystalline layer an impurity of the other conductivity type, and heating the polycrystalline layer for the activation thereof at a temperature substantially preventing the impurity contained therein from being diffused into the substrate. The crystal of the substrate is kept free from lattice defect since the impurity is not diffused thereinto. In addition, this method prevents a short circuit from occurring between semiconductor regions of differing conductivity types which would otherwise be caused by deviation in the location of a mask used in the photoetching step.

Patent
09 Apr 1976
TL;DR: A Schottky barrier is formed between a semiconductor substrate and a metal contact and stabilized by a polycrystalline silicon layer containing oxygen in the range between 2 and 45 atomic percent and surrounding a peripheral portion of the metal contact.
Abstract: A Schottky barrier is formed between a semiconductor substrate and a metal contact and stabilized by a polycrystalline silicon layer containing oxygen in the range between 2 and 45 atomic percent and surrounding a peripheral portion of the metal contact to improve the breakdown voltage characteristics of the device. The invention is applicable to Schottky barrier type diodes, bipolar transistors, field effect transistors and so on.

Patent
14 Jan 1976
TL;DR: In this article, an n-layer of single crystal silicon over polycrystalline silicon was used to produce thin layers of silicon on insulating substrates, such as silicon dioxide or poly crystal silicon, using an etch which will only etch the n++ or p++ region and will stop when the n- or p- region has been reached.
Abstract: This disclosure relates to methods of producing thin layers of silicon as well as thin layers of silicon on insulating substrates such as silicon dioxide or polycrystalline silicon by forming either an n- layer of single crystal silicon over a p++ layer of single crystal silicon or a p- layer of single crystal silicon over an n++ layer of single crystal silicon and then removing either the n++ or p++ single crystal substrate, as the case may be, by utilizing an etch which will only etch the n++ or p++ region and will stop when the n- or p- region, as the case may be, has been reached.

Journal ArticleDOI
John Y. W. Seto1
TL;DR: In this article, a polycrystalline silicon films implanted with 1×1012 to 7.8×1015/cm2 doses of boron and phosphorus were isochronally annealed up to 1100°C.
Abstract: Polycrystalline silicon films implanted with 1×1012 to 7.8×1015/cm2 doses of boron and phosphorus were isochronally annealed up to 1100 °C. Annealing below 600 °C removes the radiation damage created by the implantation process. For doses higher than 1×1014/cm2 an abrupt decrease in sheet resistance takes place between 650 and 700 °C. Hall measurements show that this decrease is the result of a large increase in both the carrier concentration and mobility. Electron‐reflection diffraction patterns show that recrystallization takes place within this temperature range. Annealing above 700 °C only causes a small further decrease in the sheet resistance.

Patent
10 Dec 1976
TL;DR: In this article, a charge transfer device (C.T.D) with polycrystalline silicon electrodes which are provided on a nitride layer has been proposed, where electrodes of a second metallization layer, for example, of aluminium, are provided via said apertures.
Abstract: The invention relates to a charge transfer device (C.T.D.) with polycrystalline silicon electrodes which are provided on a nitride layer. The nitride layer has apertures between the polyelectrodes. Electrodes of a second metallization layer, for example, of aluminium, are provided via said apertures. The charge storage capacities per surface unit (and with equal voltages) can be made equal by subjecting the device for a short period of time to an oxidation treatment prior to providing the Al electrodes so that the oxide layer in the apertures can become thicker than below the Si electrodes.