Showing papers on "Polycrystalline silicon published in 1977"

Evidence for surface asperity mechanism of conductivity in oxide grown on polycrystalline silicon

Abstract: High conductivity observed in oxides grown on polycrystalline silicon has been previously speculated as being due to asperities on the silicon surface, which enhance the oxide field. Direct evidence of these asperities is shown here in SEM micrographs. The presence of the asperities is strongly correlated with the oxide conductivity (as controlled by the oxidation temperature).

Method of making a high density floating gate electrically programmable ROM

Abstract: An N-channel, double level polysilicon, MOS read only memory or ROM array is electrically programmable by floating gates which are interposed between the gate oxide and control gates formed by polycrystalline silicon row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate. A very dense array is obtained by a simplified manufacturing process which is generally compatible with standard N-channel silicon gate technology. Parallel strips of gate oxide, polycrystalline silicon, and nitride oxidation mask are applied, field oxide is grown, then a perpendicular pattern of strips is etched, removing field oxide as well as parts of the original strips, providing a diffusion mask. The second level polysilicon is then applied as strips overlying the original strips.

Annealing of surface states in polycrystalline‐silicon–gate capacitors

Abstract: Charge injection at the polycrystalline‐silicon–SiO2 interface of phosphorus‐doped, polycrystalline‐silicon–gate MOS capacitors can cause excess currents during quasistatic C‐V measurements and hysteresis in high‐frequency C‐V curves. The effect of annealing in nitrogen and forming gas at temperatures between 300 and 850 °C on these instabilities as well as on surface states Nss and surface charge Qss has been studied. To distinguish effects occurring at the substrate Si‐SiO2 interface from effects occurring at the polycrystalline‐silicon–SiO2 interface, measurements are also reported of the effect of annealing Si‐SiO2 structures without gate electrodes, in the same temperature range and atmospheres. There is a minimum in Nss after anneal of samples without electrodes in forming gas at 400 °C. Reaction with hydrogen is essential to anneal surface states; thermal anneal is not sufficient. Some reaction, possibly formation of SiO, occurs above 450 °C that increases Nss and may increase Qss. Anneal of polycr...

Reduction of grain boundary recombination in polycrystalline silicon solar cells

Abstract: The possibility of increasing the carrier collection efficiency in polycrystalline silicon by means of a heavily doped region near the grain boundaries is investigated. Phosphorous dopant is preferentially introduced into the grain boundaries of p‐type material by a low‐temperature diffusion process. A subsequent high‐temperature diffusion forms a highly n‐doped skin covering each grain. The resulting junction around each grain surface collects electrons which might otherwise recombine at the grain boundaries. This grain boundary doping scheme makes possible an increase in the conversion efficiency of polycrystalline silicon solar cells in which the grain structure is columnar.

Electrically programmable and electrically erasable MOS memory cell

Abstract: An MOS memory cell which includes a floating gate charged from the substrate by avalanche injection. Charge is removed from the floating gate to an erasing gate by tunneling. Sharp edges on the polycrystalline silicon floating gate provide an enhanced electric field to overcome the silicon/silicon oxide barrier, thus permitting charge to be transferred from the floating gate to the erasing gate.

Arsenic implantation into polycrystalline silicon and diffusion to silicon substrate

Abstract: Arsenic implantation into polycrystalline silicon and drive‐in diffusion to silicon substrate have been investigated by MeV He+ backscattering analysis and also by electrical measurements. The range distributions of arsenic implanted into polycrystalline silicon are well fitted to Gaussian distributions over the energy range 60–350 keV. The measured values of RP and ΔRP are about 10 and 20% larger than the theoretical predictions, respectively. The effective diffusion coefficient of arsenic implanted into polycrystalline silicon is expressed as D=0.63 exp[(−3.22 eV/kT)] and is independent of the arsenic concentration. The drive‐in diffusion of arsenic from the implanted polycrystalline silicon layer into the silicon substrate is significantly affected by the diffusion atmosphere. In the N2 atmosphere, a considerable amount of arsenic atoms diffuses outward to the ambient. The outdiffusion can be suppressed by encapsulation with Si3N4. In the oxidizing atmosphere, arsenic atoms are driven inward by growing...

High density N-channel silicon gate read only memory

Abstract: An N-channel silicon gate read only memory or ROM array of very high bit density is made by providing columns in the form of parallel N+ moats separated by field oxide and removing small areas of the field oxide in a pattern of "1's" and "0's" according to the ROM program. Gate oxide is grown in the areas where field oxide is removed, and parallel polycrystalline silicon strips are laid down over the field oxide and gate oxide areas normal to the moats, providing the rows. The ROM may be made as part of a standard double level poly, N-channel, self-aligned silicon gate process. The columns may include an output line and several intermediate lines for each ground line so that a virtual ground format is provided. An implant step may be used to avoid the effects of exposed gate oxide so that zero-overlap design rules are permitted.

Si{hd 3{b N{HD 4 {B formed by nitridation of sintered silicon compact containing boron

Abstract: A polycrystalline silicon nitride body is produced by shaping a particulate mixture of silicon powder and boron into a green body, sintering the body to a density ranging from 60% to 75% of the theoretical density of silicon, said sintered body having pores which are interconnecting and open to the surface of the body, and reacting said sintered body with gaseous nitrogen to convert it to silicon nitride.

Semiconductor device having a miniature junction area and process for fabricating same

Abstract: In a method for fabricating a semiconductor device, a polycrystalline film deposited on a main surface of a substrate is subjected to selective oxidation to form polycrystalline silicon electrode wiring paths separated by silicon oxide. An impurity of a conductivity type opposite to that of the substrate is introduced through at least one of the wiring paths into the substrate. Also disclosed is a novel semiconductor device fabricated according to this process which has a reduced junction area and a shortened junction-to-electrode distance.

Enhanced crystallinity of silicon films deposited by CVD on liquid layers (CVDOLL process): Silicon on tin layers in the presence of hydrogen chloride

Abstract: Chemical vapor deposition of silicon on a graphite substrate coated with a 5‐μm‐thick fluid tin layer provides a possibility for the production of large grained polycrystalline silicon layers. Using silane as a source material, crystallites can be produced with a mean grain size of about 20 μm, compared with 5 μm on a substrate without fluid layer. The grain size can be further enhanced by adding HCl as an etching agent to the gas phase. Mean crystallite sizes of 100 μm and larger can be obtained by the use of a fluid layer and a proper combination of SiH4 and HCl.

Use of electron‐trapping region to reduce leakage currents and improve breakdown characteristics of MOS structures

Abstract: A trapping layer of W (≈1014 atoms/cm2) has been deposited between 70 A of thermal silicon dioxide grown from a polycrystalline silicon substrate and 520 A of deposited pyrolytic silicon dioxide in an MOS structure to reduce high leakage currents and low‐voltage breakdowns associated with asperities at the polycrystalline Si–thermal SiO2 interface. MOS structures without the W layer but with the pyrolytic SiO2 layer were also found to be effective. This improvement is ascertained to be due to localized electron trapping in the W or pyrolytic oxide layer at low average fields which reduces the locally high fields and therefore high dark currents associated with the asperities. At higher average fields uniform trapping is believed to be dominant. This uniform effect can also enhance the breakdown characteristics if the trapped charge is not detrapped by the applied field.

Gate electrode for MNOS semiconductor memory device

Abstract: Optimized switching and retention characteristics of an MNOS memory device are obtained by using as a gate electrode material either metals or semi-metals having a high work function, in conjunction with a gate dielectric layer having a low density of trapping states throughout its volume. The preferred gate electrode materials are either titanium or p + -doped polycrystalline silicon.

Polycrystalline silicon etching with tetramethylammonium hydroxide

Abstract: A family of etchants for polycrystalline silicon based upon an aqueous solution of NR4 OH, where R is an alkyl group, has a relatively low etching rate enabling the exercise of better control over the delineation of fine structures

Semiconductor devices and method of manufacturing the same

Abstract: The semiconductor device comprises a semiconductor substrate, a polycrystalline silicon semiconductor body extending upwardly from a portion of the surface of the semiconductor substrate and containing an impurity at a substantially uniform concentration, and a metal electrode disposed on the top surface of the polycrystalline silicon semiconductor body. The metal electrode extends in the lateral direction beyond the periphery of the top surface of the polycrystalline silicon semiconductor body.

The lateral diffusion of boron in polycrystalline silicon and its influence on the fabrication of sub-micron MOSTs

Abstract: The fabrication of submicron silicon gate MOSTs by the lateral diffusion of boron in polycrystalline silicon (polysilicon) requires knowledge of the relative diffusion kinetics of boron in both polysilicon and silicon dioxide. The kinetics were determined using polysilicon layers deposited by pyrolysis of silane and diffusion from a BN source. An activation energy of 3.26 ± 0.10 eV was found for both lateral and perpendicular diffusion in polysilicon. Values for the pre-exponential rate constants in the Arrhenius relationship of 88.0, 40.0 and 5.73 cm2 s−1 were found for lateral diffusion in polysilicon deposited at 720, 770 and 820°C respectively. In comparison, a value of 27.6 cm2 s−1 was found for perpendicular diffusion in polysilicon deposited at 770°C. Corresponding values of 1.76 eV and 4.37 × 10−7 cm2 s−1 were found for the conversion of silicon dioxide to borosilicate glass in the region of exposed thin oxide immediately adjacent to the polysilicon gate. Over the temperature range studied, these results give a maximum ratio between the gate length and gate oxide thickness of about 15 in comparison to the ratio of around 40 commonly used for conventional MOSTs. Values for the corresponding diffusion constants were also calculated from the rate constants using the commonly-assumed complementary error function profile. Measurement of the diffusion profiles for electrically active boron shows, however, that the erfc profile is not entirely valid.

Planar semiconductor devices and method of making the same

Abstract: A semiconductor device includes a region of polycrystalline silicon on a portion of the surface of a body of semiconductor material. A layer of oxidized polycrystalline silicon is also on the semiconductor material body and extends to the polycrystalline silicon region. The surface of the silicon oxide layer is substantially coplanar with the surface of the polycrystalline silicon region so that a metal film conductor can be easily provided over the semiconductor device. The polycrystalline silicon region may be the gate of an MOS transistor or a conductive region of any type of semiconductor device. The semiconductor device is made by forming a polycrystalline silicon layer over the semiconductor material body, forming a mask on a portion of the polycrystalline silicon layer, reducing the thickness of the unmasked portion of the polycrystalline silicon layer and then oxidizing the unmasked portion of the polycrystalline silicon layer to form the oxide layer.

Field-effect transistor structure in multilevel polycrystalline silicon

Abstract: An ion-implanted lightly-doped polycrystalline silicon strip in an N-channel silicon gate integrated circuit device functions as a resistor element which exhibits transistor action. The impedance of the resistor element changes in response to the voltage on an underlying polycrystalline silicon area which is insulated from the resistor element by a thin silicon oxide layer. This resistor element is used as a load in a static RAM cell array and lowers the power dissipation of the array; the resistance is high for stored zeros and low for stored logic ones.

Semiconductor integrated circuit

Abstract: PURPOSE:To achieve the decrease in costs and the increase in reliability by composing all layers includijng wiring with single-crystalline or polycrystalline silicon and silicon oxide thereby forming a multilayer structure.

A Radiation Hardened Field Oxide

Abstract: This paper describes the results of a radiation-tolerant field oxide development compatible with both MOS and bipolar technologies. Data is presented which illustrates that nonguardbanded devices utilizing conventional field oxide structures cannot be expected to survive an ionizing radiation dose above approximately 5 × 104 rads (Si) due to inversion of p-type silicon surfaces under metallized areas. The radiation hardened oxide was evaluated with both aluminum and polycrystalline silicon gate MOS structures which conclusively demonstrates that this oxide eliminates the field inversion problem for radiation levels in excess of 106 rads (Si).

Semiconductor integrated circuit with implanted resistor element in second-level polycrystalline silicon layer

Abstract: Integrated circuit resistor elements ideally suited for load devices in static MOS RAM cells are made in second-level polycrystalline silicon by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The cell size is reduced as the resistors can overly the first-level poly or MOS transistors. The second-level poly does not form transistor gates, so it is less critical, and an efficient layout provides a very small cell area.

Ceramic coated with molten silicon

Abstract: It is desirable to coat large area, thin sheets of large-grain polycrystalline silicon on an inexpensive ceramic substrate for use in solar cell applications and the like. Such ceramic substrate as are used are chosen from those having thermal expansion coefficients similar to those of silicon. The ceramics meeting these requirements, for example mulite, alumina and zirconia, when brought into contact with molten silicon, however, are not wet by the silicon and no coating takes place. In this invention the structure includes an interface layer comprising carbon on the surface of such a substrate to render the surface wettable by molten silicon. With this interface layer the ceramic of the type which is not wet by molten silicon can be successfully coated with silicon.

Field effect transistors with polycrystalline silicon gate self-aligned to both conductive and non-conductive regions and fabrication of integrated circuits containing the transistors

Abstract: A field effect transistor (FET) with a unique gate structure is disclosed wherein the polycrystalline silicon (polysilicon) gate is self-aligned on its ends with respect to the conductive source and drain regions, and is self-aligned on its sides with respect to the nonconductive field isolation regions. The boundaries of these conductive and nonconductive regions determine the boundaries of the channel region of the FET. This double self-alignment feature results in a polysilicon gate, the lateral dimensions and location of which correlate directly with the lateral dimensions and location of the channel region of the FET. The unique gate fabrication technique employed according to the present invention comprises delineating lithographic patterns twice in the same polysilicon layer using the same oxidation barrier masking layer; whereby the first lithographic pattern delineates the FET device regions, and the next lithographic pattern forms the gate regions wherever the two patterns cross each other (i.e., wherever they delineate a common area).

Polycrystalline silicon semiconducting material by nuclear transmutation doping

Abstract: A NTD semiconductor material comprising polycrystalline silicon having a mean grain size less than 1000 microns and containing phosphorus dispersed uniformly throughout the silicon rather than at the grain boundaries.

Hot pressing of silicon nitride using magnesium silicide

Abstract: A dense polycrystalline silicon nitride body is produced by hot-pressing a particulate mixture of silicon nitride and a magnesium silicide additive.

An integrated optical waveguide and charge-coupled-device image array

Abstract: The device structure and experimental operation of an integrated optical waveguide and charge-coupled device (CCD) detector array are considered. The use of silicon as a substrate allows direct fabrication of the CCD detector array and a thermally oxidized layer of SiO 2 forms an effective substrate for waveguide deposition. The detector array is composed of a two-phase overlapping-gate CCD with first-level polycrystalline silicon electrodes and second-level aluminum electrodes connected in parallel by means of a series of gates to an array of pbotodiodes. In the photodiode region the SiO 2 layer is tapered to a termination so that with minimal scatter, light is multiply refracted into the detector region. The center-to-center detector element spacing of the device fabricated and successfully operated is 32 μm. Optimum detector length is considered as a function of waveguide thickness. The integrated waveguide-CCD array is expected to become an integral part of various signal-processing devices.

Stepped Electrode Transistor: SET

Abstract: SET can achieve high performance without precise photolithography and metallization techniques. An arsenic doped polycrystalline silicon is used as a part of the emitter electrode in the SET structure. It is processed to have an inverse trapezoid shape. Procedure to make the inverse trapezoid shape uses a difference of etching rates between double layers of polycrystalline silicon. Base contact windows are opened through the ion-implantation process followed by chemical etching. The spacing between the emitter diffused layer and the base contact is as short as 0.4 µm or less. The cut off frequency of |S21e| is about 8.4 GHz. This frequency is higher than that of the conventional planar transistors with equal size emitter by 2 GHz. The rise time is 150 psec in the integrated SET.