Showing papers on "Polycrystalline silicon published in 1980"

Dopant segregation in polycrystalline silicon

Abstract: Dopant segregation at grain boundaries in polycrystalline silicon has been investigated. Arsenic, phosphorus, and boron were ion implanted into low‐pressure, chemically‐vapor‐deposited polycrystalline‐silicon films. All films were then annealed at 1000 °C for 1 h, and some were subsequently further annealed at 800, 850, or 900 °C for 64, 24, or 12 h, respectively. For phosphorus and arsenic the room‐temperature resistivity of the films was found to be higher after annealing at lower temperatures. By successively annealing the same sample at lower and higher temperatures, the resistivity would repeatedly increase and decrease, indicating reversible dopant segregation at the grain boundaries. Hall measurements were used to estimate the number of active dopant atoms within the grains and the number of atoms segregated at the grain boundaries as a function of annealing temperature. A theory of segregation in systems of small particles has been developed. Using this theory, the heat of segregation of arsenic and phosphorus in polycrystalline silicon was calculated. For boron no appreciable segregation was observed.

Theory of the electrical and photovoltaic properties of polycrystalline silicon

Abstract: Grain boundary states play a dominant role in determining the electrical and photovoltaic properties of polycrystalline silicon by acting as traps and recombination centers. The recombination loss at grain boundaries is the predominant loss mechanism in polycrystalline solar cells. Cell parameters are calculated based on a transformation of grain boundary recombination centers to a uniform distribution of such states throughout the grain. Effective carrier lifetime is expressed in terms of grain size, allowing calculation of short‐circuit current, open‐circuit voltage, and fill factor. Excellent agreement is observed between theory and experiment for almost all device parameters. It is indicated that one could fabricate 10% efficiency polycrystalline solar cells from 20‐μm‐thick material if the grain size exceeds 500 μm.

Hydrogenation of transistors fabricated in polycrystalline-silicon films

Abstract: Transistors have been fabricated with their active channels in thin films of polycrystalline silicon. A subsequent hydrogen plasma treatment has been used to improve the transistor properties significantly by reducing the number of electrically active grain-boundary defects. Plasma conditions to maximize the hydrogenation effect have been briefly investigated.

Thin film interaction between titanium and polycrystalline silicon

Abstract: The low resistivity of the titanium disilicide makes this material attractive for gate and interconnect metallizations. TiSi2 has been formed by reacting Ti films with polycrystalline and monocrystalline silicon in the temperature range 400–1100 °C. The interaction is investigated by use of sheet resistance, x‐ray diffraction, and stress measurements. It has been found that Ti and Si react very rapidly to form both TiSi and TiSi2 at temperatures ? 700 °C and only TiSi2 at temperatures ≳ 700 °C. The TiSi2 films are associated with a very low resistivity (∼15 μΩ cm), high tensile stress [∼ (1–2) ×1010 dyn/cm2)], and a rough surface. Silicided structures are mechanically stable. It is proposed that the silicon, as the predominant diffusing species, first diffuses into titanium to completely convert titanium into TiSi and then into TiSi to form TiSi2.

Silicon integrated circuits

Abstract: A dynamic random access memory in which individual cells, including an access transistor and a storage capacitor, are formed in mesas formed on a silicon chip. The access transistor of the cell is formed on the top surface of the mesa and one plate of the storage capacitor of the cell is formed by the sidewall of the mesa and the other plate by doped polycrystalline silicon which fills the grooves surrounding the mesas isolated therefrom by a silicon dioxide layer. By this geometry, large storage surfaces, and so large capacitances, can be obtained for the capacitor without using surface area of the chip. In other embodiments, the mesas may include other forms of circuit elements.

Silicide formation in thin cosputtered (tantalum + silicon) films on polycrystalline silicon and SiO2

Abstract: Formation of the silicides of titanium has been investigated by cosputtering titanium and silicon on polycrystalline silicon and oxidized silicon wafers. Alloys with as‐deposited Si/Ti atomic ratios of 0.5–8 were sintered in vacuum or hydrogen ambient in the temperature range 400–1000 °C. The Ti‐Si interaction in such films was studied by the use of sheet resistance, x‐ray diffraction, and stress measurements. It was found that in cases of silicon deficient alloys (e.g., the case of alloys sputtered on oxide with Si/Ti ratio <2) intermetallics Ti5Si3 and TiSi were formed. These intermetallics were stable up to 900 °C. In the presence of polycrystalline silicon and for alloys with Si/Ti ratio ?2, the only intermetallic formed was TiSi2. TiSi2 was responsible for very low resistivity (as low as ∼25 μΩcm) in the films. The volume change associated with silicide formation led to high tensile stresses in the films. It is suggested that in cosputtered films metallurgical interaction occurs locally which leads t...

Anisotropic plasma etching of polysilicon

Abstract: Plasma etching of polycrystalline silicon films for fabrication of silicon gate MOS integrated circuits has been studied with emphasis on fine‐line devices. CF4–O2 plasmas, commonly used for etching silicon, are unacceptable for very fine features because the etching is isotropic and load dependent. This results in substantial undercutting and insufficient dimensional control. Several alternative gases were investigated in a parallel–plate reactor. CF3Cl and a 70% CF3Br–30% He mixture were found to provide selectivities of 30:1 and 16:1, respectively, over thermal SiO2, freedom from loading effects and a large vertical to lateral etch rate anisotropy which minimizes undercutting. Extensive measurements of etch rate and edge profile as a function of gas composition were made for C2F6–Cl2 plasmas. Fully anisotropic etching (zero lateral etch rate) was observed at low Cl2 concentrations with a selectivity ≳6:1 over thermal SiO2 when using conventional photoresist masks. The vertical and lateral etch rates an...

Electrowinning of Silicon from K 2SiF6 ‐ Molten Fluoride Systems

Abstract: The electrowinning of silicon from solutions of in fluoride melts at 745°C has been achieved. Electrolysis close to the deposition potential gave dense, coherent, and well‐adherent deposits. Up to 3 mm thick films were grown using a concentration of 4–6 m/o. The polycrystalline silicon has a columnar structure with grain size up to 100 μm. The morphology of the electrodeposited silicon onto silver substrates and its dependence on the deposition parameters is discussed. The purity of the deposits is substantially higher than that previously reported for electrodeposited silicon.

Method of making high density semiconductor device such as floating gate electrically programmable ROM or the like

Abstract: An improved method of making a semiconductor device such as an N-channel, double level poly, MOS read only memory or ROM array is provided; the array is of very dense structure and may be electrically programmable by floating gates which are interposed between the gate oxide and control gates formed by polycrystalline silicon or metal row address lines. The electrical programming of the cells is accomplished by applying selected voltages to the source, drain, control gate and substrate. The very dense array results from a simplified manufacturing process generally compatible with standard N-channel silicon gate technology. Parallel strips of gate oxide, polycrystalline silicon, and nitride (functioning as an oxidation mask) are created in one mask step before field oxide is grown, then a perpendicular pattern of conductive strips is etched using a second mask step.

Polycrystalline silicon films deposited in a glow discharge at temperatures below 250 °C

Abstract: Raman scattering, x‐ray diffraction and electron diffraction results show that thin films of silicon (ranging in thickness from a few hundred A to 1 μm) prepared by chemical transport in low‐pressure hydrogen plasma at a temperature between 230 and 280 °C and a deposition rate of up to ∼0.5 A sec−1, are polycrystalline. X‐ray diffraction and transmission electron microscopic data indicate crystallite sizes amounting to a few hundred A.

A quantitative model of the effect of grain size on the resistivity of polycrystalline silicon resistors

Abstract: The effect of grain size on the resistivity of polycrystalline silicon films has been investigated theoretically and experimentally. It is shown that existing models do not accurately predict the resistivity dependence on doping concentration as grain size increases. A new modified trapping theory demonstrates from a good agreement with experimental results that a significant increase in grain size drastically reduces the sensitivity of polysilicon resistivity to doping concentration.

Plasma etching of silicon

Abstract: By utilizing a fluorine-containing gaseous compound in a plasma etching process, isotropic etching of monocrystalline silicon (48) and doped or undoped polycrystalline silicon (54) is achieved. The etching processes, which are applicable, for example, to pattern delineation in the processing of semiconductor wafers, are substantially free of any proximity effects and are characterized by a high etching rate at relatively low power levels, high selectivity (with respect to, for example, silicon dioxide) and excellent uniformity. By mixing other gases (for example, chlorine) with the fluorine-containing gas, the amount of undercutting achieved during the etching process can be selectively controlled.

Improvement of polycrystalline silicon solar cells with grain‐boundary hydrogenation techniques

Abstract: Electron‐beam‐induced‐current– and dark‐current–voltage measurements have been made on p/n photovoltaic cells fabricated from polycrystalline silicon. These data have demonstrated that grain‐boundary hydrogenation greatly reduces grain‐boundary minority carrier recombination and improves diode current‐voltage characteristics.

Silicon Oxidation Studies: Morphological Aspects of the Oxidation of Polycrystalline Silicon

Abstract: Previous studies have shown that the oxide grown from polycrystalline silicon displays degraded reliability in terms of higher leakage current and premature dielectric breakdown as compared with the oxide grown from single crystal silicon. Present transmission electron microscope studies of the morphology of polycrystalline silicon films and the oxide grown therefrom show several novel features. The polycrystalline silicon becomes rougher after oxidation, the oxide displays thickness undulations which replicate the previous grain boundaries with thinner oxide over grain boundaries, and the oxide forms intergranularly as well as on the free silicon surface. Despite the intergranular oxide formation, the film skin of oxidized polycrystalline silicon does not become significantly more compressive. The surface roughness features of the polycrystalline silicon and oxide and the film stress values are explained by a Si creep mechanism. From these studies some aspects of the reliability of polycrystalline silicon and oxide are understood.

Composite silicide gate electrodes&#8212;Interconnections for VLSI device technologies

Abstract: A potentially severe limit on density, performance, and wirability of polysilicon-gate technologies for VLSI applications, is the high resistivity of polycrystalline silicon. Composite structures of highly conductive molybdenum or tungsten disilicide on top of polysilicon (polycide) are shown to be a viable alternative gate electrode and interconnect level. Sheet resistance values of 1-3 Ω/□ for an integrated structure are easily attainable. IGFET devices fabricated to channel lengths of ≥ 1.4 µm show the polycide devices to be indistinguishable from normal polysilicon gate devices.

Forming air-dielectric isolation regions in a monocrystalline silicon substrate by differential oxidation of polysilicon

Abstract: Dielectric isolation regions are formed in a monocrystalline silicon substrate through forming trenches in the substrate by reactive ion etching after having etched openings in a layered structure of silicon dioxide and silicon nitride on the surface of the substrate. The walls of the trenches in the substrate are oxidized prior to depositing polycrystalline silicon on the substantially vertical side walls of the trenches in the substrate and on the substantially vertical walls defining the openings in the layered structure. By selectively doping the portion of the polycrystalline silicon on the substantially vertical walls of the openings in the layered structure so that the polycrystalline silicon on the substantially vertical walls of the openings in the layered structure will oxidize at least twice as fast as the polycrystalline silicon on the substantially vertical side walls of the trenches in the substrate, thermal oxidation causes the polycrystalline silicon to close the upper end of each of the trenches while leaving an air space therebeneath to form the dielectric isolation regions.

Energy distribution of trapping states in polycrystalline silicon

Abstract: The electronic density of states in the forbidden gap of polycrystalline silicon has been determined from an analysis of capacitance and conductance of a Metal/SiO2 (∼60 A)/polycrystalline silicon(∼250 A)/Si(111) (MOSS) structure. In this structure the thickness of the polycrystalline silicon is comparable to its grain size. Net density of trapped charges in the polycrystalline silicon is enough to terminate the electric field penetrating from the oxide layer. Then, two‐terminal admittance of the MOSS structure is dominated by charging or discharging of the trapping states in a wide range of applied gate bias. The U‐shaped distribution of trapping state density has been found for thin polycrystalline silicon films.

On the mobility of polycrystalline semiconductors

Abstract: A simple phenomenological model based on tunnel and thermionic emission across grain boundary barrier has been developed. The present model has been applied to polycrystalline silicon assuming that the dangling bonds at the grain boundaries behave as electron traps. The calculations have been carried out in two different ways; one, assuming that the interface states density, N is (cm −2 eV −1 ), is constant across the energy gap; and second with the boundary states, N T (cm −2 ), localized around a very narrow energy range at E T . In the first case no differences in the mobility reduction have been found between n and p type polysilicon, but for the assumption of states localized at an energy E T in the upper half of the gap , the barrier height is larger in n -type than in p -type material and consequently the calculated mobility of n -type polysilicon becomes lower than the p -type mobility. In general, the mobility increases with the dopant concentration approaching the monocrystalline behaviour for very large dopings, in qualitative agreement with other approaches and with available experiments.

Hall mobility of polycrystalline silicon

Abstract: Hall mobility of polycrystalline silicon was measured in the dark and under illuminated conditions. Grain boundary potential barriers present in the dark can be eliminated with light. When the barriers are removed, the mobility between 200 and 400 K is found to vary as T−2, which is the dependence observed in single crystals for the same order of magnitude of doping. The free‐carrier concentration of 5×1015 cm−3 was not affected by illumination, and the room temperature mobility in 1‐mm grain size material after barrier elimination with light was 900 cm2/V sec. A phenomological theory of Hall mobility in polycrystallllne silicon which explains these observations is presented.

Oxidation of tantalum disilicide on polycrystalline silicon

Abstract: Oxidation characteristics of the tantalum disilicide films have been investigated in the temperature range of 900°–1050 °C in dry oxygen and steam ambients. The silicide does not oxidize in dry oxygen and oxidizes in steam at a rate lower than that of doped polycrystalline silicon films as long as there is a polycrystalline silicon layer between the silicide and the gate oxide. Under these circumstances, the silicide retains its electrical and mechanical characteristics. The oxide on the silicide has an etch rate (in buffered hydrofluoric acid) similar to that of thermal SiO2 on silicon. Electrical characteristics of the oxide appear to be similar to those of the wet oxide on polycrystalline silicon. In the absence of polycrystalline silicon, between the silicide and the gate oxide, oxidation leads to a loss in the conductivity of the silicide and eventually to a mechanical instability of the film. An oxidation mechanism, which assumes silicon diffusion by substitution through the silicide, has been proposed.

Self-aligned metal process for integrated circuit metallization

Abstract: A self-aligned metal process is decribed which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming this structure involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body. The remaining polycrystalline silicon layer is then removed by etching to leave the narrow dimensioned regions on the major surface of the silicon body. A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between. The surface is planarized leaving the structure of metal filling the regions between the pattern of dielectric material.

The Nucleation of CVD Silicon on SiO2 and Si3 N 4 Substrates III . The System at Low Temperatures

Abstract: The growth of polycrystalline silicon layers on and substrates can be hampered in the early stages of growth by the presence of different species adsorbed on the surface In this article nucleation experiments with silicon on and are described in the system at temperatures between 600° and 900°C In this temperature regime (and without addition) the saturation nucleus density of silicon clusters on substrates shows a decrease in density with decreasing temperature, whereas on substrates the opposite occurs Experiments with nitrogen as a carrier gas, however, give almost the same saturation nucleus densities of silicon clusters on and substrates Additions of to the system produce a decrease in the nucleus saturation density on and substrates, and the density also decreases with decreasing temperatures below 900°C It is further shown that selective growth of silicon on partly coated silicon substrates becomes more difficult at lower growth temperatures Adsorption of different surface species (H, Cl, , and ) on and substrates is discussed and it is concluded that a strong adsorption of atomic hydrogen, notably on surfaces, may explain the difference in nucleus densities on and substrates at temperatures below 900°C

Self-aligned metal process for field effect transistor integrated circuits

Abstract: A process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistors. The insulation between the contacts and the metal is dielectric material having a thickness dimension about a micron or less. The structure is substantially planar. The method for forming this structure involves providing a silicon body and then forming a first insulating layer on the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the layer by reactive ion etching which results in the structure having horizontal surfaces and vertical surfaces. The openings can be in either the areas designated to be the gate regions or a PN junction region of the field effect transistors in the integrated circuit. A second insulating layer is then formed on both the horizontal surfaces and vertical surfaces. Reactive ion etching of this second insulating layer moves the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body. The gate dielectric is either formed hereat or PN junctions are fabricated by diffusion or ion implantation. The remaining polycrystalline layer is removed to leave the narrow regions on the major surface of the silicon body. A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between to make contact to source/drain PN regions and form the gate electrodes.

Single electrode U-MOSFET random access memory

Abstract: A method for making highly dense, dielectrically isolated, U-shaped MOSFET. In a preferred method a monocrystalline silicon P substrate with a N+ layer thereon, a P layer on the N+ layer and a N+ layer on the P layer is provided. A pattern of U-shaped openings is formed in the body through to the P substrate by the reactively ion etching technique. This pattern of openings is filled with an insulator material, such as silicon dioxide. A conductive layer of N+ doped polycrystalline silicon is deposited on the bare surface of this silicon body. Openings are formed in the polycrystalline silicon over the silicon dioxide filled openings. A silicon dioxide layer is then grown by, for example, thermal oxidation over the polycrystalline silicon layer. Reactively ion etching is used to produce substantially U-shaped openings through the layers over the P substrate and into the P substrate to substantially bisect the regions of monocrystalline silicon. This etching step forms two storage cells in the monocrystalline silicon areas and a bit line for each column of cells in the polycrystalline silicon layer. A silicon dioxide gate insulator is grown on the monocrystalline silicon surfaces of the U-shaped openings by thermal oxidation in a suitable ambient. Conductively doped polycrystalline silicon is deposited in the U-shaped openings over the silicon dioxide gate insulator layer until the openings are filled and cover the surface of the body. The conductively doped polycrystalline silicon on the surface of the body is etched in a suitable pattern to produce the word lines of the random access memory device.

Optical determination of mobility and carrier concentration in heavily doped polycrystalline silicon

Abstract: Optical absorption of phosphorus‐doped polycrystalline Si films observed at photon energies below the energy gap has been interpreted in terms of free‐carrier absorption, which obeys the Drude theory. As a result, we can simultaneously determine conductivity, electron mobility, and carrier concentration of heavily doped polycrystalline Si films from their optical transmission spectra alone. The new technique offers a contactless measurement of electrical properties for heavily doped polycrystalline Si thin films.

MOS Integrated circuit having refractory metal or metal silicide interconnect layer

Abstract: A partial silicide layer under a polycrystalline silicon (polysi) first level interconnect reduces the sheet resistance of the first level interconnect. The polysi insulates the silicide from possibly reactive materials and gases. Since the silicide is not deposited over contacts between the polysi and the substrate, conventional polysi/silicon ohmic contacts can be made.

Self aligned method for making bipolar transistor having minimum base to emitter contact spacing

Abstract: A method for making a high performance bipolar transistor characterized by self-aligned emitter and base regions and minimized base and emitter contact spacing. The disclosed method comprises forming a recessed oxide-isolated structure having opposite conductivity epitaxial layer and substrate. Multiple layered mass of alternating silicon nitride and silicon dioxide layers are placed over the base region and over the collector reach-through region. Polycrystalline silicon is deposited between the mesas. The mesas are undercut-etched to expose the extrinsic base region which is ion implanted. Then, the mesas are removed to expose the emitter and intrinsic base regions as well as the collector reach-through regions. The latter exposed regions are ion implanted appropriately. Contacts are made directly to the emitter and collector reach-through regions and indirectly via the polysilicon to the base region.

High speed lateral bipolar transistor

Abstract: A bipolar transistor NPN structure (20) is constructed at a major surface of a silicon body with a P-type polycrystalline silicon electrode (13) contacting a P-type base zone (13.6). Excess acceptor impurities from the polycrystalline silicon electrode (13) are diffused into the base zone (13.6) in order to tailor its conductivity profile.

Method of manufacturing a metal-insulator-semiconductor device utilizing a graded deposition of polycrystalline silicon

Abstract: A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The intrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing. The yield for the manufacture of devices having thin oxide gates is substantially improved.

Process of forming recessed dielectric regions in a monocrystalline silicon substrate

Abstract: A method of forming surface planarity to a substrate during removal of excess dielectric material when fabricating recessed regions of dielectric material in a semiconductor device wherein a dielectric layer is formed on the surface of the silicon substrate, a relatively thick layer of polycrystalline silicon deposited over the SiO2 layer, openings formed through the polycrystalline layer and SiO2 layer and into the substrate to form trenches, vapor depositing a layer of dielectric material over the surface of the substrate to a depth sufficient to fill the trench, depositing a planarized layer over a layer of dielectric material, reactive ion etching the planarizing layer, the dielectric layer, the polycrystalline layer, and selectively removing the remaining polycrystalline silicon layer to expose the SiO2 layer.