Showing papers on "Polycrystalline silicon published in 1983"
TL;DR: In this article, the dependences of maximum free standing length and beam deflection on the thickness of a polycrystalline silicon beam were investigated, and annealing the poly-Si prior to beam formation was improved.
Abstract: Using the conventional MOS planar process, miniature cantilever and doubly supported mechanical beams are fabricated from polycrystalline silicon. Poly‐Si micromechanical beams having thicknesses of 230 nm to 2.3 μm and separated by 550 nm to 3.5μm from the substrate are made in a wide range of lengths and widths. Two static mechanical properties are investigated: the dependences of maximum free‐standing length and beam deflection on the thickness of the beam. By annealing the poly‐Si prior to beam formation, both of these properties are improved. Nonuniform internal stress in the poly‐Si is apparently responsible for the beam deflection.
206 citations
TL;DR: In this paper, various absolute determinations of the thermal expansivity of both single crystal and polycrystalline silicon are used to establish a smooth relationship from 90 to 850 K which is believed to be reliable to roughly 10−8 K−1, and which is extrapolated to 1000 K.
Abstract: Silicon, a high melting point, low expansivity, cubic material which can be obtained readily in high purity form, provides an excellent thermal expansion standard. Various absolute determinations of the thermal expansivity of both single crystal and polycrystalline silicon are used to establish a smooth relationship from 90 to 850 K which is believed to be reliable to roughly 10−8 K−1, and which is extrapolated to 1000 K. Values also are suggested for temperatures to absolute zero. Key words: high temperature expansivity; silicon; standard expansivities; thermal expansivity.
188 citations
Patent•
15 Jun 1983
TL;DR: In this paper, a transistor is fabricated by depositing an unpatterned layer of silicon on an insulating layer over a surface of a semiconductor substrate, with the silicon layer being deposited in an amorphous state to improve its uniformity in thickness and smoothness.
Abstract: In the disclosed method, a transistor is fabricated by depositing an unpatterned layer of silicon on an insulating layer over a surface of a semiconductor substrate, with the silicon layer being deposited in an amorphous state to improve its uniformity in thickness and smoothness. Subsequently, while the silicon layer is still in the amorphous state, it is patterned by removing selected portions to form a gate. This patterning in the amorphous state improves the gates edge definition. Thereafter, the patterned amorphous silicon layer is heated to change it to polycrystalline silicon, thereby increasing its stability and conductivity.
181 citations
Patent•
12 Sep 1983
TL;DR: In this paper, a gate oxide film is formed on a solid-phase epitaxy silicon thin film formed on quartz substrate, and a polycrystalline silicon gate electrode 2-5 is formed by patterning.
Abstract: PURPOSE: To turn a gate electrode into salicide, and reduce gate line resistance, by forming a high melting point metal film on a polycrystalline silicon gate electrode, and annealing the film. CONSTITUTION: After a gate oxide film is formed on a solid-phase epitaxy silicon thin film formed on a quartz substrate, a polycrystalline silicon film is deposited, and a polycrystalline silicon gate electrode 2-5 is formed by patterning. Impurities are ion-implanted, and a source region 3-6 and a drain region 3-7 are formed in a self-alignment manner. A high melting point metal film 3-9 is formed. The polycrystalline silicon gate electrode 2-5 is turned into salicide by annealing, and a salicide layer 3-10 is formed. By selectively eliminating the high melting point metal, a salicide gate electrode 3-12 is formed. After a contact hole is formed in an interlayer insulating film 3-13, a source electrode and a drain electrode are formed, and a thin film transistor whose gate line resistance is small is formed. COPYRIGHT: (C)1995,JPO
115 citations
TL;DR: In this paper, the authors measured compressive stresses in polycrystalline and amorphous silicon thin films deposited on oxidized silicon wafers by the lengthening of the undercut edge of a silicon stripe.
Abstract: Stress in polycrystalline and amorphous silicon thin films deposited on oxidized silicon wafers is determined from the lengthening of the undercut edge of a silicon stripe. The technique measures only compressive stresses, has a stress resolution of 108 dyn/cm2, and a spatial resolution on the wafer of 250 μm. Unannealed silicon thin films deposited on oxide are under high compressive stress (1010 dyn/cm2). This stress is reduced below the resolution by annealing at 1100 °C for 20 min in N2, except for the thinnest polycrystalline silicon films studied (230 nm thick).
111 citations
TL;DR: In this paper, low-pressure chemical vapor deposition of tungsten silicide has been done and the properties of the deposited films have been studied to determine the process compatibility and suitability to form gate electrodes and interconnections in MOS VLSI applications.
Abstract: Low-pressure chemical vapor deposition of tungsten silicide has been done and the properties of the deposited films have been studied to determine the process compatibility and suitability to form gate electrodes and interconnections in MOS VLSI applications. The silicide was deposited on single-crystal silicon and on oxidized silicon with and without a coating of polycrystalline silicon film. Auger analysis of the As-deposited films showed absence of any contaminants in it. X-ray diffraction and transmission electron microscopy showed that As-deposited films were microcrystalline with grains smaller than 30 A and upon annealing became polycrystalline WSi 2 with hexagonal structure at 500°C and tetragonal structure at or above 600°C with a corresponding decrease in resistivity from 600-900 µΩ . cm to 35-60 µΩ . cm depending upon anneal temperature and time. No appreciable change in the thickness of the silicide was found during the high-temperature anneals. Silicon-rich silicide films remained stable, smooth, and free of cracks through high-temperature anneals and oxidations, and their adherence to the wafer remained excellent. On the other hand, metal-rich films had overall inferior properties. Thermal oxidation of WSi 2 on polysilicon in dry oxygen in the temperature range of 900 to 1100°C was found to be similar to that of silicon except the linear regime of oxidation was extremely rapid and the entire process could be modeled by a parabolic equation X^{2) = Bt with an activation energy of 1.7 eV. MOS capacitors were fabricated with silicide and polycide gate electrodes. Polysilicon thickness variation from 0 to 5000 A had no adverse effect on the electrical characteristics or mechanical integrity of the devices. In all cases, low values of N f (1 × 1010-7 × 1010cm-2) and N it ( \sime 8 MV/cm) were obtained.
108 citations
TL;DR: In this article, a new type of amorphous silicon (a-Si) solar cell stacked with polycrystalline silicon (poly-c-Si), has been developed, and the conversion efficiency more than 12% has been obtained with a cell structure of ITO/n-i-p a-Si/p poly c-Si//Al.
Abstract: A new type of amorphous silicon (a-Si) solar cell stacked with polycrystalline silicon (poly-c-Si) has been developed. The conversion efficiency more than 12% has been obtained with a cell structure of ITO//n-i-p a-Si//n a-Si/p poly c-Si//Al. A series of technical data on the cell fabrication and resulting photovoltaic characteristics are presented.
98 citations
Patent•
IBM1
TL;DR: In this article, a process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal to metal spacing for field effect transistor integrated circuits.
Abstract: A process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits The method for forming integrated circuits with this structure includes forming openings in a first polycrystalline silicon layer overlying an insulator by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces The openings are in those areas designated to be the gate regions of the field effect transistors A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body The gate dielectric is formed hereat A second polycrystalline silicon gate electrode is formed over the gate dielectric and between certain of said narrow dimensioned regions The remaining first polycrystalline silicon layer is then removed by etching to leave the narrow dimensioned regions on the major surface of the silicon body A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between to make contact to source/drain PN regions A blanket layer of a plastic material is used to planarize the surface by reactive ion etching the plastic material and the conductive layer until the tops of the narrow dimensioned regions are reached The plastic material is then removed leaving the structure of patterns of metal or polycrystalline silicon filling the regions between the pattern of dielectric material having a thickness dimension in the order of a micron or less The source and drain electrodes are thusly formed
80 citations
TL;DR: In this paper, the authors investigated the polysilicon stress properties as a function of film thicknesses and phosphorus doping and found that asdeposited films are moderately compressive, and become less compressive with increasing film thickness.
Abstract: An investigation of the polysilicon stress properties as a function of film thicknesses and phosphorus doping showed that as‐deposited films are moderately compressive, and become less compressive with increasing film thickness. High temperature PBr3 diffusion in silicon produces wafer bending corresponding to a tensile stress in wafer. Following a PBr3 diffusion, polysilicon films, however, become less compressive. Subsequent oxidation introduces an additional compressive stress component of the order of 2−3×109 dyne/cm2 for oxidation temperatures between ∼900−1000 °C. The thermal expansion coefficients were similar for doped and undoped films (α∼2.9 ppm/°C) and slightly less than for 〈100〉 silicon, while the doped films were found to be less stiff than undoped ones but both were less stiff than 〈100〉 silicon. The observed changes in polysilicon stress due to film thickness and phosphorus doping have been interpreted in terms of a grain growth model wherein those factors which lead to enhanced grain grow...
79 citations
Patent•
28 Mar 1983TL;DR: In this paper, an optical reflectance method for rapid and simultaneous determination of surface roughness and structure of silicon films deposited by chemical vapor deposition is described, where the magnitude of the reflectance of polycrystalline silicon films at a wavelength of about 280 nm can be used directly as a quantitative measure of film surface roughs.
Abstract: This disclosure describes an optical reflectance method for rapid and simultaneous determination of surface roughness and structure of silicon films deposited by chemical vapor deposition. The magnitude of the reflectance of polycrystalline silicon films at a wavelength of about 280 nm can be used directly as a quantitative measure of film surface roughness. The magnitude of the reflectance of as-deposited amorphous or mixed amorphous-polycrystalline silicon films at a wavelength of about 400 nm can be used as a measure of the combined surface roughness and amorphism of the films. Other materials such as metals, alloys and silicides used in semiconductor technology may be evaluated with respect to surface roughness in a similar manner.
72 citations
Patent•
12 Aug 1983TL;DR: In this article, a CMOS integrated circuit made up of complementary insulated gate field effect transistors incorporates isolation trenches formed by a combination of thermal growth of silicon dioxide and chemical vapor deposition of polycrystalline silicon to prevent air gaps.
Abstract: A CMOS integrated circuit made up of complementary insulated gate field effect transistors incorporates isolation trenches formed by a combination of thermal growth of silicon dioxide and chemical vapor deposition of polycrystalline silicon to prevent air gaps. Matching of the thermal coefficient of expansion of the trench with that of the substrate minimizes pn junction leakage currents as well as positive feedback latch-up operation. To reduce the ohmic contact resistance and interconnect resistance of the transistor elements, refractory metal silicide areas of low sheet resistance are contacted with the source, drain and gate elements. The process of manufacture also employs vertical walls of silicon nitride to prevent the formation of "birds' beak" portions of increased thickness in the silicon dioxide layer of each transistor, which could degrade the high frequency performance of the device.
Patent•
28 Jan 1983
TL;DR: In this article, a method for fabricating an MOS memory array is disclosed, wherein the method includes steps for constructing electricallyprogrammable and electrically-erasable memory cells (2, 198, 200) in combination with assorted peripheral devices (202, 204, 206) on a semiconductor substrate (8, 71).
Abstract: A method for fabricating an MOS memory array is disclosed, wherein the method includes steps for constructing electrically-programmable and electrically-erasable memory cells (2, 198, 200) in combination with assorted peripheral devices (202, 204, 206) on a semiconductor substrate (8, 71). Tunneling regions (20, 78) are formed in the substrate (8, 71) and thin tunnel dielectrics (22, 84) comprised of silicon dioxide/oxynitride material are grown over the tunneling regions (20, 78) to facilitate transport of charge carriers between the tunneling regions (20, 78) and subsequently-fashioned floating gate structures (14R, 14L, 156) in the memory cells (2, 198, 200). A first layer of doped polycrystalline silicon is then deposited over the substrate and etched to define large polysilicon areas. An oxide layer is grown over the large polysilicon areas in a manner such that out-diffusion of the impurity present in the large polysilicon areas is prevented. Thereafter, a second layer of doped polycrystalline silicon is deposited over the substrate and etched together with the large polysilicon areas to define the memory cell floating gate structures (14 R, 14L, 156) as well as various memory cell program and control gates (16R, 16L, 40R, 40L, 128, 132) and peripheral device control gates (136, 138). Source and drain regions (34, 36, 58, 60, 64, 66, 168-179) for the memory cells (2, 198, 200) and the peripheral devices (202, 204, 206) are established by implanting an impurity in the semiconductor substrate (8, 71), using the memory cell program and control gates (16R, 16L, 40R, 40L, 128, 132) and the peripheral device control gates (136, 138) for alignment. Protective coverings of refill oxide (188) and VapOx (190) are formed over the substrate to complete the fabrication process.
Patent•
11 Apr 1983
TL;DR: In this paper, a thin-film MOS transistor was used in active matrix liquid crystal display devices with a plurality of picture elements arranged in a matrix, each picture element having a thin film MOS transistor as a switching element.
Abstract: A thin film MOS transistor includes a silicon layer (202) whose thickness, at least in the channel region is less than 2500 ANGSTROM . The silicon layer may be a polycrystalline silicon layer and its thickness in the channel region may be less than its thickness in the source and drain regions. Such thin film MOS transistors may be used in active matrix liquid crystal display devices having a plurality of picture elements arranged in a matrix, each picture element having a thin film MOS transistor as a switching element.
Patent•
IBM1
TL;DR: In this paper, a method for making a dielectric isolation pattern in integrated circuit structure is described, where the layers are patterned to form openings in the structure at the areas where it is desired to form an oxide isolation pattern within the monocrystalline silicon body.
Abstract: A method for making a dielectric isolation pattern in integrated circuit structure is described. A monocrystalline silicon body (10, 20) is provided. There is formed thereon a layered structure (22, 24, 26) of silicon dioxide, polycrystalline silicon and silicon nitride, in that order. The layers are patterned to form openings in the structure at the areas where it is desired to form an oxide isolation pattern within the monocrystalline silicon body. If it is desired to form a semi-recessed oxide isolation there will be no etching of the monocrystalline silicon body in the openings. Should it be desired to form a full recessed oxide isolation there is etching of the monocrystalline silicon to a desired depth to form a substantially planar top surface of the monocrystalline with the recessed dielectric oxide isolation. The body is then oxidized until the desired oxide isolation pattern penetrates to the desired depth within the silicon body. Through a reduced silicon oxide layer (22) and by adding the polycrystalline silicon layer (24) a substantially reduced lateral oxidation and thus smaller beak length is achieved allowing higher integration density.
TL;DR: In this paper, a 2D investigation of the band curvature near a grain boundary has been carried out on transistors made in laser recrystallized polycrystalline silicon.
Abstract: Measurements have been carried out on transistors made in laser recrystallized polycrystalline silicon. In these devices, grain size is comparable to channel dimensions. A 2-D investigation of the band curvature near a grain boundary has made it possible to model transistor characteristics. Good agreement has been found between theory and experiments.
Patent•
13 Oct 1983TL;DR: In this article, the authors describe a method for the synthesis of high-purity polycrystalline silicon and hydrogen from metallurgical silicon at high pressure at a pressure of more than 6.9 bar, and particularly between 20.7 and 41.4 bar.
Abstract: Silicon tetrachloride, hydrogen and metallurgical silicon are reacted at about 400 to 600 DEG C at a pressure of more than 6.9 bar, and particularly between 20.7 and 41.4 bar, with the formation of di- and tri-chlorosiloanes. The latter are disproportionated in the presence of an anion exchanger with the formation of high-purity silane. Byproducts and unreacted material are recycled, while practically only silicon and hydrogen are consumed. Silane is further purified by means of activated carbon or by cryodistillation, and finally decomposed in a fluidised bed or in a free space to form high-purity polycrystalline silicon and hydrogen as byproduct, which is recycled. The method is simplified with respect to process products to be removed and permits an improvement in the overall reaction of metallurgical silicon to form silane and high-purity silicon which can be used for solar cells and semiconductors.
TL;DR: In this article, the 1/f noise in polycrystalline silicon resistors has been measured at room temperature at low doping levels and it decreased with increasing doping concentration, more or less as (μ/μlattice)2.
Abstract: The 1/f noise in polycrystalline silicon resistors has been measured at room temperature. The resistors were manufactured in low‐pressure chemical vapor deposition films, implanted with B, P, and As and processed in two different technologies with different temperature cycles. The spectral density was essentially independent of the type of implantation and of the processing. The results can be described with Hooge’s empirical law and Kleinpenning’s model for the 1/f noise in Schottky barriers. At low doping levels Hooge’s constant turned out to be ∼4×10−3 and it decreased with increasing doping concentration, more or less as (μ/μlattice)2.
TL;DR: In this article, it was shown that chemically grown interfacial oxide layers of about 1.4nm thickness provide more effective diffusion sources than oxygen-free interfaces, which is caused by the strong correlation between the crystalline structure of the polysilicon layer and the diffusion rates of dopant species in that layer.
Abstract: Boron and arsenic concentration profiles, diffused from polycrystalline silicon (polysilicon) into the underlying‐single crystalline silicon (mono) substrate, were analyzed by Rutherford backscattering spectrometry and secondary ion mass spectrometry for various levels of oxygen concentration at the poly/mono interface. In contrast with previous reports it was found that chemically grown interfacial oxide layers of about 1.4‐nm thickness provide more effective diffusion sources than oxygen‐free interfaces. This surprising phenomenon is caused by the strong correlation between the crystalline structure of the polysilicon layer and the diffusion rates of dopant species in that layer. It is shown that the small amount of oxide at the poly/mono interface prevents the epitaxial realignment of the polysilicon, thereby maintaining high diffusion rates in the polysilicon, without offering a significant barrier to the diffusion of boron and arsenic across the interface.
TL;DR: In this article, it was shown that hydrogen loss in silicon nitride is unimpeded by polycrystalline silicon gate layers, and it was inferred that Si-H and N-H bonds do not reconstruct when hydrogen is lost during high temperature processing.
TL;DR: The formation of titanium silicide from polycrystalline silicon and metallic titanium was studied in the temperature range 500-900°C as mentioned in this paper, and it was shown that only TiSi2 is obtained in these cases.
TL;DR: In this article, a directional acoustic microscope is described that has enhanced contrast for elastically anisotropic materials, which can detect surface acoustic waves by the acoustic lens on (100 and 111) silicon crystals.
Abstract: A directional acoustic microscope is described that has enhanced contrast for elastically anisotropic materials. Directional detection of surface acoustic waves by the acoustic lens is demonstrated on (100) and (111) silicon crystals. The grains of a polycrystalline silicon sample have contrast which varies as a function of lens orientation. Symmetry of contrast variations and measurement of surface wave phase velocity may provide a new way to determine the orientation of microscopic grains.
01 Jan 1983
TL;DR: The use of chlorinated oxides and Intrinsic gettering techniques for VLSI processing is discussed in this article. But the simulation of impurity redistribution near mask edges is not considered in this paper.
Abstract: Diffusion in Silicon.- Thermal Oxidation: Kinetics, Charges, Physical Models, and Interaction with Other Processes in VLSI Devices.- The Use of Chlorinated Oxides and Intrinsic Gettering Techniques for VLSI Processing.- Ion Implantation.- Beam Annealing of Ion Implanted Silicon.- Materials Characterization.- Modeling of Polycrystalline Silicon Structures for Integrated Circuit Fabrication Processes.- Two-Dimensional Process Simulation - Supra.- Numerical Simulation of Impurity Redistribution Near Mask Edges.- Optical and Deep UV Lithography.- Wafer Topography Simulation.- Analyses of Nonplanar Devices.- Two Dimensional MOS-Transistor Modeling.- Fielday - Finite Element Device Analyses.
Abstract: Halogen lamps have been used to recrystallize polycrystalline silicon deposited on SiO2. 〈100〉 single crystals have been obtained. 100–200 μm wide subgrains are present in the recrystallized films. We present the results of a structural analysis of the defects by using essentially Transmission Electron Microscopy. We can classify the defects as follows: primary subgrain boundaries are misfit dislocations resulting from a low angle misorientation between adjacent growing regions. Secondary subgrain boundaries are related to the strain present in the films during the recrystallization. We find coherent and incoherent precipitates. Precipitates result from a segregation of impurities. Some of them are revealed as α‐SiC.
TL;DR: In this paper, the influence of grain boundaries on the elctrical properties of laser-recrystallized polycrystalline silicon films with typical grain size 1 × 20 μm2 and doping concentration between 1016 cm−3 and 1020 cm −3 has been investigated.
Patent•
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TL;DR: In this paper, a bipolar memory cell is fabricated by forming diodes 60 and 65 on top of the transistors Q1 and Q2 formed in the underlying substrate 10.
Abstract: A bipolar memory cell is fabricated by forming diodes 60 and 65 on top of the transistors Q1 and Q2 formed in the underlying substrate 10. Metal silicide 30 overlies strips 34 and 35 of doped polycrystalline silicon 25, 28, 37, and 38 to cross-couple the bases and collectors of the two transistors 01 and 02 forming the memory cell. The metal silicide 30 shorts PN junctions 29 in polycrystalline 23. Two further strips 50 and 52, each comprising a sandwich of P type polycrystalline silicon 42, metal silicide 45, and N conductivity type polycrystalline silicon 47, are formed to couple the cross-coupled bases and collectors to respective diodes 60 and 65. The diodes 60 and 65 are formed by depositing metal 62 and 64 in electrical contact with the underlying N type polycrystalline silicon 47.
TL;DR: In this article, the three-dimensional diffusion equation of the minority carrier with grain boundary effects has been solved for the first time using the Green's function method, which points out correctly the limiting factors of the solar cell.
TL;DR: In this article, the characteristics of polycrystalline silicon-on-metal strain gauge transducers are reported and a model relating the poly-crystal silicon gauge factor and its temperature dependence to that of singlecrystal Si strain gauges is developed and shown to adequately describe transducer properties.
Abstract: The characteristics of polycrystalline silicon-on-metal strain gauge transducers are reported. This strain gauge material is stable, rugged, operates over a wide temperature range, and has a gauge factor intermediate between that of single-crystal Si, having the same carrier concentration, and that of metal wires and thin films. A model relating the polycrystalline silicon gauge factor and its temperature dependence to that of single-crystal Si strain gauges is developed and shown to adequately describe transducer properties.
TL;DR: In this article, the crystallinity of polycrystalline silicon layers was examined by a Raman microprobe in combination with polarization measurements and it was found that at high power levels the tensile stress in the annealed layer is relaxed to a certain extent, though the weak residual strain still remains.
Abstract: Implantation‐amorphized polycrystalline silicon layers which are directly deposited on single‐crystal Si are annealed by a scanning cw laser. The crystallinity of the annealed layers has been examined by a Raman microprobe in combination with polarization measurements. The Raman spectra measured for the specimens annealed at various power levels reveal that the polysilicon layer is regrown liquid epitaxially and is transformed into single crystal at high annealing power levels and that the regrowth at lower power levels is governed by the mixture of solid and liquid epitaxial processes. It is found that for specimens annealed at high power levels the tensile stress in the annealed layer is relaxed to a certain extent, though the weak residual strain still remains. The Raman microprobe spectra from the boundary reigon between the annealed and amorphous layers are recorded by making the probe laser beam traverse the boundary region. This technique enables us to investigate the variation in crystallinity and...
01 Jan 1983
TL;DR: In this paper, microscopie electronique en transmission and a balayage, diffusion Raman, diffusion optique, reflexion et absorption optique. And the taille des grains, de la cristalline, des deformations, de l'indice de refraction, de the rugosite de surface and de la conductivite electrique
Abstract: Etude par diffraction RX, microscopie electronique en transmission et a balayage, diffusion Raman, diffusion optique, reflexion et absorption optique. Determination de la taille des grains, de la perfection cristalline, des deformations, de l'indice de refraction, de la rugosite de surface et de la conductivite electrique
TL;DR: In this paper, the effects of grain size and doping concentration on the resistivity of polycrystalline silicon are investigated and a new relation is presented for the resistivities of large-grain polycrystaline material.