Showing papers on "Polycrystalline silicon published in 1984"

Growth and Physical Properties of LPCVD Polycrystalline Silicon Films

Abstract: Undoped LPCVD silicon films have been deposited at five temperatures between 560° and 620°C. The films were characterized as grown and after thermal annealing at 900°, 950°, and 1000°C. We used x‐ray diffraction, TEM, SEM, Raman and elastic light scattering, optical absorption and reflection, and other techniques in order to obtain information on the grain size, structure, structural perfection, and surface roughness. We found that polysilicon films of good structural perfection, low strain, and small surface roughness are obtained when the films are deposited in the amorphous phase and subsequently crystallized at 900°–1000°C. Such films are superior in all investigated material aspects to films grown in the crystalline phase.

A New Defect Etch for Polycrystalline Silicon

Abstract: Presentation d'une methode d'attaque isotrope pour la detection de defauts dans le silicium polycristallin. Application a un ruban de silicium polycristallin prepare par le procede RTR de Motorola

Method of manufacturing semiconductor device having polycrystalline silicon layer with metal silicide film

Abstract: A metal silicide film is formed on the sides of a polycrystalline silicon layer formed on a semiconductor substrate via an insulating film and the surface of the metal silicide film is covered by a silicon oxide film, whereby the silicon layer has a low electrical resistance and no short-circuiting is necessary. For example, in an insulated gate field effect transistor, the gate electrode is constituted by the polycrystalline silicon layer and the metal silicide film at the side walls of the polycrystalline silicon layer. Such a gate electrode has a low electrical resistance and does not cause undesirable short-circuiting with source and drain regions by the existence of the silicon oxide film formed on the surface of the metal silicide film. Also, other metal silicide film may be formed on the upper surface of the gate electrode. Moreover the silicide-SiO 2 structure may be used on the source and drain regions.

Phosphorus‐Doped Polycrystalline Silicon via LPCVD I . Process Characterization

Abstract: We have studied the low pressure chemical vapor deposition (LPCVD) process as applied to the preparation of in situ phosphorus‐doped polycrystalline silicon films. Thickness profiling, electron microprobe, and mass spectrometry have been utilized in the characterization of this process. The addition of phosphine as the dopant bearing precursor molecule was found to result in a factor of 25 decay in film growth rates relative to the intrinsic LPCVD process. The physical and chemical characteristics of samples prepared in this manner are shown to be a strong function of local reactor geometry, with growth‐rate variations of a factor of two within a wafer commonly observed. Mass spectrometry data is presented supporting the proposal that phosphine passivates the silicon surface, and the implications of this phenomenon for altering silicon growth kinetics are discussed. A model is presented accounting for the growth‐rate variations observed within individual wafers, as well as for the sensitivity of the phosphine‐doped process to system geometry.

Study of the atomic models of three donorlike defects in silicon metal‐oxide‐semiconductor structures from their gate material and process dependencies

Abstract: The atomic models of the generation and annealing of three donorlike defects [the bulk compensating donor, the donorlike interface density‐of‐state (DOS) peak, and the positive turn‐around charge] in silicon metal‐oxide‐semiconductor capacitors (MOSC) are investigated by studying their dependencies on the gate materials and process conditions. Starting thermal oxides used in this study include 1000 C dry oxides on 〈100〉 p‐Si substrates and 750 C high‐pressure steam oxides on 〈111〉 p‐Si substrates. Gate materials include aluminum, gold, and LPCVD (low‐pressure chemical‐vapor‐deposition) polycrystalline silicon (poly‐Si) with several doping methods. The densities of these donors generated during avalanche electron injection in MOSC’s with boron in situ doped LPCVD poly‐Si gates are smaller compared with those with aluminum gates. High temperature (>900 C) processes (diffusion or anneal) in dry inert gas after the poly‐Si gate deposition inhibit the generation of all three donors. After the inhibition, the d...

A comprehensive analytical and numerical model of polysilicon emitter contacts in bipolar transistors

Abstract: A comprehensive model-both analytical and numerical-is proposed as a tool to analyze heavily doped emitters of transistors with polycrystalline silicon (polysilicon) contacts. The grains and grain boundaries of polysilicon, the interfacial oxide-like layer between polycrystalline and monocrystalline silicon are lumped respectively into "boxes" in which the drift minority current component is neglected. The mobility reduction of carriers in polysilicon on the whole is explicitly attributed to the additional scattering due to the lattice disorder in the grain boundaries and the carrier tunneling through the interface. The effect of the poly-contacts on transistors can be modeled as a reduced surface recombination velocity for minority carriers in combination with a series emitter resistance for majority carriers. Furthermore, by characterizing the monocrystalline emitter with an effective recombination velocity, the effect of the polysilicon layer on the current gain can be analyzed analytically. Computer simulation is used to verify the assumptions of the model formulation. Using published data [1], the analytical and numerical approaches are compared and it is shown that for these devices a unique combination of physical parameters are needed for the model to fit the data.

Theory of conduction in polysilicon: Drift-diffusion approach in crystalline-amorphous-crystalline semiconductor system—Part I: Small signal theory

Abstract: A theory of conduction in polycrystalline silicon is presented. The present approach fundamentally differs from previous theories in its treatment of the grain boundary. This theory regards the grain boundary as amorphous semiconductor in equilibrium contact with crystalline grain. The model explains the electrical properties of polysilicon in terms of the electronic and structural parameters of the material and is in excellent agreement with the experimental data. The formulation is applicable for arbitrary grain size, temperature, doping concentration, and applied voltage. Specifically, the temperature dependence of resistivity is explained in terms of conduction channels inherent in the amorphous grain boundary. Also, this paper explicitly compares the previous emission theories with the present model in terms of voltage partition scheme and I - V predictions.

Phosphorus‐Doped Polycrystalline Silicon via LPCVD II . Surface Interactions of the Silane/Phosphine/Silicon System

Abstract: Secondary ion mass spectrometry (SIMS), low energy electron diffraction (LEED), and Auger electron spectroscopy (AES) have been employed to study the interactions of silane and phosphine with the Si(100) surface. Phosphine adsorption and desorption were investigated at surface temperatures in the range . At ambient temperature, phosphine saturated the bare Si(100) surface after 3–5L exposure, and fitting adsorption data to a Langmuir model yields the value for the sticking coefficient. Phosphine adsorption was found to follow the pattern of the underlying silicon. Competitive adsorption experiments set an upper bound of for silane adsorption under like conditions. The silicon surface was observed to be passivated with respect to silane adsorption by prior exposure to phosphine, with a layer of preferentially adsorbed phosphine formed which served to preclude subsequent silane adsorption. The results obtained here are discussed in the context of their bearing upon the phosphorus‐doped low pressure chemical vapor deposition process.

Effects of implantation temperature on the properties of buried oxide layers in silicon formed by oxygen ion implantation

Abstract: The effects of implantation temperature (Ti) on the chemical and physical structure of annealed high‐dose oxygen ion implanted layers were investigated by Auger electron spectroscopy (AES) and transmission electron microscopy (TEM). At low Ti (∼400 °C) the buried oxide is bordered by layers of polycrystalline silicon (polysilicon) which, in the top silicon layer, is separated from damaged single crystal Si by a thin band of discontinuous oxide. These polysilicon layers are formed from amorphous regions during high‐temperature anneals. At high Ti (∼500 °C) polysilicon was not observed.

Influence of as‐deposited film structure on 〈100〉 texture in laser‐recrystallized silicon on fused quartz

Abstract: A strong 〈100〉 texture has been achieved in cw neodymium:yttrium aluminum garnet laser recrystallization of the 700 °C low pressure chemical vapor deposited (LPCVD) polycrystalline silicon films which exhibit 〈100〉 preferred orientation. When 〈110〉 texture is dominant in as‐deposited films, the 〈100〉 texture is not so strong as in the 700 °C LPCVD films. The dependence of the 〈100〉 texture on as‐deposited film structure implies that the 〈100〉 grain growth occurs under such a melting condition as the initial film structure is partially maintained.

The poly‐single crystalline silicon interface

Abstract: Cross sectional transmission electron microscopy (TEM) reveals an amorphous interfacial region of the order of 2 nm thick between chemical vapor deposition‐(CVD) deposited polycrystalline silicon films and the single‐crystal silicon substrate. The continuity of this region varies from sample to sample and plays an important role in the effects produced by subsequent heat treatment. In cases where this interfacial layer is continuous, the deposited layer remains polycrystalline. When the region is discontinuous, complete epitaxial realignment of the poly is possible. The speed of realignment depends on the implanted arsenic dose and is much greater than reported for undoped films. Various impurities are also observed at the interface and correlate with the character of the interface.

Control of lateral epitaxial chemical vapor deposition of silicon over insulators

Abstract: Single‐crystal silicon films have been grown over SiO2‐covered regions of a single‐crystal silicon wafer by lateral epitaxial chemical vapor deposition (CVD). Nucleation of polycrystalline silicon on the SiO2 is suppressed by adding HCl to the SiH4 deposition gas. Sequential variation of the HCl partial pressure during different stages of the deposition process controls the relative deposition rates of the [100] and [110] planes and, consequently, the shape of the laterally advancing growth fronts, allowing the fronts from opposite sides of the SiO2 region to join uniformly. A plane surface is obtained by increasing the HCl partial pressure after coalescence. A standard silicon CVD epitaxial reactor is used for the deposition.

Process for manufacturing an integrated circuit with tantalum silicide connections utilizing self-aligned oxidation

Abstract: The invention concerns an integrated circuit the monocrystalline or polycrystalline silicon zones of which the source, gate and drain are covered with tantalum silicide TaSi 2 while the remainder of the slice is covered with portions of a layer of tantalum oxide Ta 2 O 5 , especially on the sides of the grids of polycrystalline silicon and on the thick oxide and an aluminum alloy layer comes into contact with the tantalum silicide to form connections with the portions of tantalum silicide.

On the effect of impurities on the photovoltaic behavior of solar grade silicon - II. Influence of titanium, vanadium, chromium, iron, and zirconium on photovoltaic behavior of polycrystalline solar cells

Abstract: Structural, electrical, and photovoltaic properties of single impurity doped polycrystalline silicon were investigated in order to forecast the behavior of more complicated impurity matrixes, like those deriving from upgrading MG silicon. To this purpose, silicon was doped with increasing amounts of titanium, vanadium, chromium, iron, and zirconium, and the diffusion length of minority carriers was measured as a function of the impurity concentration and microstructural features like grain boundaries (GB), dislocations, twins, and stacking faults. Results are displayed in three‐dimensional diagrams which permit observations on the dependence of simultaneously with the impurity concentration and with the total density of electrically active structural defects.

Enhanced conduction and minimized charge trapping in electrically alterable read‐only memories using off‐stoichiometric silicon dioxide films

Abstract: An electrically alterable read‐only memory using silicon dioxide and silicon‐rich silicon dioxide layers capable of being cycled ≳107 times by minimizing electron charge trapping in the SiO2 layers of the device by incorporation of small amounts of silicon is discussed in detail. Charge transfer to and from a floating polycrystalline silicon layer from a control gate electrode is accomplished by means of a modified dual‐electron‐injector‐structure stack. This modified stack has the intervening silicon dioxide layer, which is sandwiched between silicon‐rich silicon dioxide injectors, replaced by a slightly off‐stoichiometric oxide containing between 1 and 6% excess atomic silicon above the normal 33% found in silicon dioxide. The operation of the electrically alterable device structures in terms of write/erase voltages, cyclability, breakdown, and retention is related to current‐voltage characteristics obtained from capacitors. A physical model based on direct tunneling between Si islands in the off‐stoichiometric oxide layer is proposed to account for the observed increase in the moderate electric field conductance and decrease in charge trapping in these oxide layers incorporated into devices and capacitors. This model and the observed current‐voltage characteristics are used to predict device operation for a variety of conditions.

Low resistance polycrystalline silicon by boron or arsenic implantation and thermal crystallization of amorphously deposited films

Abstract: Polycrystalline silicon films with high surface smoothness, good step coverage, and a relatively large grain size of ∼0.3 μm have been prepared by low‐pressure chemical vapor deposition in the amorphous state and subsequent crystallization in a furnace. The final grain size achieved does not significantly depend on the initial annealing temperature used to crystallize the layer. For heavily boron implanted films, a clear correlation between sheet resistance and average grain size is found and the resistivity is close to the single crystal value for the amorphously deposited films. In contrast, only a minor resistivity reduction relative to standard polycrystalline silicon could be achieved by amorphous deposition for arsenic implanted films.

Sensor with polycrystalline silicon resistors

Abstract: Sensor with polycrystalline silicon resistors which are applied to a substrate and are covered with a dielectric passivating layer, characterized by the feature that the resistors are thermally adapted by targeted adjustment of their dopings and by suitable healing, and are balanced by laser trimming.

Diffusion of arsenic in bilayer polycrystalline silicon films

Abstract: The diffusion of arsenic in polycrystalline silicon films is studied using a novel bilayer structure consisting of a polycrystalline silicon layer, in situ doped with arsenic, deposited on top of an undoped polycrystalline silicon layer. This technique avoids the complication of structural changes resulting from the ion implantation doping that has been employed in other investigations. The diffusivity is measured for the relatively low temperature range 700–850 °C and is described by the relation D=10 exp (−3.36/kT)cm2/s. The average deviation from this relation of the measurements from samples prepared in two different deposition systems is less than 20%. The values are about three orders of magnitude greater than the intrinsic diffusivity of arsenic in the silicon lattice. It is proposed that the diffusion takes place along grain boundaries and that certain background impurities in the grain boundaries are responsible for the large variation in the values that are reported in the literature.

Electronic transport properties of TiSi2 thin films

Abstract: High purity, single‐phase TiSi2 thin films were prepared by deposition of titanium onto polycrystalline silicon layers followed by furnace annealing. Measurements of the temperature dependence of resistivity show that the material behaves as a classical metallic conductor, with an intrinsic resistivity proportional to temperature and having a room temperature value of ∼11μΩ cm. Geometrical magnetoresistance measurements on Corbino disk samples give a ‘‘representative’’mobility value (∼60 cm2/V‐s at room temperature) that mirrors the temperature dependence of resistivity. The very small Hall effect, taken together with a sizeable physical magnetoresistance, indicates the material is predominantly an electron conductor with a spectrum of mobility values for carriers on the Fermi surface because an isotropic, two‐band model cannot quantitatively account for the data.

Method for nucleating and growing tungsten films

Abstract: Adherent deposits of tungsten are formed on receiving surfaces by preparing the receiving surface and thereafter forming a thin deposit of polycrystalline silicon on the surface The surface and the deposited polycrystalline silicon is then exposed to a hydrogen containing tungsten fluoride gas at a suitable temperature to induce the adherent growth of tungsten film on the surface by reaction of the silicon with the tungsten fluoride gas It is possible to form the polycrystalline silicon in a pattern on the surface and to form the tungsten deposit in the pattern in which the polycrystalline silicon had been deposited

Interactions in metallization systems for integrated circuits

Abstract: Conductive films are required to provide interconnection between contacts on the devices and between devices and outside world. Aluminum has been the most popular metal. Conducting polycrystalline silicon (polysilicon) film has been the conductor for gate and interconnection. PtSi has been used as a Schottky barrier contact and also simply as a contact for deep junctions. Refractory silicides are now used as gate and interconnection metallizations. Titanium/palladium/gold or titanium/platinum/gold beam lead technology was successful in providing high reliability connection to the outside world. Several similar schemes have been suggested or used in the integrated circuits. A considerable amount of work is carried out in adopting such a metallization scheme in integrated circuits. These include a study of metallurgical and chemical interactions between various materials and effect of such interactions on the properties of the materials and devices. In this paper a review of these studies will be presented.

Method for source/drain self-alignment in stacked CMOS

Abstract: In stacked CMOS, a single gate in first level polycrystalline silicon is used to address both an N-channel device in the substrate and an overlaid p-channel device. The p-channel device has self-aligned source and drain regions formed by diffusing a dopant from doped regions underlying them. The doped regions are formed by planarizing a doped insulating layer, and etching the doped layer back to the upper level of the gate prior to deposition of a second polysilicon layer.

A model of electrical conduction in polycrystalline silicon

Abstract: This paper presents a modified version of the conduction model for polycrystalline silicon which includes the thermionic field emission of carriers through the space-charge potential barrier, carrier tunneling through the grain-boundary rectangular potential barrier after being thermally emitted over the space-charge barriers, and the thermionic emission of carriers over these barriers. It is found that if the height of the space-charge potential barrier is much smaller than the height of the grain-boundary barrier, the conduction is mainly controlled by the second mechanism. As grain size decreases, the contribution to current by second mechanism increases. The model predicts that the grain-boundary width in phosphorus-doped polycrystalline silicon film is a strong function of dopant concentration at intermediate dopant concentrations, while the grain-boundary width in boron-doped polycrystalline silicon is independent of dopant concentration in the range of 1016to 5 × 1019cm-3. Considering the potential drop across the grain-boundary barriers, the computed variation of resistivity with dopant concentration for different grain sizes is found to agree with the available experimental data.

Buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer

Abstract: The disclosure relates to a method for realizing a fully functional buried level of interconnect using only a single level of a silicide over N+ polycrystalline silicon, the latter serving as the gate material for both the N channel and P channel devices formed.

Method of manufacturing semiconductor integrated circuit devices having dielectric isolation regions

Abstract: A method of making semiconductor integrated circuit devices with narrow and deep isolation regions of polycrystalline silicon and wide and thick isolation regions of thermally grown silicon oxide. A multi-layer of a first silicon nitride layer, a polycrystalline silicon layer, a second silicon nitride layer and a silicon oxide layer are formed on a semiconductor body. A photoresist layer is applied on the surface of the silicon oxide layer. An opening is formed in the photoresist layer and the multi-layer. The silicon oxide layer under the photoresist layer is side-etched through the opening. The exposed polycrystalline layer is converted into another silicon oxide layer. Another opening surrounding the silicon oxide layer is formed to expose surfaces of the semiconductor body. Deep grooves are formed in the semiconductor body.

Laser make-link programming of semiconductor devices

Abstract: A semiconductor device is programmed by a laser beam which causes an electrical short between two conductors on a silicon substrate, as by melting an insulator between the conductors and fusing or shorting the conductors. The conductors may be first and second levels of polycrystalline silicon in a standard double-level poly process, and the insulator is thermal silicon oxide. The laser beam is focused on an area which is shielded from the silicon substrate by the first-level conductor, so heating and disruption of the substrate or underlying circuit structure is minimized.

Monolithic integrated circuit structure and method of fabrication

Abstract: Method of forming a substrate for fabricating CMOS FET's by forming sections of N and P-type conductivity in a body of silicon. Grooves are etched in the N and P-type sections to produce N and P-type sectors encircled by grooves. The surfaces of the grooves are oxidized, the grooves are filled with polycrystalline silicon, and exposed surfaces of the polycrystalline silicon are oxidized to form barriers which encircle the sectors and electrically isolate them. Shallow trenches are etched in regions of the body outside the N and P-type sectors and the trenches are filled with regions of silicon dioxide. A pair of complementary FET's are fabricated in the two sectors and a metal interconnection between them overlies a portion of a region of silicon dioxide.

Semiconductor device with deep grip accessible via the surface and process for manufacturing same

Abstract: A semiconductor device with deep grid accessible via the surface having a silicon substrate and comprising U-shaped grooves. The upper parts of the side walls of these grooves are insulated by a silica layer and the lower parts of these grooves connect up with overdoped zones. Polycrystalline silicon provides ohmic contact between selected positions on the upper face of the transistor and the grid layer.

Method for integrated circuit device isolation

Abstract: The disclosure relates to a method manufacturing semiconductor devices which minimizes encroachment by utilizing a polycrystalline silicon (polysilicon) layer over a grown oxide on the substrate with a nitride layer positioned above the polysilicon layer. A patterned resist is then formed in the active device regions and the device is then etched in the regions where the resist has not been applied to remove the nitride layer, the polysilicon layer and the oxide layer in one embodiment and, in a second embodiment, also removes a portion of the substrate. The silicon substrate portion which is exposed is then oxidized by field oxidation to provide, in the first embodiment, an oxide layer which rises above the level of the polysilicon layer and, in the second embodiment, to a point equal to or slightly above the oxide layer beneath the polysilicon layer. The nitride and polysilicon layer are then stripped or, alternatively, the polysilicon layer can be oxidized. The oxide layer in the active region is then etched back to the silicon layer and a gate oxide is then formed in the active region in standard manner. The processing then continues in standard manner to provide an MOS or bipolar device. The above noted procedure provides active semiconductor devices with essentially no encroachment or "bird beak" problem present. The procedure can also be used with elimination of the first oxide layer over the substrate.