Showing papers on "Polycrystalline silicon published in 1986"

Resonant-microbridge vapor sensor

Abstract: A novel integrated vapor sensor is described that incorporates a polycrystalline silicon microbridge coated with a thin polymer film The microbridge is resonated electrostatically and its vibration is detected capacitively using an integrated NMOS circuit Vapor uptake by the polymer increases the mass-loading on the microbridge, thereby perturbing the first resonant frequency of the microbridge In the prototype device, a 150-nm-thick layer of negative photoresist coats a 153-µm-long 135-µm-thick polycrystalline silicon microbridge The phase between the excitation and output voltages at resonance is monitored as the sensor output signal Exposure to saturated xylene vapor produces a phase shift of -8° with a response time of less than 7 min

Determination of gap state density in polycrystalline silicon by field‐effect conductance

Abstract: We have obtained the density of states (DOS) in polycrystalline silicon from the analysis of the field‐effect conductance. The DOS exhibits a U‐shaped distribution with an exponential band tail. The method is very sensitive and accounts for the effect of film morphology and differences in device processing (e.g., post‐hydrogenation).

Sealed cavity semiconductor pressure transducers and method of producing the same

Abstract: Sealed cavity structures suitable for use as pressure transducers are formed on a single surface of a semiconductor substrate (20) by, for example, deposit of a polycrystalline silicon layer (32) from silane gas over a relatively large silicon dioxide post (22) and smaller silicon dioxide ridges (27) leading outwardly from the post. The polysilicon layer is masked and etched to expose the outer edges of the ridges and the entire structure is then immersed in an etchant which etches the silicon dioxide forming the ridges and the post but not the substrate (20) or the deposited polysilicon layer (32). A cavity structure results in which channels (35) are left in place of the ridges and extend from communication with the atmosphere to the cavity (36) left in place of the post. The cavity (36) may be sealed off from the external atmosphere by a second vapor deposition of polysilicon or silicon nitride, which fills up and seals off the channels (35), or by exposing the substrate and the structure thereon to an oxidizing ambient which results in growth of silicon dioxide in the channels sufficient to seal off the channels. Deflection of the membrane spanning the cavity occurring as a result of pressure changes, may be detected, for example, by piezoresistive devices formed on the membrane.

Manufacture of semiconductor device

Abstract: PURPOSE:To make it possible to form a resistor or a wiring beneath an element region in a dielectric isolating structure by surrounding the entire surface of a single crystal region which is isolated with a non-single crystal silicon that is embedded in a groove formed in a semiconductor substrate with a three-layer structure of an insulating film, a conductor layer and an insulating film. CONSTITUTION:An isolating groove 12 is formed by selective etching (isotropic etching) by using KOH in a single-crystal silicon substrate 11. An insulating SiO2 film 13 is deposited on the entire surface. Then, a wiring layer 14 having the thickness of 100-1,000Angstrom is formed with conductive material (e.g., high- melting-point metal such as nickel chromium) by an evaporating method. An insulating film SiO2 film 15 is deposited again. Then a supporting layer 16 is formed by growing polycrystalline silicon. Etching is performed to a position shown with a broken line. A dielectric isolated substrate having a single crystal region 17 that is isolated with the SiO2 film 13 and the conductive layer 14 that is isolated with the insulating SiO2 films 13 and 15 can be obtained without using especially complicated steps. When the conductive layer 14 is utilized as a resistor, polycrystalline silicon whose resistivity is controlled by ion implantation can be used.

Semiconductor device with protective means against overheating

Abstract: A semiconductor substrate has a power region and a control region. The control region is located in the center portion of the substrate, and the power region surrounds the control region and is separated therefrom. A vertical type, MOS transistor, i.e., an active semiconductor element, is formed on the power region. An insulation film is formed on part of the control region. A polycrystalline silicon diode, which functions as a heat-sensitive element, is formed on the insulation film. A control section comprising a lateral type, MOS transistor is also formed on the control region. The lateral type, MOS transistor is connected to receive a signal form the polycrystalline silicon diode. Further, a polycrystalline silicon resistor, which determines a circuit constant, is formed on the insulation film. The MOS transistor protects the active semiconductor element in response to a signal supplied from the heat-sensitive element showing that the temperature of the semiconductor substrate has risen above a predetermined value. For example, the active semiconductor element may be disabled until the detected temperature drops below a predetermined value.

Thin film FET doped with diffusion inhibitor

Abstract: The present invention relates to a semiconductor device including a MOS transistor which is formed with a source region, a drain region and a channel region by the use of polycrystalline silicon, and a method of manufacturing the semiconductor device. Ions of carbon, oxygen or/and nitrogen are introduced into a polycrystalline silicon layer over the whole area thereof, and restrain conductive ions in the source and drain regions from diffusing into the channel region.

Polycrystalline-silicon device technology for large-area electronics

Abstract: The process sequence used to fabricate post-hydrogenated polycrystalline silicon thin-film devices has a dramatic impact on performance. A near-optimal process for devices that have hole mobilities of up to 50 cm2/V . s and electron mobilities of 70 cm2/V . s is demonstrated. These observed mobilities are substantially higher than previous literature reports. Implantation of boron or phosphorus into the polycrystalline-silicon device channel after the gate-oxidation step allows threshold-voltage tailoring for achievement of either enhancement-or depletion-mode operation of n- and p-channel devices. These results indicate that CMOS or NMOS logic could be fabricated using polycrystalline-silicon devices. Devices with steam-grown gate oxides have reduced channel mobility in comparison with devices oxidized in dry O 2 at the same temperature. Possible mechanisms for the variation in performance with oxidation conditions are discussed.

Micromachining and Micropackaging of Transducers

Abstract: I. Overview. Silicon micromachining and its application to high performance integrated sensors (K.D. Wise). Epoxy encapsulants, adhesives and specialty polymers for microelectronic applications (D.R. Owen, R.M. Zone). II. Micropackaging and Encapsulation. Packaging considerations for the microdielectrometer and related chemical sensors (S.D. Senturia, D.R. Day). Bonding techniques for microsensors (W.H. Ko et al.). Corrosion protection for implantable integrated sensors by CO 2 laser processing for glass and silicon (Y. Naruse et al.). Electrical contacts to implantable integrated sensors by CO 2 laser-drilled bias through glass (L. Bowman et al.). Packaging of an intracranial pressure telemetering unit for chronic implantation (T. Spear et al.). III. Etching Techniques. Orientations of the third kind: the coming of age of (110) silicon (D.L. Kendall,G.R. de Guel). The use of a certain fluorocarbon surfactant and fluorocarbon conformal coating improves KOH silicon etching quality (B. Block, M. Sierakowsky). Ellipsometric study of bias-dependent etching and the etch-stop mechanism for silicon in aqueous KOH (E.D. Palik et al.). Submicron accuracies in anisotropic etched silicon piece parts - a case study (T.L. Poteat). Deep etching of silicon using plasma (C.D. Fung, J.R. Linkowski). IV. Microstructures. Microfabrication technology for microsensors (L.T. Romankiw). Polycrystalline silicon microstructures (R.T. Howe). Micromachining technology for flexible sensor arrays (P.W. Barth). Planar processed, integrated displacement sensors (H. Guckel et al.). Electrochemical shaping of three dimensional continuously modulated surface contours (U. Langau et al.). V. Applications. A microtransducer for air flow and differential pressure sensing applications (G.B. Hocker et al.). V-groove capillary for low flow control and measurement (M.G. Guvenc). Fabrication of biomedical sensors using thin and thick film microelectronic technology (M.R. Neuman, C.-C. Liu). Microelectronic microelectrode glucose sensor at low potentials (L.-T. Chan et al.). Potential applications of micromachining to semiconductor chemical sensors (P.W. Cheung).

Process for preparing a silicon carbide device

Abstract: A silicon carbide layer(s) is provided on a silicon substrate. If necessary, a desired pattern of the silicon carbide layer(s) is allowed to remain, while the other portion(s) is embedded with SiO2. If necessary, the silicon carbide layer(s) may be constituted of a barrier layer and a device-forming layer. A layer capable of easily forming an insulating layer, such as a polycrystalline silicon layer, is provided on the silicon carbide layer to form first electrodes, followed by insulation of the surface, such as oxidation of the surfaces of the first electrodes and the silicon carbide layer. Second electrodes are further formed in self alignment by utilizing the insulating layer of the surface of the first electrodes. This process is useful in preparation of a silicon carbide device capable of operation at high temperatures.

Multilayer semi-insulating film for hermetic wafer passivation and method for making same

Abstract: A film for hermetically passivating monocrystalline silicon includes sequential layers of undoped amorphous silicon, oxygen doped polycrystalline silicon, silicon rich oxynitride, and silicon nitride, and may be overlaid with an organic bulk dielectric such as polyimide The inorganic film accurately sets the monocrystalline surface Fermi potential, independent of ambient electrical, mechanical, thermal, ionic, and moisture conditions A method for depositing the amorphous silicon and the oxygen doped polycrystalline silicon layers of the film includes sequentially reacting monosilane in an inert carrier gas, such as helium or argon, and nitrous oxide The layers are blended by varying the deposition temperature, the nitrous oxide flow rate, the monosilane flow rate, the monosilane dilution, and the inert carrier gas species The layers are annealed to locally segregate the oxygen, to grow the grains to the proper size, and to set the final recombination velocity of the monocrystalline region

Semiconductor device including a semiconductor layer having a polycrystalline silicon film with selected atomic constituency

Abstract: A semiconductor device mainly comprises a semiconductor layer of a polycrystalline silicon film containing at least one atom selected from the group consisting of carbon, sulfur, nitrogen and oxygen as a constituent.

Method of making a bipolar semiconductor device

Abstract: An n-type buried layer is selectively formed in a surface region of a p-type semiconductor substrate. At least one insulating film is formed on the semiconductor substrate. A first opening is formed on the buried layer in the insulating film. An n-type polycrystalline silicon layer is formed in the first opening connected to the buried layer. A second opening is formed on the buried layer of the insulating film. An n-type monocrystalline silicon layer is formed in the second opening connected to the buried layer. A p-type base region is formed in the monocrystalline silicon layer and a collector region is formed in the remaining portion of the monocrystalline silicon layer. An emitter region is selectively formed in the base region.

Manufacture of semiconductor device

Abstract: PURPOSE:To coat the roughened surface of the semiconductor substrate with an insulating film at a comparatively low temperature and to make gentle the surface by a method wherein an amorphous silicon film with a good covering property is deposited on the insulating film in an atmosphere of plasma CONSTITUTION:Impurity diffusion layers 2 are formed in a single crystal silicon substrate 1 and a silicon oxide film 3 is formed on the single crystal silicon substrate 1 Moreover, after that, polycrystalline silicon wiring layers 4, which act as the gate of a transistor and a wiring, are formed The state of the surface of the semiconductor substrate in this stage is in a state that a comparatively steep roughness of a thickness of 2-3,000Angstrom to 7-8,000Angstrom is formed on the surface An amorphous silicon film 5 of a thickness of about 4,000Angstrom is deposited by decomposing silane gas in an atmosphere of plasma in such a way that this roughness is sufficiently coated with the amorphous silicon film 5 After this, the amorphous silicon film 5 is made to completely oxidize by performing a wet oxidation at about 600 degC to form a silicon oxide film 6

Method of manufacturing a semiconductor device using amorphous silicon as a mask

Abstract: A method of manufacturing a semiconductor device has the steps of forming an insulating film on a semiconductor substrate, forming a polycrystalline silicon layer on the insulating film, converting either all of the polycrystalline silicon layer or a portion of predetermined thickness of the polycrystalline silicon layer into an amorphous silicon layer, patterning the polycrystalline silicon layer, either all of which or a portion of predetermined thickness of which has been converted into an amorphous silicon layer, and ion-implanting an impurity in the semiconductor substrate using the patterned layer as a mask.

Thermal stability of TiSi2 on mono‐ and polycrystalline silicon

Abstract: Thermal stability of TiSi2 on mono‐ and polycrystalline silicon was investigated by cross‐sectional transmission electron microscopy and high‐resolution electron energy loss spectroscopy. Additional heat treatments after silicide formation result in a rough silicide/silicon interface, discontinuity of the metal silicide film, and a penetration of silicide into silicon/polycrystalline silicon substrates. Plausible explanations for these observations are presented.

Method for making electrically programmable memory device by doping the floating gate by implant

Abstract: In the present invention, asperity in the floating gate of an EPROM or EEPROM device is reduced. An improved process for fabricating ultrahigh coupling interpoly isolation dielectrics comprising a structure of oxide-nitride-oxide is disclosed. The first oxide is grown on undoped LPCVD polycrystalline silicon (polysilicon) to reduce the grain boundary-oxidation enhancement effect at the interface of floating gate polysilicon and interpoly oxide. This results in much higher breakdown capability of interpoly dielectrics. As a consequence, the shrinkage of the interpoly electrical thickness to an extent far beyond current limitation becomes possible. Implanted dopants through interpoly oxide into the floating gate polysilicon also eliminate the oxidation enhanced diffusion from conventional POCl 3 doped polysilicon into tunnel oxide. The phosphorus induced trap in the tunnel oxide region are reduced. The EEPROM threshold window can remain open beyond 10 6 cycles.

High efficiency polycrystalline silicon solar cells using phosphorus pretreatment

Abstract: Recent improvements in crystalline silicon solar cell energy conversion efficiency to beyond 20% have been obtained by combining surface oxide passivation with high quality, low resistivity substrates. The objective of the present work was to evaluate the effectiveness of these techniques in improving efficiency on lower quality cast polycrystalline silicon. Due to the poorer crystallographic quality and higher levels of secondary impurities, an additional phosphorus pretreatment was found to reliably improve the performance of the polycrystalline cells above those fabricated without this pretreatment. Cell energy conversion efficiencies were notably higher than previously reported for the present material with values in the 15.3–16.0% range obtained for p‐type substrates of 0.1–1 Ω cm resistivity.

Manufacture of semiconductor device

Abstract: PURPOSE:To form an element whose resistance is lower than a tungsten or molybdenum polycide LDD type MOS transistor, by a method wherein, after polycrystalline silicon is deposited, only said polycrystalline silicon is selectively wet-etched, and metal is selectively deposited only on the surface of polycrystalline silicon after the etching. CONSTITUTION:In the case of manufacturing a semiconductor device having a MOS field-effect transistor whose gate electrode has a lamination structure of a lower part polycrystalline silicon layer 38 and an upper part metal layer 35, polycrystalline silicon 34 is deposited, and then only the polycrystalline silicon 34 is selectively wet-etched. Only on the surface of the polycrystalline silicon 34 after the etching, metal 35 is selectively deposited. For example, after a polycrystalline Si gate LDD type MOS transistor is formed by an ordinary method, a gate electrode 34 is etched to be 2000Angstrom thick by using etching agent whose main component is ethylenediamine-pyrocatechol. An Al layer 35 is deposited on the surface of the polycrystalline Si 34, by a chemical vapor deposition method using alkyl aluminum hydride and hydrogen.

Method of providing buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer

Abstract: The disclosure relates to a method for realizing a fully functional buried level of interconnect using only a single level of a silicide over N+ polycrystalline silicon, the latter serving as the gate material for both the N channel and P channel devices formed.

Leakage current mechanisms in Hydrogen-passivated fine-grain polycrystalline Silicon on insulator MOSFET's

Abstract: In this paper we identify various sources of leakage current in thin-film silicon on insulator (SOI) MOSFET's made in hydrogen-passivated small-grain polycrystalline silicon. The action of a parasitic bipolar transistor that can amplify the leakage current due to the thermally generated carriers has been confirmed and characterized. A current gain (β) of more than 6 for the parasitic bipolar transistor has been experimentally measured in accumulation-mode devices, in spite of the presence of a large number of defects. This high gain is attributed to the presence of the vertical electric field, which separates the carriers, thus reducing the probability of recombination. The presence of field-enhanced generation is shown to be the cause of the observed increase in the leakage current with positive front- or back-gate bias for p-channel accumulation-mode devices. Reasonable agreement has been obtained between experimental data and theory based on field-enhanced generation due to Poole-Frenkel barrier lowering.

Manufacture of semiconductor device

Abstract: PURPOSE:To form high melting point metal silicide with a better close adhering ability on a diffusion layer for source and drain regions of a MOS device, by forming a gate electrode, by depositing silicide, and by etching the silicide portion having silicon underlaid by using a mask of a silicon oxide film. CONSTITUTION:On the surface of a silicon substrate 11, a field oxide film 12, gate oxide film 13, polycrystalline silicon layer 14 and polycrystalline silicon gate electrode 14' are formed. After a CVD-SiO2 film is formed over the entire face, reactive ion etching forms side walls 15. Next, an N diffusion layer 16 is formed, high melting point metal silicide 17 is formed over the entire face, and then thermal oxidation forms a silicon oxide film 18. Thereafter, the portion of the silicon oxide film 18 under which there does not exist silicon is removed, only the silicon oxide film 18 on the diffusion layer 16 for the source and drain regions and on the gate electrode 14' is left, and the silicide 17 is etched using a mask of this silicon oxide film 18. Next, a PSG film 19 is evaporated, contact holes 20 are formed, and an Al film is evaporated over the entire face and is patterned to form Al wiring 21.

Method of forming multiple nitride coating on silicon

Abstract: In an integrated circuit process a composite dielectric layer is formed on a monocrystalline, polycrystalline or amorphous silicon substrate by thermally growing a first silicon nitride layer from a surface layer of the silicon and then depositing a layer of amorphous or polycrystalline silicon. A second nitride layer is thermally grown from the deposited silicon to form a nitride-silicon-nitride, termed nitsinitride, composite dielectric. At least a top layer of the nitsinitride dielectric can be oxidized to produce an alternative composite dielectric, termed oxidized nitsinitride. Variation of the thickness of the dielectric layers and/or repeating the layering process sequence results in composite dielectrics of different thicknesses and dielectric properties.

Polycrystalline silicon thin-film transistors on a novel 800°C glass substrate

Abstract: A new polycrystalline silicon thin-film transistor (TFT) technology using a potentially low-cost glass substrate is reported. Transistors are made using modified conventional n-channel MOS processes at temperatures of 800°C or less, with a final hydrogen implantation step. These transistors show leakage currents of 2 × 10-11A/µm of channel width, ON-to-OFF current ratios of 1 × 104at V ds = 9.0 V, and good dc stability. This combination of polycrystalline silicon transistors on potentially low-cost glass substrates offers a new option in the choice of active device technology for large-area flat-panel liquid crystal displays (LCD's).

Optical waveguide utilizing an antiresonant layered structure

Abstract: A planar silicon dioxide waveguide with low loss for the TE mode has been built on a silicon wafer by separating the waveguide from the substrate with a relatively thin layer of polycrystalline silicon and a layer of silicon dioxide having a combined thickness less than that of the waveguide. The separating layers provide a high antiresonant reflectivity which is operative over a broad range of wavelengths.

Anomalous diffusion and gettering of transition metals in silicon

Abstract: By using metallic haze to detect the presence of transition metals in silicon, and rapid thermal annealing to thermally process wafers, anomalous diffusion and gettering of transition metals in silicon have been observed. Gettering is observed over a wide temperature range (300 –1100 °C) and anneal duration (1–300 s). The rapid initial gettering is found to occur over mechanical and laser damaged areas but not over polycrystalline silicon backsealed regions. Surface diffusion is found to dominate over anomalous bulk diffusion at the lower temperatures investigated.

Thermal SiO 2 films on n + polycrystalline silicon: Electrical conduction and breakdown

Abstract: The conduction and breakdown properties of thermally grown SiO 2 films on amorphous-deposited n+polycrystalline silicon (polysilicon) are evaluated using ramped current-voltage ( I-V ) measurements. It is shown that the inferior insulating properties of oxides on polysilicon (polyoxides), when compared to SiO 2 on bulk silicon, can be directly attributed to oxidation-induced interface roughness leading to localized enhancement of the oxide electric field. For example, 16.7-nm-thick polyoxides approach bulk SiO 2 properties since a breakdown field E BD of approximately 9.5 MV . cm-1and an effective barrier height for Fowler-Nordheim tunneling, φ Beff as high as 2.78 eV were measured. Both of these parameters are progressively degraded by increasing polyoxide thickness D OX such that for 165-nm-thick polyoxides E_{BD} \simeq 2.5 MV . cm-1and φ Beff is reduced to as low as 0.83 eV. The measured I-V curves are found to become more polarity dependent with increasing D OX due to a comparatively higher degree of oxidation-induced surface roughening at the lower interface, which renders it more "conductive," with regard to Fowler-Nordheim electron injection, than the upper oxide-polysilicon interface. Certain specific device applications require a relatively "conductive" polyoxide capable of carrying high current densities before failure. Consequently, a polysilicon texturing procedure was developed that has the effect of decreasing φ Beff , increasing breakdown current J BD , and eliminating the polarity dependence of I-V curves for any subsequently formed thin polyoxide. The particular process entails growing a predetermined thickness of "texturing" oxide D teox , and removal prior to formation of the device polyoxide of approximately 25-nm thickness. As D teox is increased from zero to 103 nm, the resultant J BD is found to increase by more than an order of magnitude for both polarities of bias. The corresponding decrease in φ Beff is from 1.7 and 2.4 eV for positive and negative gate bias, respectively, to a polarity-independent value of approximately 1.3 eV.

Ambient and dopant effects on boron diffusion in oxides

Abstract: Diffusion of boron from ion implanted polycrystalline silicon source through 12.5 nm oxides was measured as a function of annealing ambience and doping concentrations of phosphorus or arsenic in the polycrystalline silicon. For comparison, boron ion implanted into 500 nm oxides was also investigated. In both cases, annealing in forming gas (90% N2, 10% H2) increases the diffusion rate of boron over that in nitrogen and the rate increase is the result of a large increase in the pre‐exponential term. Diffusion of ion implanted boron in oxides is much slower than that from an ion implanted polycrystalline silicon source. The lowering of the rate is the result of the five orders of magnitude decrease in the pre‐exponential term, even though concurrently there is also a decrease in the activation energy. Co‐doping of polycrystalline silicon with either phosphorus or arsenic lowers the pre‐exponential term by approximately 10%. Therefore, we conclude that boron diffusion through oxides is entropy dominated.

Stacked static random access memory cell having capacitor

Abstract: A static random access memory cell in which capacitors are electrically connected to storage nodes, so that the memory cell will not suffer from soft error even when it is hit by alpha particles. The memory cell has MOS transistors, capacitors constituted by two polycrystalline silicon layers, and resistors constituted by a polycrystalline silicon layer, that are formed on a semiconductor substrate.

Polycrystalline silicon as a strain gauge material

Abstract: A theoretical model for piezoresistance in both n- and p-type polycrystalline silicon is described. This model considers the contribution to piezoresistance from the grain and the Schottky-type barrier regions around the grain boundaries. Comparison between theory and experiment shows reasonable agreement for both longitudinal and transverse strain measurements. The difference in magnitude between longitudinal and transverse gauge factors depends on texture and is found to be explained by the anisotropy of piezoresistance in silicon. Experimental results for the temperature coefficients of resistance and gauge factor in conjunction with the model for piezoresistance may be used to optimise sensor characteristics within the confines of available processes.